Changeset 40907 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Apr 13, 2012 8:50:14 PM (13 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r40282 r40907 214 214 RT_C_DECLS_BEGIN 215 215 216 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel );217 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel );216 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag); 217 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag); 218 218 PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb); 219 219 PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb); … … 601 601 } 602 602 603 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq )603 static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc) 604 604 { 605 605 /* This is only allowed to be called with a pointer to the host bus. */ … … 620 620 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n", 621 621 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num)); 622 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level );622 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc); 623 623 624 624 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) { … … 628 628 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n", 629 629 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num)); 630 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level );630 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc); 631 631 } 632 632 } else { 633 633 Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n", 634 634 R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq)); 635 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel );635 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc); 636 636 } 637 637 } … … 650 650 * @param iIrq IRQ number to set. 651 651 * @param iLevel IRQ level. 652 * @param uTagSrc The IRQ tag and source ID (for tracing). 652 653 * @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge. 653 654 * In that case uDevFn will be the slot of the bridge which is needed to calculate the 654 655 * PIRQ value. 655 656 */ 656 static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel )657 static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 657 658 { 658 659 PPCIBUS pBus = &pGlobals->PciBus; … … 682 683 * PCI device configuration space). 683 684 */ 684 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE] );685 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc); 685 686 else 686 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1 );687 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc); 687 688 return; 688 689 } … … 732 733 pic_level |= pGlobals->acpi_irq_level; 733 734 734 Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d \n",735 R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level ));736 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level );735 Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n", 736 R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc)); 737 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc); 737 738 738 739 /** @todo optimize pci irq flip-flop some rainy day. */ 739 740 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) 740 pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW );741 pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc); 741 742 } 742 743 } … … 749 750 * @param iIrq IRQ number to set. 750 751 * @param iLevel IRQ level. 751 */ 752 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel) 753 { 754 pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel); 752 * @param uTagSrc The IRQ tag and source ID (for tracing). 753 */ 754 PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 755 { 756 pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc); 755 757 } 756 758 … … 2246 2248 * @param iIrq IRQ number to set. 2247 2249 * @param iLevel IRQ level. 2248 */ 2249 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel) 2250 * @param uTagSrc The IRQ tag and source ID (for tracing). 2251 */ 2252 PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 2250 2253 { 2251 2254 /* … … 2273 2276 2274 2277 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus)); 2275 pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel );2278 pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc); 2276 2279 } 2277 2280 -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r40282 r40907 165 165 166 166 /* Prototypes */ 167 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel); 167 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, 168 int iIrq, int iLevel, uint32_t uTagSrc); 168 169 #ifdef IN_RING3 169 170 static void ich9pcibridgeReset(PPDMDEVINS pDevIns); … … 192 193 } 193 194 194 PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel )195 { 196 ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel );197 } 198 199 PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel )195 PDMBOTHCBDECL(void) ich9pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 196 { 197 ich9pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PICH9PCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc); 198 } 199 200 PDMBOTHCBDECL(void) ich9pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc) 200 201 { 201 202 /* … … 223 224 224 225 AssertMsgReturnVoid(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus)); 225 ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel );226 ich9pciSetIrqInternal(PCIROOTBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc); 226 227 } 227 228 … … 504 505 } 505 506 506 static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int iForcedIrq) 507 static void ich9pciApicSetIrq(PICH9PCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, 508 uint32_t uTagSrc, int iForcedIrq) 507 509 { 508 510 /* This is only allowed to be called with a pointer to the root bus. */ … … 522 524 apic_irq = irq_num + 0x10; 523 525 apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0; 524 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d \n",525 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num ));526 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level );526 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x\n", 527 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc)); 528 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc); 527 529 528 530 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) … … 535 537 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW; 536 538 apic_level = pGlobals->uaPciApicIrqLevels[irq_num] != 0; 537 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",538 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num ));539 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level );539 Log3(("ich9pciApicSetIrq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d uTagSrc=%#x (flop)\n", 540 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num, uTagSrc)); 541 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc); 540 542 } 541 543 } else { 542 Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d\n", 543 R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq)); 544 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel); 545 } 546 } 547 548 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel) 544 Log3(("ich9pciApicSetIrq: (forced) %s: irq_num1=%d level=%d acpi_irq=%d uTagSrc=%#x\n", 545 R3STRING(pPciDev->name), irq_num1, iLevel, iForcedIrq, uTagSrc)); 546 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), iForcedIrq, iLevel, uTagSrc); 547 } 548 } 549 550 static void ich9pciSetIrqInternal(PICH9PCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, 551 int iIrq, int iLevel, uint32_t uTagSrc) 549 552 { 550 553 … … 554 557 { 555 558 PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns); 556 MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel );559 MsiNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc); 557 560 } 558 561 … … 560 563 { 561 564 PPDMDEVINS pDevIns = pGlobals->aPciBus.CTX_SUFF(pDevIns); 562 MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel );565 MsixNotify(pDevIns, pGlobals->aPciBus.CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc); 563 566 } 564 567 return; … … 582 585 * PCI device configuration space). 583 586 */ 584 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, PCIDevGetInterruptLine(pPciDev));587 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, -1, iLevel, uTagSrc, PCIDevGetInterruptLine(pPciDev)); 585 588 else 586 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);589 ich9pciApicSetIrq(pBus, uDevFn, pPciDev, iIrq, iLevel, uTagSrc, -1); 587 590 } 588 591 } -
trunk/src/VBox/Devices/Bus/MsiCommon.cpp
r36663 r40907 103 103 104 104 #ifdef IN_RING3 105 void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, uint32_t u32Address, uint32_t val, unsigned len) 105 void MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, 106 uint32_t u32Address, uint32_t val, unsigned len) 106 107 { 107 108 int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset; … … 169 170 { 170 171 Log(("msi: notify earlier masked pending vector: %d\n", uVector)); 171 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH );172 MsiNotify(pDevIns, pPciHlp, pDev, uVector, PDM_IRQ_LEVEL_HIGH, 0 /*uTagSrc*/); 172 173 } 173 174 } … … 271 272 } 272 273 273 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel )274 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel, uint32_t uTagSrc) 274 275 { 275 276 AssertMsg(msiIsEnabled(pDev), ("Must be enabled to use that")); … … 304 305 305 306 Assert(pPciHlp->pfnIoApicSendMsi != NULL); 306 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value );307 } 307 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc); 308 } -
trunk/src/VBox/Devices/Bus/MsiCommon.h
r36663 r40907 37 37 38 38 /* Device notification (aka interrupt). */ 39 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel );39 void MsiNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel, uint32_t uTagSrc); 40 40 41 41 #ifdef IN_RING3 … … 54 54 55 55 /* Device notification (aka interrupt). */ 56 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel );56 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel, uint32_t uTagSrc); 57 57 58 58 #ifdef IN_RING3 -
trunk/src/VBox/Devices/Bus/MsixCommon.cpp
r39135 r40907 109 109 { 110 110 if (msixIsPending(pDev, iVector) && !msixIsVectorMasked(pDev, iVector)) 111 MsixNotify(pDevIns, pPciHlp, pDev, iVector, 1 /* iLevel */ );111 MsixNotify(pDevIns, pPciHlp, pDev, iVector, 1 /* iLevel */, 0 /*uTagSrc*/); 112 112 } 113 113 … … 239 239 } 240 240 241 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel )241 void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPCIDEVICE pDev, int iVector, int iLevel, uint32_t uTagSrc) 242 242 { 243 243 AssertMsg(msixIsEnabled(pDev), ("Must be enabled to use that")); … … 265 265 uint32_t u32Value = msixGetMsiData(pDev, iVector); 266 266 267 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value );267 pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc); 268 268 } 269 269 -
trunk/src/VBox/Devices/PC/DevAPIC.cpp
r40280 r40907 55 55 #include "VBoxDD2.h" 56 56 #include "DevApic.h" 57 57 58 58 59 /******************************************************************************* … … 338 339 /** Timer description timer. */ 339 340 R3PTRTYPE(char *) pszDesc; 341 342 /** The IRQ tags and source IDs for each (tracing purposes). */ 343 uint32_t auTags[256]; 344 340 345 # ifdef VBOX_WITH_STATISTICS 341 346 # if HC_ARCH_BITS == 32 … … 436 441 437 442 static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s); 438 static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode );443 static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode, uint32_t uTagSrc); 439 444 static bool apic_update_irq(APICDeviceInfo* pDev, APICState *s); 440 445 … … 530 535 PCVMCPUSET pDstSet, uint8_t delivery_mode, 531 536 uint8_t vector_num, uint8_t polarity, 532 uint8_t trigger_mode )533 { 534 LogFlow(("apic_bus_deliver mask=%R[vmcpuset] mode=%x vector=%x polarity=%x trigger_mode=%x \n",535 pDstSet, delivery_mode, vector_num, polarity, trigger_mode ));537 uint8_t trigger_mode, uint32_t uTagSrc) 538 { 539 LogFlow(("apic_bus_deliver mask=%R[vmcpuset] mode=%x vector=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n", 540 pDstSet, delivery_mode, vector_num, polarity, trigger_mode, uTagSrc)); 536 541 537 542 switch (delivery_mode) … … 543 548 { 544 549 APICState *pApic = getLapicById(pDev, idDstCpu); 545 apic_set_irq(pDev, pApic, vector_num, trigger_mode );550 apic_set_irq(pDev, pApic, vector_num, trigger_mode, uTagSrc); 546 551 } 547 552 return VINF_SUCCESS; … … 585 590 586 591 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet); 587 apic_set_irq(pDev, pCurApic, vector_num, trigger_mode );592 apic_set_irq(pDev, pCurApic, vector_num, trigger_mode, uTagSrc); 588 593 APIC_FOREACH_END(); 589 594 return VINF_SUCCESS; … … 830 835 vector, 831 836 0 /* Polarity - conform to the bus */, 832 0 /* Trigger mode - edge */); 837 0 /* Trigger mode - edge */, 838 0 /*uTagSrc*/); 833 839 APIC_UNLOCK(pDev); 834 840 break; … … 1077 1083 PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, 1078 1084 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity, 1079 uint8_t u8TriggerMode )1085 uint8_t u8TriggerMode, uint32_t uTagSrc) 1080 1086 { 1081 1087 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); 1082 1088 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect))); 1083 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x \n",1084 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode ));1089 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x uTagSrc=%#x\n", 1090 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc)); 1085 1091 VMCPUSET DstSet; 1086 1092 return apic_bus_deliver(pDev, apic_get_delivery_bitmask(pDev, u8Dest, u8DestMode, &DstSet), 1087 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode );1093 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc); 1088 1094 } 1089 1095 … … 1269 1275 } 1270 1276 1271 static void apic_set_irq(APICDeviceInfo *pDev, APICState* s, int vector_num, int trigger_mode) 1272 { 1273 LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode)); 1277 static void apic_set_irq(APICDeviceInfo *pDev, APICState* s, int vector_num, int trigger_mode, uint32_t uTagSrc) 1278 { 1279 LogFlow(("CPU%d: apic_set_irq vector=%x trigger_mode=%x uTagSrc=%#x\n", s->phys_id, vector_num, trigger_mode, uTagSrc)); 1280 1274 1281 Apic256BitReg_SetBit(&s->irr, vector_num); 1275 1282 if (trigger_mode) … … 1277 1284 else 1278 1285 Apic256BitReg_ClearBit(&s->tmr, vector_num); 1286 1287 if (!s->auTags[vector_num]) 1288 s->auTags[vector_num] = uTagSrc; 1289 else 1290 s->auTags[vector_num] |= RT_BIT_32(31); 1291 1279 1292 apic_update_irq(pDev, s); 1280 1293 } … … 1368 1381 { 1369 1382 int dest_shorthand = (s->icr[0] >> 18) & 3; 1370 LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x \n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));1383 LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode)); 1371 1384 1372 1385 VMCPUSET DstSet; … … 1420 1433 1421 1434 return apic_bus_deliver(pDev, &DstSet, delivery_mode, vector_num, 1422 polarity, trigger_mode );1423 } 1424 1425 1426 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns )1435 polarity, trigger_mode, 0 /* uTagSrc*/); 1436 } 1437 1438 1439 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc) 1427 1440 { 1428 1441 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); … … 1455 1468 if (s->tpr && (uint32_t)intno <= s->tpr) 1456 1469 { 1470 *puTagSrc = 0; 1457 1471 Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff)); 1458 1472 return s->spurious_vec & 0xff; 1459 1473 } 1474 1460 1475 Apic256BitReg_ClearBit(&s->irr, intno); 1461 1476 Apic256BitReg_SetBit(&s->isr, intno); 1477 1478 *puTagSrc = s->auTags[intno]; 1479 s->auTags[intno] = 0; 1480 1462 1481 apic_update_irq(pDev, s); 1463 LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno)); 1482 1483 LogFlow(("CPU%d: apic_get_interrupt: returns %d / %#x\n", s->phys_id, intno, *puTagSrc)); 1464 1484 return intno; 1465 1485 } … … 1679 1699 if (!(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { 1680 1700 LogFlow(("apic_timer: trigger irq\n")); 1681 apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE );1701 apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE, 0 /*uTagSrc*/); 1682 1702 1683 1703 if ( (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) -
trunk/src/VBox/Devices/PC/DevIoApic.cpp
r40280 r40907 87 87 uint32_t irr; 88 88 uint64_t ioredtbl[IOAPIC_NUM_PINS]; 89 /** The IRQ tags and source IDs for each pin (tracing purposes). */ 90 uint32_t auTagSrc[IOAPIC_NUM_PINS]; 89 91 90 92 /** The device instance - R3 Ptr. */ … … 157 159 else 158 160 vector = entry & 0xff; 161 uint32_t uTagSrc = pThis->auTagSrc[vector]; 162 pThis->auTagSrc[vector] = 0; 159 163 160 164 int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns), … … 164 168 vector, 165 169 polarity, 166 trig_mode); 170 trig_mode, 171 uTagSrc); 167 172 /* We must be sure that attempts to reschedule in R3 168 173 never get here */ … … 174 179 175 180 176 static void ioapic_set_irq(void *opaque, int vector, int level )181 static void ioapic_set_irq(void *opaque, int vector, int level, uint32_t uTagSrc) 177 182 { 178 183 IOAPICState *pThis = (IOAPICState*)opaque; … … 189 194 { 190 195 pThis->irr |= mask; 196 if (!pThis->auTagSrc[vector]) 197 pThis->auTagSrc[vector] = uTagSrc; 198 else 199 pThis->auTagSrc[vector] = RT_BIT_32(31); 200 191 201 ioapic_service(pThis); 202 192 203 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) 193 204 pThis->irr &= ~mask; … … 202 213 { 203 214 pThis->irr |= mask; 215 if (!pThis->auTagSrc[vector]) 216 pThis->auTagSrc[vector] = uTagSrc; 217 else 218 pThis->auTagSrc[vector] = RT_BIT_32(31); 219 204 220 ioapic_service(pThis); 205 221 } … … 372 388 } 373 389 374 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel )390 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc) 375 391 { 376 392 /* PDM lock is taken here; */ /** @todo add assertion */ 377 393 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *); 378 394 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq)); 379 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d \n", iIrq, iLevel));380 ioapic_set_irq(pThis, iIrq, iLevel );381 } 382 383 PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue )395 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc)); 396 ioapic_set_irq(pThis, iIrq, iLevel, uTagSrc); 397 } 398 399 PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc) 384 400 { 385 401 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *); … … 406 422 vector_num, 407 423 0 /* polarity, n/a */, 408 trigger_mode); 424 trigger_mode, 425 uTagSrc); 409 426 /* We must be sure that attempts to reschedule in R3 410 427 never get here */ -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r40280 r40907 51 51 RT_C_DECLS_BEGIN 52 52 53 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel );54 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns );53 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc); 54 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc); 55 55 PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb); 56 56 PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb); … … 109 109 uint8_t elcr_mask; 110 110 /** Pointer to the device instance, R3 Ptr. */ 111 PPDMDEVINSR3 pDevInsR3;111 PPDMDEVINSR3 pDevInsR3; 112 112 /** Pointer to the device instance, R0 Ptr. */ 113 PPDMDEVINSR0 pDevInsR0;113 PPDMDEVINSR0 pDevInsR0; 114 114 /** Pointer to the device instance, RC Ptr. */ 115 PPDMDEVINSRC pDevInsRC; 116 RTRCPTR Alignment0; /**< Structure size alignment. */ 115 PPDMDEVINSRC pDevInsRC; 116 RTRCPTR Alignment0; /**< Structure size alignment. */ 117 /** The IRQ tags and source IDs for each (tracing purposes). */ 118 uint32_t auTags[8]; 119 117 120 } PicState; 118 121 … … 164 167 165 168 /* set irq level. If an edge is detected, then the IRR is set to 1 */ 166 static inline void pic_set_irq1(PicState *s, int irq, int level )169 static inline void pic_set_irq1(PicState *s, int irq, int level, uint32_t uTagSrc) 167 170 { 168 171 int mask; … … 194 197 } 195 198 } 199 200 /* Save the tag. */ 201 if (level) 202 { 203 if (!s->auTags[irq]) 204 s->auTags[irq] = uTagSrc; 205 else 206 s->auTags[irq] |= RT_BIT_32(31); 207 } 208 196 209 DumpPICState(s, "pic_set_irq1"); 197 210 } … … 251 264 if (irq2 >= 0) { 252 265 /* if irq request by slave pic, signal master PIC */ 253 pic_set_irq1(&pics[0], 2, 1 );266 pic_set_irq1(&pics[0], 2, 1, pics[1].auTags[irq2]); 254 267 } else { 255 268 /* If not, clear the IR on the master PIC. */ 256 pic_set_irq1(&pics[0], 2, 0 );269 pic_set_irq1(&pics[0], 2, 0, 0 /*uTagSrc*/); 257 270 } 258 271 /* look at requested irq */ … … 352 365 * @param iIrq IRQ number to set. 353 366 * @param iLevel IRQ level. 354 */ 355 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 367 * @param uTagSrc The IRQ tag and source ID (for tracing). 368 */ 369 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc) 356 370 { 357 371 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC); … … 371 385 * line must be held high for a while to avoid spurious interrupts. 372 386 */ 373 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0 );387 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0, uTagSrc); 374 388 pic_update_irq(pThis); 375 389 } 376 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH );390 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc); 377 391 pic_update_irq(pThis); 378 392 } … … 402 416 * @returns Pending interrupt number. 403 417 * @param pDevIns Device instance of the PICs. 404 */ 405 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns) 418 * @param puTagSrc Where to return the IRQ tag and source ID. 419 */ 420 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc) 406 421 { 407 422 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC); … … 431 446 } 432 447 intno = pThis->aPics[1].irq_base + irq2; 433 Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pThis->aPics[1].irq_base, irq2)); 448 *puTagSrc = pThis->aPics[0].auTags[irq2]; 449 pThis->aPics[0].auTags[irq2] = 0; 450 Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc)); 434 451 irq = irq2 + 8; 435 452 } 436 else { 453 else 454 { 437 455 intno = pThis->aPics[0].irq_base + irq; 438 Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pThis->aPics[0].irq_base, irq)); 456 *puTagSrc = pThis->aPics[0].auTags[irq]; 457 pThis->aPics[0].auTags[irq] = 0; 458 Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc)); 439 459 } 440 460 } … … 445 465 irq = 7; 446 466 intno = pThis->aPics[0].irq_base + irq; 467 *puTagSrc = 0; 447 468 } 448 469 pic_update_irq(pThis);
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