Changeset 40907 in vbox for trunk/src/VBox/Devices/PC
- Timestamp:
- Apr 13, 2012 8:50:14 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 77458
- Location:
- trunk/src/VBox/Devices/PC
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevAPIC.cpp
r40280 r40907 55 55 #include "VBoxDD2.h" 56 56 #include "DevApic.h" 57 57 58 58 59 /******************************************************************************* … … 338 339 /** Timer description timer. */ 339 340 R3PTRTYPE(char *) pszDesc; 341 342 /** The IRQ tags and source IDs for each (tracing purposes). */ 343 uint32_t auTags[256]; 344 340 345 # ifdef VBOX_WITH_STATISTICS 341 346 # if HC_ARCH_BITS == 32 … … 436 441 437 442 static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s); 438 static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode );443 static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode, uint32_t uTagSrc); 439 444 static bool apic_update_irq(APICDeviceInfo* pDev, APICState *s); 440 445 … … 530 535 PCVMCPUSET pDstSet, uint8_t delivery_mode, 531 536 uint8_t vector_num, uint8_t polarity, 532 uint8_t trigger_mode )533 { 534 LogFlow(("apic_bus_deliver mask=%R[vmcpuset] mode=%x vector=%x polarity=%x trigger_mode=%x \n",535 pDstSet, delivery_mode, vector_num, polarity, trigger_mode ));537 uint8_t trigger_mode, uint32_t uTagSrc) 538 { 539 LogFlow(("apic_bus_deliver mask=%R[vmcpuset] mode=%x vector=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n", 540 pDstSet, delivery_mode, vector_num, polarity, trigger_mode, uTagSrc)); 536 541 537 542 switch (delivery_mode) … … 543 548 { 544 549 APICState *pApic = getLapicById(pDev, idDstCpu); 545 apic_set_irq(pDev, pApic, vector_num, trigger_mode );550 apic_set_irq(pDev, pApic, vector_num, trigger_mode, uTagSrc); 546 551 } 547 552 return VINF_SUCCESS; … … 585 590 586 591 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet); 587 apic_set_irq(pDev, pCurApic, vector_num, trigger_mode );592 apic_set_irq(pDev, pCurApic, vector_num, trigger_mode, uTagSrc); 588 593 APIC_FOREACH_END(); 589 594 return VINF_SUCCESS; … … 830 835 vector, 831 836 0 /* Polarity - conform to the bus */, 832 0 /* Trigger mode - edge */); 837 0 /* Trigger mode - edge */, 838 0 /*uTagSrc*/); 833 839 APIC_UNLOCK(pDev); 834 840 break; … … 1077 1083 PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, 1078 1084 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity, 1079 uint8_t u8TriggerMode )1085 uint8_t u8TriggerMode, uint32_t uTagSrc) 1080 1086 { 1081 1087 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); 1082 1088 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect))); 1083 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x \n",1084 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode ));1089 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x uTagSrc=%#x\n", 1090 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc)); 1085 1091 VMCPUSET DstSet; 1086 1092 return apic_bus_deliver(pDev, apic_get_delivery_bitmask(pDev, u8Dest, u8DestMode, &DstSet), 1087 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode );1093 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc); 1088 1094 } 1089 1095 … … 1269 1275 } 1270 1276 1271 static void apic_set_irq(APICDeviceInfo *pDev, APICState* s, int vector_num, int trigger_mode) 1272 { 1273 LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode)); 1277 static void apic_set_irq(APICDeviceInfo *pDev, APICState* s, int vector_num, int trigger_mode, uint32_t uTagSrc) 1278 { 1279 LogFlow(("CPU%d: apic_set_irq vector=%x trigger_mode=%x uTagSrc=%#x\n", s->phys_id, vector_num, trigger_mode, uTagSrc)); 1280 1274 1281 Apic256BitReg_SetBit(&s->irr, vector_num); 1275 1282 if (trigger_mode) … … 1277 1284 else 1278 1285 Apic256BitReg_ClearBit(&s->tmr, vector_num); 1286 1287 if (!s->auTags[vector_num]) 1288 s->auTags[vector_num] = uTagSrc; 1289 else 1290 s->auTags[vector_num] |= RT_BIT_32(31); 1291 1279 1292 apic_update_irq(pDev, s); 1280 1293 } … … 1368 1381 { 1369 1382 int dest_shorthand = (s->icr[0] >> 18) & 3; 1370 LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x \n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));1383 LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode)); 1371 1384 1372 1385 VMCPUSET DstSet; … … 1420 1433 1421 1434 return apic_bus_deliver(pDev, &DstSet, delivery_mode, vector_num, 1422 polarity, trigger_mode );1423 } 1424 1425 1426 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns )1435 polarity, trigger_mode, 0 /* uTagSrc*/); 1436 } 1437 1438 1439 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc) 1427 1440 { 1428 1441 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); … … 1455 1468 if (s->tpr && (uint32_t)intno <= s->tpr) 1456 1469 { 1470 *puTagSrc = 0; 1457 1471 Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff)); 1458 1472 return s->spurious_vec & 0xff; 1459 1473 } 1474 1460 1475 Apic256BitReg_ClearBit(&s->irr, intno); 1461 1476 Apic256BitReg_SetBit(&s->isr, intno); 1477 1478 *puTagSrc = s->auTags[intno]; 1479 s->auTags[intno] = 0; 1480 1462 1481 apic_update_irq(pDev, s); 1463 LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno)); 1482 1483 LogFlow(("CPU%d: apic_get_interrupt: returns %d / %#x\n", s->phys_id, intno, *puTagSrc)); 1464 1484 return intno; 1465 1485 } … … 1679 1699 if (!(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { 1680 1700 LogFlow(("apic_timer: trigger irq\n")); 1681 apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE );1701 apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE, 0 /*uTagSrc*/); 1682 1702 1683 1703 if ( (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) -
trunk/src/VBox/Devices/PC/DevIoApic.cpp
r40280 r40907 87 87 uint32_t irr; 88 88 uint64_t ioredtbl[IOAPIC_NUM_PINS]; 89 /** The IRQ tags and source IDs for each pin (tracing purposes). */ 90 uint32_t auTagSrc[IOAPIC_NUM_PINS]; 89 91 90 92 /** The device instance - R3 Ptr. */ … … 157 159 else 158 160 vector = entry & 0xff; 161 uint32_t uTagSrc = pThis->auTagSrc[vector]; 162 pThis->auTagSrc[vector] = 0; 159 163 160 164 int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns), … … 164 168 vector, 165 169 polarity, 166 trig_mode); 170 trig_mode, 171 uTagSrc); 167 172 /* We must be sure that attempts to reschedule in R3 168 173 never get here */ … … 174 179 175 180 176 static void ioapic_set_irq(void *opaque, int vector, int level )181 static void ioapic_set_irq(void *opaque, int vector, int level, uint32_t uTagSrc) 177 182 { 178 183 IOAPICState *pThis = (IOAPICState*)opaque; … … 189 194 { 190 195 pThis->irr |= mask; 196 if (!pThis->auTagSrc[vector]) 197 pThis->auTagSrc[vector] = uTagSrc; 198 else 199 pThis->auTagSrc[vector] = RT_BIT_32(31); 200 191 201 ioapic_service(pThis); 202 192 203 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) 193 204 pThis->irr &= ~mask; … … 202 213 { 203 214 pThis->irr |= mask; 215 if (!pThis->auTagSrc[vector]) 216 pThis->auTagSrc[vector] = uTagSrc; 217 else 218 pThis->auTagSrc[vector] = RT_BIT_32(31); 219 204 220 ioapic_service(pThis); 205 221 } … … 372 388 } 373 389 374 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel )390 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc) 375 391 { 376 392 /* PDM lock is taken here; */ /** @todo add assertion */ 377 393 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *); 378 394 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq)); 379 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d \n", iIrq, iLevel));380 ioapic_set_irq(pThis, iIrq, iLevel );381 } 382 383 PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue )395 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc)); 396 ioapic_set_irq(pThis, iIrq, iLevel, uTagSrc); 397 } 398 399 PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc) 384 400 { 385 401 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *); … … 406 422 vector_num, 407 423 0 /* polarity, n/a */, 408 trigger_mode); 424 trigger_mode, 425 uTagSrc); 409 426 /* We must be sure that attempts to reschedule in R3 410 427 never get here */ -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r40280 r40907 51 51 RT_C_DECLS_BEGIN 52 52 53 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel );54 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns );53 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc); 54 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc); 55 55 PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb); 56 56 PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb); … … 109 109 uint8_t elcr_mask; 110 110 /** Pointer to the device instance, R3 Ptr. */ 111 PPDMDEVINSR3 pDevInsR3;111 PPDMDEVINSR3 pDevInsR3; 112 112 /** Pointer to the device instance, R0 Ptr. */ 113 PPDMDEVINSR0 pDevInsR0;113 PPDMDEVINSR0 pDevInsR0; 114 114 /** Pointer to the device instance, RC Ptr. */ 115 PPDMDEVINSRC pDevInsRC; 116 RTRCPTR Alignment0; /**< Structure size alignment. */ 115 PPDMDEVINSRC pDevInsRC; 116 RTRCPTR Alignment0; /**< Structure size alignment. */ 117 /** The IRQ tags and source IDs for each (tracing purposes). */ 118 uint32_t auTags[8]; 119 117 120 } PicState; 118 121 … … 164 167 165 168 /* set irq level. If an edge is detected, then the IRR is set to 1 */ 166 static inline void pic_set_irq1(PicState *s, int irq, int level )169 static inline void pic_set_irq1(PicState *s, int irq, int level, uint32_t uTagSrc) 167 170 { 168 171 int mask; … … 194 197 } 195 198 } 199 200 /* Save the tag. */ 201 if (level) 202 { 203 if (!s->auTags[irq]) 204 s->auTags[irq] = uTagSrc; 205 else 206 s->auTags[irq] |= RT_BIT_32(31); 207 } 208 196 209 DumpPICState(s, "pic_set_irq1"); 197 210 } … … 251 264 if (irq2 >= 0) { 252 265 /* if irq request by slave pic, signal master PIC */ 253 pic_set_irq1(&pics[0], 2, 1 );266 pic_set_irq1(&pics[0], 2, 1, pics[1].auTags[irq2]); 254 267 } else { 255 268 /* If not, clear the IR on the master PIC. */ 256 pic_set_irq1(&pics[0], 2, 0 );269 pic_set_irq1(&pics[0], 2, 0, 0 /*uTagSrc*/); 257 270 } 258 271 /* look at requested irq */ … … 352 365 * @param iIrq IRQ number to set. 353 366 * @param iLevel IRQ level. 354 */ 355 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 367 * @param uTagSrc The IRQ tag and source ID (for tracing). 368 */ 369 PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc) 356 370 { 357 371 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC); … … 371 385 * line must be held high for a while to avoid spurious interrupts. 372 386 */ 373 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0 );387 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0, uTagSrc); 374 388 pic_update_irq(pThis); 375 389 } 376 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH );390 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc); 377 391 pic_update_irq(pThis); 378 392 } … … 402 416 * @returns Pending interrupt number. 403 417 * @param pDevIns Device instance of the PICs. 404 */ 405 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns) 418 * @param puTagSrc Where to return the IRQ tag and source ID. 419 */ 420 PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc) 406 421 { 407 422 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC); … … 431 446 } 432 447 intno = pThis->aPics[1].irq_base + irq2; 433 Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pThis->aPics[1].irq_base, irq2)); 448 *puTagSrc = pThis->aPics[0].auTags[irq2]; 449 pThis->aPics[0].auTags[irq2] = 0; 450 Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc)); 434 451 irq = irq2 + 8; 435 452 } 436 else { 453 else 454 { 437 455 intno = pThis->aPics[0].irq_base + irq; 438 Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pThis->aPics[0].irq_base, irq)); 456 *puTagSrc = pThis->aPics[0].auTags[irq]; 457 pThis->aPics[0].auTags[irq] = 0; 458 Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc)); 439 459 } 440 460 } … … 445 465 irq = 7; 446 466 intno = pThis->aPics[0].irq_base + irq; 467 *puTagSrc = 0; 447 468 } 448 469 pic_update_irq(pThis);
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