Changeset 41173 in vbox for trunk/include

Timestamp:

May 4, 2012 3:45:28 PM (13 years ago)

Author:

vboxsync

Message:

VMM: Fixed reading the wrong (reserved) bit in EPT capabilities, renamed capability defines to better suit the Intel Spec.

File:

• trunk/include/VBox/vmm/hwacc_vmx.h (modified) (1 diff)

trunk/include/VBox/vmm/hwacc_vmx.h

@@ -636 +636 @@
  * @{
  */
-#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY                     RT_BIT_64(0)
-#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY                     RT_BIT_64(1)
-#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY                    RT_BIT_64(2)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS                    RT_BIT_64(3)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS                    RT_BIT_64(4)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS                    RT_BIT_64(5)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS                    RT_BIT_64(6)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS                    RT_BIT_64(7)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_UC                         RT_BIT_64(8)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WC                         RT_BIT_64(9)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WT                         RT_BIT_64(12)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WP                         RT_BIT_64(13)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WB                         RT_BIT_64(14)
-#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS                     RT_BIT_64(16)
-#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS                     RT_BIT_64(17)
-#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS                     RT_BIT_64(18)
-#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS                     RT_BIT_64(19)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT                         RT_BIT_64(20)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV              RT_BIT_64(24)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT            RT_BIT_64(25)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL                RT_BIT_64(26)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID                        RT_BIT_64(32)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV             RT_BIT_64(40)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT           RT_BIT_64(41)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL               RT_BIT_64(42)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL    RT_BIT_64(43)
+#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY                                    RT_BIT_64(0)
+#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY                                    RT_BIT_64(1)
+#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY                                   RT_BIT_64(2)
+#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS                                   RT_BIT_64(3)
+#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS                                   RT_BIT_64(4)
+#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS                                   RT_BIT_64(5)
+#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS                                   RT_BIT_64(6)
+#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS                                   RT_BIT_64(7)
+#define MSR_IA32_VMX_EPT_CAPS_EMT_UC                                        RT_BIT_64(8)
+#define MSR_IA32_VMX_EPT_CAPS_EMT_WC                                        RT_BIT_64(9)
+#define MSR_IA32_VMX_EPT_CAPS_EMT_WT                                        RT_BIT_64(12)
+#define MSR_IA32_VMX_EPT_CAPS_EMT_WP                                        RT_BIT_64(13)
+#define MSR_IA32_VMX_EPT_CAPS_EMT_WB                                        RT_BIT_64(14)
+#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS                                    RT_BIT_64(16)
+#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS                                    RT_BIT_64(17)
+#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS                                    RT_BIT_64(18)
+#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS                                    RT_BIT_64(19)
+#define MSR_IA32_VMX_EPT_CAPS_INVEPT                                        RT_BIT_64(20)
+#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT                    RT_BIT_64(25)
+#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS                      RT_BIT_64(26)
+#define MSR_IA32_VMX_EPT_CAPS_INVVPID                                       RT_BIT_64(32)
+#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR                       RT_BIT_64(40)
+#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT                   RT_BIT_64(41)
+#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS                     RT_BIT_64(42)
+#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS    RT_BIT_64(43)
 
 /** @} */