Changeset 41328 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

May 16, 2012 10:57:35 AM (13 years ago)

Author:

vboxsync

Message:

VMM/VMMR0/HWVMXR0: Code cleanup, style fixes, wrap to 130 columns.

File:

• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (196 diffs)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -61 +61 @@
 #endif
 
+
 /*******************************************************************************
 *   Global Variables                                                           *
@@ -73 +74 @@
 #endif
 
+
 /*******************************************************************************
 *   Local Functions                                                            *
 *******************************************************************************/
-static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx);
 static DECLCALLBACK(void) hmR0VmxSetupTLBEPT(PVM pVM, PVMCPU pVCpu);
 static DECLCALLBACK(void) hmR0VmxSetupTLBVPID(PVM pVM, PVMCPU pVCpu);
@@ -85 +86 @@
 static void hmR0VmxUpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
 static void hmR0VmxSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
-
-
+static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx);
+
+
+/**
+ * Updates error from VMCS to HWACCMCPU's lasterror record.
+ *
+ * @param    pVM            Pointer to the VM.
+ * @param    pVCpu          Pointer to the VMCPU.
+ * @param    rc             The error code.
+ */
 static void hmR0VmxCheckError(PVM pVM, PVMCPU pVCpu, int rc)
 {
@@ -99 +108 @@
 }
 
+
 /**
- * Sets up and activates VT-x on the current CPU
+ * Sets up and activates VT-x on the current CPU.
  *
  * @returns VBox status code.
- * @param   pCpu            CPU info struct
- * @param   pVM             The VM to operate on. (can be NULL after a resume!!)
- * @param   pvCpuPage       Pointer to the global cpu page.
- * @param   HCPhysCpuPage   Physical address of the global cpu page.
+ * @param   pCpu            Pointer to the CPU info struct.
+ * @param   pVM             Pointer to the VM. (can be NULL after a resume!!)
+ * @param   pvCpuPage       Pointer to the global CPU page.
+ * @param   HCPhysCpuPage   Physical address of the global CPU page.
  */
 VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
@@ -112 +122 @@
     AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
     AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
-    NOREF(pCpu);
 
     if (pVM)
@@ -127 +136 @@
         return VERR_VMX_IN_VMX_ROOT_MODE;
 
-    /* Make sure the VMX instructions don't cause #UD faults. */
-    ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
-
-    /* Enter VMX Root Mode. */
+    ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);    /* Make sure the VMX instructions don't cause #UD faults. */
+
+    /*
+     * Enter VM root mode.
+     */
     int rc = VMXEnable(HCPhysCpuPage);
     if (RT_FAILURE(rc))
@@ -156 +166 @@
 }
 
+
 /**
- * Deactivates VT-x on the current CPU
+ * Deactivates VT-x on the current CPU.
  *
  * @returns VBox status code.
- * @param   pCpu            CPU info struct
- * @param   pvCpuPage       Pointer to the global cpu page.
- * @param   HCPhysCpuPage   Physical address of the global cpu page.
+ * @param   pCpu            Pointer to the CPU info struct.
+ * @param   pvCpuPage       Pointer to the global CPU page.
+ * @param   HCPhysCpuPage   Physical address of the global CPU page.
  */
 VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
@@ -182 +193 @@
 }
 
+
 /**
- * Does Ring-0 per VM VT-x init.
+ * Does Ring-0 per VM VT-x initialization.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
+ * @param   pVM         Pointer to the VM.
  */
 VMMR0DECL(int) VMXR0InitVM(PVM pVM)
@@ -309 +321 @@
 }
 
+
 /**
  * Does Ring-0 per VM VT-x termination.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
+ * @param   pVM         Pointer to the VM.
  */
 VMMR0DECL(int) VMXR0TermVM(PVM pVM)
@@ -379 +392 @@
 }
 
+
 /**
- * Sets up VT-x for the specified VM
+ * Sets up VT-x for the specified VM.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
+ * @param   pVM         Pointer to the VM.
  */
 VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
@@ -445 +459 @@
         *(uint32_t *)pVCpu->hwaccm.s.vmx.pvVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
 
-        /* Clear VM Control Structure. */
+        /*
+         * Clear and activate the VMCS.
+         */
         Log(("HCPhysVMCS  = %RHp\n", pVCpu->hwaccm.s.vmx.HCPhysVMCS));
         rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
@@ -451 +467 @@
             goto vmx_end;
 
-        /* Activate the VM Control Structure. */
         rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
         if (RT_FAILURE(rc))
             goto vmx_end;
 
-        /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
+        /*
+         * VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
          * Set required bits to one and zero according to the MSR capabilities.
          */
-        val  = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
-        /* External and non-maskable interrupts cause VM-exits. */
-        val |= VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
-        /* enable the preemption timer. */
+        val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
+        val |=    VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT      /* External interrupts */
+                | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;         /* Non-maskable interrupts */
+
+        /*
+         * Enable the VMX preemption timer.
+         */
         if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
             val |= VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER;
@@ -470 +489 @@
         AssertRC(rc);
 
-        /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
+        /*
+         * VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
          * Set required bits to one and zero according to the MSR capabilities.
          */
         val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
         /* Program which event cause VM-exits and which features we want to use. */
-        val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT;    /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
+        val |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
+               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
+               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
+               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
+               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
+               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT
+               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT;     /* don't execute mwait or else we'll idle inside
+                                                                      the guest (host thinks the cpu load is high) */
 
         /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
         if (!pVM->hwaccm.s.fNestedPaging)
-            val |=  VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
-                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
-
-        /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
+        {
+            val |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
+                   | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
+                   | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
+        }
+
+        /*
+         * VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch
+         * failure with an invalid control fields error. (combined with some other exit reasons)
+         */
         if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
         {
@@ -519 +545 @@
         if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
         {
-            /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
+            /*
+             * VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
              * Set required bits to one and zero according to the MSR capabilities.
              */
@@ -545 +572 @@
         }
 
-        /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
+        /*
+         * VMX_VMCS_CTRL_CR3_TARGET_COUNT
          * Set required bits to one and zero according to the MSR capabilities.
          */
@@ -551 +579 @@
         AssertRC(rc);
 
-        /* Forward all exception except #NM & #PF to the guest.
+        /*
+         * Forward all exception except #NM & #PF to the guest.
          * We always need to check pagefaults since our shadow page table can be out of sync.
-         * And we always lazily sync the FPU & XMM state.
+         * And we always lazily sync the FPU & XMM state.                                                           .
          */
 
@@ -564 +593 @@
          */
 
-        /* Don't filter page faults; all of them should cause a switch. */
+        /*
+         * Don't filter page faults, all of them should cause a world switch.
+         */
         rc  = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
-        rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
         AssertRC(rc);
-
-        /* Init TSC offset to zero. */
+        rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
+        AssertRC(rc);
+
         rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
         AssertRC(rc);
-
         rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
         AssertRC(rc);
-
         rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
         AssertRC(rc);
 
-        /* Set the MSR bitmap address. */
+        /*
+         * Set the MSR bitmap address.
+         */
         if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
         {
@@ -600 +631 @@
 
 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-        /* Set the guest & host MSR load/store physical addresses. */
+        /*
+         * Set the guest & host MSR load/store physical addresses.
+         */
         Assert(pVCpu->hwaccm.s.vmx.pGuestMSRPhys);
         rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, pVCpu->hwaccm.s.vmx.pGuestMSRPhys);
@@ -614 +647 @@
         rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
         AssertRC(rc);
-
         rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
         AssertRC(rc);
@@ -635 +667 @@
         AssertRC(rc);
 
-        /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
+        /*
+         * Clear VMCS, marking it inactive. Clear implementation specific data and writing back
+         * VMCS data back to memory.
+         */
         rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
         AssertRC(rc);
 
-        /* Configure the VMCS read cache. */
+        /*
+         * Configure the VMCS read cache.
+         */
         PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
 
@@ -659 +696 @@
         VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
 
-        VMX_SETUP_SELREG(ES, pCache);
-        VMX_SETUP_SELREG(SS, pCache);
-        VMX_SETUP_SELREG(CS, pCache);
-        VMX_SETUP_SELREG(DS, pCache);
-        VMX_SETUP_SELREG(FS, pCache);
-        VMX_SETUP_SELREG(GS, pCache);
+        VMX_SETUP_SELREG(ES,   pCache);
+        VMX_SETUP_SELREG(SS,   pCache);
+        VMX_SETUP_SELREG(CS,   pCache);
+        VMX_SETUP_SELREG(DS,   pCache);
+        VMX_SETUP_SELREG(FS,   pCache);
+        VMX_SETUP_SELREG(GS,   pCache);
         VMX_SETUP_SELREG(LDTR, pCache);
-        VMX_SETUP_SELREG(TR, pCache);
-
-        /* Status code VMCS reads. */
+        VMX_SETUP_SELREG(TR,   pCache);
+
+        /*
+         * Status code VMCS reads.
+         */
         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
@@ -689 +728 @@
     } /* for each VMCPU */
 
-    /* Choose the right TLB setup function. */
+    /*
+     * Setup the right TLB function based on CPU capabilities.
+     */
     if (pVM->hwaccm.s.fNestedPaging && pVM->hwaccm.s.vmx.fVPID)
         pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = hmR0VmxSetupTLBBoth;
@@ -704 +745 @@
 }
 
+
 /**
- * Sets the permission bits for the specified MSR
+ * Sets the permission bits for the specified MSR.
  *
- * @param   pVCpu       The VMCPU to operate on.
- * @param   ulMSR       MSR value
- * @param   fRead       Reading allowed/disallowed
- * @param   fWrite      Writing allowed/disallowed
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   ulMSR       The MSR value.
+ * @param   fRead       Whether reading is allowed.
+ * @param   fWrite      Whether writing is allowed.
  */
 static void hmR0VmxSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
@@ -717 +759 @@
     uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.vmx.pMSRBitmap;
 
-    /* Layout:
+    /*
+     * Layout:
      * 0x000 - 0x3ff - Low MSR read bits
      * 0x400 - 0x7ff - High MSR read bits
@@ -729 +772 @@
     }
     else
-    if (    ulMSR >= 0xC0000000
-        &&  ulMSR <= 0xC0001FFF)
+    if (   ulMSR >= 0xC0000000
+        && ulMSR <= 0xC0001FFF)
     {
         /* AMD Sixth Generation x86 Processor MSRs */
@@ -756 +799 @@
 
 /**
- * Injects an event (trap or external interrupt)
+ * Injects an event (trap or external interrupt).
  *
  * @returns VBox status code.  Note that it may return VINF_EM_RESET to
  *          indicate a triple fault when injecting X86_XCPT_DF.
  *
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        CPU Context
- * @param   intInfo     VMX interrupt info
- * @param   cbInstr     Opcode length of faulting instruction
- * @param   errCode     Error code (optional)
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU Context.
+ * @param   intInfo     VMX interrupt info.
+ * @param   cbInstr     Opcode length of faulting instruction.
+ * @param   errCode     Error code (optional).
  */
 static int hmR0VmxInjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
@@ -779 +822 @@
 #ifdef VBOX_STRICT
     if (iGate == 0xE)
-        LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
-    else
-    if (iGate < 0x20)
-        LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
+    {
+        LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate,
+                 (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
+    }
+    else if (iGate < 0x20)
+    {
+        LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip,
+                 errCode));
+    }
     else
     {
@@ -800 +848 @@
         RTSEL    sel;
 
-        /* Injecting events doesn't work right with real mode emulation.
+        /*
+         * Injecting events doesn't work right with real mode emulation.
          * (#GP if we try to inject external hardware interrupts)
          * Inject the interrupt or trap directly instead.
@@ -808 +857 @@
         Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
 
-        /* Check if the interrupt handler is present. */
+        /*
+         * Check if the interrupt handler is present.
+         */
         if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
         {
@@ -835 +886 @@
             ip = pCtx->ip;
 
-        /* Read the selector:offset pair of the interrupt handler. */
+        /*
+         * Read the selector:offset pair of the interrupt handler.
+         */
         GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
         rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler,     sizeof(offset)); AssertRC(rc);
@@ -842 +895 @@
         LogFlow(("IDT handler %04X:%04X\n", sel, offset));
 
-        /* Construct the stack frame. */
-        /** @todo should check stack limit. */
+        /*
+         * Construct the stack frame.
+         */
+        /** @todo Check stack limit. */
         pCtx->sp -= 2;
         LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
@@ -854 +909 @@
         rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
 
-        /* Update the CPU state for executing the handler. */
+        /*
+         * Update the CPU state for executing the handler.
+         */
         pCtx->rip           = offset;
         pCtx->cs            = sel;
         pCtx->csHid.u64Base = sel << 4;
-        pCtx->eflags.u     &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
+        pCtx->eflags.u     &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
 
         pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
@@ -864 +921 @@
     }
 
-    /* Set event injection state. */
+    /*
+     * Set event injection state.
+     */
     rc  = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
-
     rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
     rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
@@ -876 +934 @@
 
 /**
- * Checks for pending guest interrupts and injects them
+ * Checks for pending guest interrupts and injects them into the guest.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        CPU Context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 static int hmR0VmxCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
@@ -887 +945 @@
     int rc;
 
-    /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
+    /*
+     * Dispatch any pending interrupts (injected before, but a VM exit occurred prematurely).
+     */
     if (pVCpu->hwaccm.s.Event.fPending)
     {
-        Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
+        Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo,
+             pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
         rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
@@ -899 +960 @@
     }
 
-    /* If an active trap is already pending, then we must forward it first! */
+    /*
+     * If an active trap is already pending, we must forward it first!
+     */
     if (!TRPMHasTrap(pVCpu))
     {
@@ -918 +981 @@
         }
 
-        /* @todo SMI interrupts. */
-
-        /* When external interrupts are pending, we should exit the VM when IF is set. */
+        /** @todo SMI interrupts. */
+
+        /*
+         * When external interrupts are pending, we should exit the VM when IF is set.
+         */
         if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
         {
@@ -934 +999 @@
                 /* else nothing to do but wait */
             }
-            else
-            if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
+            else if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
             {
                 uint8_t u8Interrupt;
 
                 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
-                Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
+                Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu,
+                     u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
                 if (RT_SUCCESS(rc))
                 {
@@ -962 +1027 @@
     if (TRPMHasTrap(pVCpu))
     {
-        uint8_t     u8Vector;
+        uint8_t u8Vector;
         rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
         AssertRC(rc);
@@ -968 +1033 @@
 #endif
 
-    if (    (pCtx->eflags.u32 & X86_EFL_IF)
+    if (   (pCtx->eflags.u32 & X86_EFL_IF)
         && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
         && TRPMHasTrap(pVCpu)
@@ -978 +1043 @@
         RTGCUINT    errCode;
 
-        /* If a new event is pending, then dispatch it now. */
+        /*
+         * If a new event is pending, dispatch it now.
+         */
         rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
         AssertRC(rc);
@@ -984 +1051 @@
         Assert(enmType != TRPM_SOFTWARE_INT);
 
-        /* Clear the pending trap. */
+        /*
+         * Clear the pending trap.
+         */
         rc = TRPMResetTrap(pVCpu);
         AssertRC(rc);
@@ -993 +1062 @@
         if (enmType == TRPM_TRAP)
         {
-            switch (u8Vector) {
-            case X86_XCPT_DF:
-            case X86_XCPT_TS:
-            case X86_XCPT_NP:
-            case X86_XCPT_SS:
-            case X86_XCPT_GP:
-            case X86_XCPT_PF:
-            case X86_XCPT_AC:
-                /* Valid error codes. */
-                intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
-                break;
-            default:
-                break;
+            switch (u8Vector)
+            {
+                case X86_XCPT_DF:
+                case X86_XCPT_TS:
+                case X86_XCPT_NP:
+                case X86_XCPT_SS:
+                case X86_XCPT_GP:
+                case X86_XCPT_PF:
+                case X86_XCPT_AC:
+                {
+                    /* Valid error codes. */
+                    intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
+                    break;
+                }
+
+                default:
+                    break;
             }
-            if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
+
+            if (   u8Vector == X86_XCPT_BP
+                || u8Vector == X86_XCPT_OF)
+            {
                 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
+            }
             else
                 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
@@ -1023 +1100 @@
 }
 
+
 /**
- * Save the host state
+ * Save the host state into the VMCS.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
  */
 VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
@@ -1036 +1114 @@
 
     /*
-     * Host CPU Context
+     * Host CPU Context.
      */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
@@ -1049 +1127 @@
         uint64_t    cr3;
 
-        /* Control registers */
-        rc  = VMXWriteVMCS(VMX_VMCS_HOST_CR0,               ASMGetCR0());
+        /*
+         * Control registers.
+         */
+        rc  = VMXWriteVMCS(VMX_VMCS_HOST_CR0,           ASMGetCR0());
+        Log2(("VMX_VMCS_HOST_CR0 %08x\n",               ASMGetCR0()));
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
         if (VMX_IS_64BIT_HOST_MODE())
         {
             cr3 = hwaccmR0Get64bitCR3();
-            rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3,         cr3);
+            rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3,     cr3);
         }
         else
@@ -1061 +1142 @@
         {
             cr3 = ASMGetCR3();
-            rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3,           cr3);
-        }
-        rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4,               ASMGetCR4());
+            rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3,       cr3);
+        }
+        Log2(("VMX_VMCS_HOST_CR3 %08RX64\n",            cr3));
+        rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4,           ASMGetCR4());
+        Log2(("VMX_VMCS_HOST_CR4 %08x\n",               ASMGetCR4()));
         AssertRC(rc);
-        Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
-        Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
-        Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
-
-        /* Selector registers. */
+
+        /*
+         * Selector registers.
+         */
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
         if (VMX_IS_64BIT_HOST_MODE())
@@ -1111 +1193 @@
         Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
 
-        /* GDTR & IDTR */
+        /*
+         * GDTR & IDTR.
+         */
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
         if (VMX_IS_64BIT_HOST_MODE())
@@ -1137 +1221 @@
         }
 
-        /* Save the base address of the TR selector. */
+        /*
+         * Save the base address of the TR selector.
+         */
         if (SelTR > gdtr.cbGdt)
         {
@@ -1166 +1252 @@
         }
 
-        /* FS and GS base. */
+        /*
+         * FS base and GS base.
+         */
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
         if (VMX_IS_64BIT_HOST_MODE())
@@ -1172 +1260 @@
             Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
             Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
-            rc  = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE,     ASMRdMsr(MSR_K8_FS_BASE));
-            rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE,     ASMRdMsr(MSR_K8_GS_BASE));
+            rc  = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE,         ASMRdMsr(MSR_K8_FS_BASE));
+            rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE,         ASMRdMsr(MSR_K8_GS_BASE));
         }
 #endif
         AssertRC(rc);
 
-        /* Sysenter MSRs. */
+        /*
+         * Sysenter MSRs.
+         */
         /** @todo expensive!! */
-        rc  = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS,       ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
-        Log2(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
+        rc  = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS,         ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
+        Log2(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n",              ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
         if (VMX_IS_64BIT_HOST_MODE())
@@ -1192 +1282 @@
         else
         {
-            rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP,  ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
-            rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP,  ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
-            Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n",     ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
-            Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n",     ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
+            rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
+            rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
+            Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n",         ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
+            Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n",         ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
         }
 #elif HC_ARCH_BITS == 32
-        rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
-        rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
-        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
-        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
+        rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP,          ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
+        rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP,          ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
+        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n",             ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
+        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n",             ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
 #else
-        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
-        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
-        rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP,      ASMRdMsr(MSR_IA32_SYSENTER_ESP));
-        rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP,      ASMRdMsr(MSR_IA32_SYSENTER_EIP));
+        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n",             ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
+        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n",             ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
+            rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP,    ASMRdMsr(MSR_IA32_SYSENTER_ESP));
+        rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP,        ASMRdMsr(MSR_IA32_SYSENTER_EIP));
 #endif
         AssertRC(rc);
 
+
 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
-        /* Store all host MSRs in the VM-Exit load area, so they will be reloaded after the world switch back to the host. */
+        /*
+         * Store all host MSRs in the VM-Exit load area, so they will be reloaded after
+         * the world switch back to the host.
+         */
         PVMXMSR pMsr = (PVMXMSR)pVCpu->hwaccm.s.vmx.pHostMSR;
         unsigned idxMsr = 0;
 
-        /* EFER MSR present? */
+        /*
+         * Check if EFER MSR present.
+         */
         if (ASMCpuId_EDX(0x80000001) & (X86_CPUID_AMD_FEATURE_EDX_NX|X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
         {
@@ -1231 +1327 @@
             if (CPUMIsGuestInLongMode(pVCpu))
             {
-                /* Must match the efer value in our 64 bits switcher. */
+                /* Must match the EFER value in our 64 bits switcher. */
                 pMsr->u64Value    = ASMRdMsr(MSR_K6_EFER) | MSR_K6_EFER_LME | MSR_K6_EFER_SCE | MSR_K6_EFER_NXE;
             }
@@ -1266 +1362 @@
 }
 
+
 /**
  * Loads the 4 PDPEs into the guest state when nested paging is used and the
  * guest operates in PAE mode.
  *
- * @returns VINF_SUCCESS or fatal error.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @returns VBox status code.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 static int hmR0VmxLoadPaePdpes(PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -1290 +1387 @@
 }
 
+
 /**
  * Saves the 4 PDPEs into the guest state when nested paging is used and the
  * guest operates in PAE mode.
  *
- * @returns VINF_SUCCESS or fatal error.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @returns VBox status code.
+ * @param   pVCpu       Pointer to the VM CPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  *
  * @remarks Tell PGM about CR3 changes before calling this helper.
@@ -1319 +1417 @@
 
 /**
- * Update the exception bitmap according to the current CPU state
+ * Update the exception bitmap according to the current CPU state.
  *
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 static void hmR0VmxUpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -1330 +1428 @@
     Assert(pCtx);
 
-    /* Set up a mask for intercepting traps. */
+    /*
+     * Set up a mask for intercepting traps.
+     */
     /** @todo Do we really need to always intercept #DB? */
     u32TrapMask  =   RT_BIT(X86_XCPT_DB)
@@ -1350 +1450 @@
                    ;
 
+    /*
+     * Without nested paging, #PF must be intercepted to implement shadow paging.
+     */
     /** @todo NP state won't change so maybe we should build the initial trap mask up front? */
-    /* Without nested paging, #PF must be intercepted to implement shadow paging. */
     if (!pVM->hwaccm.s.fNestedPaging)
         u32TrapMask |= RT_BIT(X86_XCPT_PF);
 
-    /* Also catch floating point exceptions if we need to report them to the guest in a different way. */
+    /* Catch floating point exceptions if we need to report them to the guest in a different way. */
     if (!(pCtx->cr0 & X86_CR0_NE))
-    {
         u32TrapMask |= RT_BIT(X86_XCPT_MF);
-    }
 
 #ifdef VBOX_STRICT
@@ -1365 +1465 @@
 #endif
 
-    /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
+    /*
+     * Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise).
+     */
     /** @todo Despite the claim to intercept everything, with NP we do not intercept #PF. Should we? */
     if (    CPUMIsGuestInRealModeEx(pCtx)
         &&  pVM->hwaccm.s.vmx.pRealModeTSS)
+    {
         u32TrapMask |=   RT_BIT(X86_XCPT_DE)
                        | RT_BIT(X86_XCPT_DB)
@@ -1387 +1490 @@
                        | RT_BIT(X86_XCPT_XF)
                        ;
+    }
 
     int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
@@ -1392 +1496 @@
 }
 
+
 /**
- * Loads a minimal guest state
+ * Loads a minimal guest state.
  *
  * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
  *
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 VMMR0DECL(void) VMXR0LoadMinimalGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -1408 +1513 @@
     Assert(!(pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_ALL_GUEST));
 
-    /* EIP, ESP and EFLAGS */
+    /*
+     * Load EIP, ESP and EFLAGS.
+     */
     rc  = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
     rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
     AssertRC(rc);
 
-    /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
+    /*
+     * Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1.
+     */
     eflags      = pCtx->eflags;
     eflags.u32 &= VMX_EFLAGS_RESERVED_0;
     eflags.u32 |= VMX_EFLAGS_RESERVED_1;
 
-    /* Real mode emulation using v86 mode. */
+    /*
+     * Check if real mode emulation using v86 mode.
+     */
     if (    CPUMIsGuestInRealModeEx(pCtx)
         &&  pVM->hwaccm.s.vmx.pRealModeTSS)
@@ -1431 +1542 @@
 }
 
+
 /**
- * Loads the guest state
+ * Loads the guest state.
  *
  * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -1446 +1558 @@
     RTGCUINTPTR val;
 
-    /* VMX_VMCS_CTRL_ENTRY_CONTROLS
+    /*
+     * VMX_VMCS_CTRL_ENTRY_CONTROLS
      * Set required bits to one and zero according to the MSR capabilities.
      */
     val  = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
-    /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
+
+    /*
+     * Load guest debug controls (DR7 & IA32_DEBUGCTL_MSR).
+     * Forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs
+     */
     val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
-    /* 64 bits guest mode? */
+
     if (CPUMIsGuestInLongModeEx(pCtx))
         val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
     /* else Must be zero when AMD64 is not available. */
 
-    /* Mask away the bits that the CPU doesn't support */
+    /*
+     * Mask away the bits that the CPU doesn't support.
+     */
     val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
     rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
     AssertRC(rc);
 
-    /* VMX_VMCS_CTRL_EXIT_CONTROLS
+    /*
+     * VMX_VMCS_CTRL_EXIT_CONTROLS
      * Set required bits to one and zero according to the MSR capabilities.
      */
     val  = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
 
-    /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
+    /*
+     * Save debug controls (DR7 & IA32_DEBUGCTL_MSR)
+     * Forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs
+     */
     val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
 
@@ -1473 +1596 @@
     if (VMX_IS_64BIT_HOST_MODE())
         val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
-    /* else: Must be zero when AMD64 is not available. */
+    /* else Must be zero when AMD64 is not available. */
 #elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
     if (CPUMIsGuestInLongModeEx(pCtx))
@@ -1481 +1604 @@
 #endif
     val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
-    /* Don't acknowledge external interrupts on VM-exit. */
+
+    /*
+     * Don't acknowledge external interrupts on VM-exit.
+     */
     rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
     AssertRC(rc);
 
-    /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
+    /*
+     * Guest CPU context: ES, CS, SS, DS, FS, GS.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
     {
@@ -1493 +1621 @@
             if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
             {
-                /* Correct weird requirements for switching to protected mode. */
+                /*
+                 * Correct weird requirements for switching to protected mode.
+                 */
                 if (    pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
                     &&  enmGuestMode >= PGMMODE_PROTECTED)
                 {
 #ifdef VBOX_WITH_REM
-                    /* Flush the recompiler code cache as it's not unlikely
-                     * the guest will rewrite code it will later execute in real
-                     * mode (OpenBSD 4.0 is one such example)
+                    /*
+                     * Flush the recompiler code cache as it's not unlikely the guest will rewrite code
+                     * it will later execute in real mode (OpenBSD 4.0 is one such example)
                      */
                     REMFlushTBs(pVM);
 #endif
 
-                    /* DPL of all hidden selector registers must match the current CPL (0). */
+                    /*
+                     * DPL of all hidden selector registers must match the current CPL (0).
+                     */
                     pCtx->csHid.Attr.n.u2Dpl  = 0;
                     pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
@@ -1517 +1649 @@
                 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
             }
-            else
-            /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
-            if (   CPUMIsGuestInRealModeEx(pCtx)
-                && pCtx->csHid.u64Base == 0xffff0000)
+            else if (   CPUMIsGuestInRealModeEx(pCtx)
+                     && pCtx->csHid.u64Base == 0xffff0000)
             {
+                /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
                 pCtx->csHid.u64Base = 0xf0000;
                 pCtx->cs = 0xf000;
@@ -1546 +1677 @@
     }
 
-    /* Guest CPU context: LDTR. */
+    /*
+     * Guest CPU context: LDTR.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
     {
@@ -1566 +1699 @@
         AssertRC(rc);
     }
-    /* Guest CPU context: TR. */
+
+    /*
+     * Guest CPU context: TR.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
     {
-        /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
+        /*
+         * Real mode emulation using v86 mode with CR4.VME (interrupt redirection
+         * using the int bitmap in the TSS).
+         */
         if (    CPUMIsGuestInRealModeEx(pCtx)
             &&  pVM->hwaccm.s.vmx.pRealModeTSS)
@@ -1575 +1714 @@
             RTGCPHYS GCPhys;
 
-            /* We convert it here every time as pci regions could be reconfigured. */
+            /* We convert it here every time as PCI regions could be reconfigured. */
             rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
             AssertRC(rc);
@@ -1612 +1751 @@
         AssertRC(rc);
     }
-    /* Guest CPU context: GDTR. */
+
+    /*
+     * Guest CPU context: GDTR.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
     {
@@ -1619 +1761 @@
         AssertRC(rc);
     }
-    /* Guest CPU context: IDTR. */
+
+    /*
+     * Guest CPU context: IDTR.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
     {
@@ -1628 +1773 @@
 
     /*
-     * Sysenter MSRs
+     * Sysenter MSRs.
      */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_MSR)
@@ -1638 +1783 @@
     }
 
-    /* Control registers */
+    /*
+     * Guest CPU context: Control registers.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
     {
@@ -1665 +1812 @@
             if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
             {
-                /* Disable cr3 read/write monitoring as we don't need it for EPT. */
+                /* Disable CR3 read/write monitoring as we don't need it for EPT. */
                 pVCpu->hwaccm.s.vmx.proc_ctls &=  ~(  VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
                                                     | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
@@ -1671 +1818 @@
             else
             {
-                /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
+                /* Reenable CR3 read/write monitoring as our identity mapped page table is active. */
                 pVCpu->hwaccm.s.vmx.proc_ctls |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
                                                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
@@ -1689 +1836 @@
         rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0,            val);
         Log2(("Guest CR0 %08x\n", val));
-        /* CR0 flags owned by the host; if the guests attempts to change them, then
-         * the VM will exit.
+
+        /*
+         * CR0 flags owned by the host; if the guests attempts to change them, then the VM will exit.
          */
         val =   X86_CR0_PE  /* Must monitor this bit (assumptions are made for real mode emulation) */
@@ -1696 +1844 @@
               | X86_CR0_PG  /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
               | X86_CR0_CD  /* Bit not restored during VM-exit! */
-              | X86_CR0_NW /* Bit not restored during VM-exit! */
+              | X86_CR0_NW  /* Bit not restored during VM-exit! */
               | X86_CR0_NE;
 
-        /* When the guest's FPU state is active, then we no longer care about
-         * the FPU related bits.
+        /*
+         * When the guest's FPU state is active, then we no longer care about the FPU related bits.
          */
         if (CPUMIsGuestFPUStateActive(pVCpu) == false)
@@ -1711 +1859 @@
         AssertRC(rc);
     }
+
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
     {
-        /* CR4 */
         rc  = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW,   pCtx->cr4);
         Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
@@ -1723 +1871 @@
             switch(pVCpu->hwaccm.s.enmShadowMode)
             {
-            case PGMMODE_REAL:          /* Real mode                 -> emulated using v86 mode */
-            case PGMMODE_PROTECTED:     /* Protected mode, no paging -> emulated using identity mapping. */
-            case PGMMODE_32_BIT:        /* 32-bit paging. */
-                val &= ~X86_CR4_PAE;
-                break;
-
-            case PGMMODE_PAE:           /* PAE paging. */
-            case PGMMODE_PAE_NX:        /* PAE paging with NX enabled. */
-                /** Must use PAE paging as we could use physical memory > 4 GB */
-                val |= X86_CR4_PAE;
-                break;
-
-            case PGMMODE_AMD64:         /* 64-bit AMD paging (long mode). */
-            case PGMMODE_AMD64_NX:      /* 64-bit AMD paging (long mode) with NX enabled. */
+                case PGMMODE_REAL:          /* Real mode                 -> emulated using v86 mode */
+                case PGMMODE_PROTECTED:     /* Protected mode, no paging -> emulated using identity mapping. */
+                case PGMMODE_32_BIT:        /* 32-bit paging. */
+                    val &= ~X86_CR4_PAE;
+                    break;
+
+                case PGMMODE_PAE:           /* PAE paging. */
+                case PGMMODE_PAE_NX:        /* PAE paging with NX enabled. */
+                    /** Must use PAE paging as we could use physical memory > 4 GB */
+                    val |= X86_CR4_PAE;
+                    break;
+
+                case PGMMODE_AMD64:         /* 64-bit AMD paging (long mode). */
+                case PGMMODE_AMD64_NX:      /* 64-bit AMD paging (long mode) with NX enabled. */
 #ifdef VBOX_ENABLE_64_BITS_GUESTS
-                break;
+                    break;
 #else
-                AssertFailed();
-                return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
-#endif
-            default:                   /* shut up gcc */
-                AssertFailed();
-                return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
+                    AssertFailed();
+                    return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
+#endif
+                default:                   /* shut up gcc */
+                    AssertFailed();
+                    return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
             }
         }
-        else
-        if (    !CPUMIsGuestInPagedProtectedModeEx(pCtx)
-            &&  !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
+        else if (   !CPUMIsGuestInPagedProtectedModeEx(pCtx)
+                 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
         {
             /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
@@ -1758 +1905 @@
         }
 
-        /* Turn off VME if we're in emulated real mode. */
+        /*
+         * Turn off VME if we're in emulated real mode.
+         */
         if (    CPUMIsGuestInRealModeEx(pCtx)
             &&  pVM->hwaccm.s.vmx.pRealModeTSS)
+        {
             val &= ~X86_CR4_VME;
+        }
 
         rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4,            val);
         Log2(("Guest CR4 %08x\n", val));
-        /* CR4 flags owned by the host; if the guests attempts to change them, then
-         * the VM will exit.
+
+        /*
+         * CR4 flags owned by the host; if the guests attempts to change them, then the VM will exit.
          */
         val =   0
@@ -1812 +1964 @@
                 RTGCPHYS GCPhys;
 
-                /* We convert it here every time as pci regions could be reconfigured. */
+                /* We convert it here every time as PCI regions could be reconfigured. */
                 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
                 AssertMsgRC(rc, ("pNonPagingModeEPTPageTable = %RGv\n", pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable));
 
-                /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
-                 * take care of the translation to host physical addresses.
+                /*
+                 * We use our identity mapping page table here as we need to map guest virtual to
+                 * guest physical addresses; EPT will take care of the translation to host physical addresses.
                  */
                 val = GCPhys;
@@ -1840 +1993 @@
     }
 
-    /* Debug registers. */
+    /*
+     * Guest CPU context: Debug registers.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
     {
@@ -1879 +2034 @@
             STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
 
-            /* Disable drx move intercepts. */
+            /* Disable DRx move intercepts. */
             pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
             rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
@@ -1894 +2049 @@
 
         /** @todo do we really ever need this? */
-        rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS,         0);
+        rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS,  0);
         AssertRC(rc);
     }
 
-    /* 64 bits guest mode? */
+    /*
+     * 64-bit guest mode.
+     */
     if (CPUMIsGuestInLongModeEx(pCtx))
     {
@@ -1994 +2151 @@
     else
         fOffsettedTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVCpu->hwaccm.s.vmx.u64TSCOffset);
+
     if (fOffsettedTsc)
     {
@@ -2011 +2169 @@
         {
             /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
-            LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVCpu->hwaccm.s.vmx.u64TSCOffset, u64CurTSC + pVCpu->hwaccm.s.vmx.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVCpu->hwaccm.s.vmx.u64TSCOffset, TMCpuTickGet(pVCpu)));
+            LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC,
+                     pVCpu->hwaccm.s.vmx.u64TSCOffset, u64CurTSC + pVCpu->hwaccm.s.vmx.u64TSCOffset,
+                     TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVCpu->hwaccm.s.vmx.u64TSCOffset,
+                     TMCpuTickGet(pVCpu)));
             pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
             rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
@@ -2029 +2190 @@
     pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
 
-    /* Minimal guest state update (esp, eip, eflags mostly) */
+    /* Minimal guest state update (ESP, EIP, EFLAGS mostly) */
     VMXR0LoadMinimalGuestState(pVM, pVCpu, pCtx);
     return rc;
 }
 
+
 /**
- * Syncs back the guest state
+ * Syncs back the guest state from VMCS.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer the guest CPU context.
  */
 DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -2048 +2210 @@
     int         rc;
 
-    /* Let's first sync back eip, esp, and eflags. */
+    /* First sync back EIP, ESP, and EFLAGS. */
     rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP,              &val);
     AssertRC(rc);
@@ -2082 +2244 @@
     CPUMSetGuestCR4(pVCpu, val);
 
-    /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
-    /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
-    if (    pVM->hwaccm.s.fNestedPaging
-        &&  CPUMIsGuestInPagedProtectedModeEx(pCtx)) /** @todo check if we will always catch mode switches and such... */
+    /*
+     * No reason to sync back the CRx registers. They can't be changed by the guest unless in
+     * the nested paging case where CR3 & CR4 can be changed by the guest.
+     */
+    if (   pVM->hwaccm.s.fNestedPaging
+        && CPUMIsGuestInPagedProtectedModeEx(pCtx)) /** @todo check if we will always catch mode switches and such... */
     {
         PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
@@ -2103 +2267 @@
     }
 
-    /* Sync back DR7 here. */
+    /* Sync back DR7. */
     VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
     pCtx->dr[7] = val;
@@ -2115 +2279 @@
     VMX_READ_SELREG(GS, gs);
 
-    /*
-     * System MSRs
-     */
+    /* System MSRs */
     VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS,    &val);
     pCtx->SysEnter.cs       = val;
@@ -2180 +2342 @@
         case MSR_K6_EFER:
             /* EFER can't be changed without causing a VM-exit. */
-//            Assert(pCtx->msrEFER == pMsr->u64Value);
+            /* Assert(pCtx->msrEFER == pMsr->u64Value); */
             break;
         default:
@@ -2191 +2353 @@
 }
 
+
 /**
- * Dummy placeholder
+ * Dummy placeholder for TLB flush handling before VM-entry. Used in the case
+ * where neither EPT nor VPID is supported by the CPU.
  *
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
  */
 static DECLCALLBACK(void) hmR0VmxSetupTLBDummy(PVM pVM, PVMCPU pVCpu)
@@ -2210 +2374 @@
  * Setup the tagged TLB for EPT+VPID.
  *
- * @param    pVM        The VM to operate on.
- * @param    pVCpu      The VMCPU to operate on.
+ * @param    pVM        Pointer to the VM.
+ * @param    pVCpu      Pointer to the VMCPU.
  */
 static DECLCALLBACK(void) hmR0VmxSetupTLBBoth(PVM pVM, PVMCPU pVCpu)
@@ -2333 +2497 @@
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
  */
 static DECLCALLBACK(void) hmR0VmxSetupTLBEPT(PVM pVM, PVMCPU pVCpu)
@@ -2343 +2507 @@
     Assert(!pVM->hwaccm.s.vmx.fVPID);
 
-    /* Deal with tagged TLBs if VPID or EPT is supported. */
     pCpu = HWACCMR0GetCurrentCpu();
-    /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
-    /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
+
+    /*
+     * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last
+     * This can happen both for start & resume due to long jumps back to ring-3.
+     * If the TLB flush count shouldn't really change in this EPT-only case.
+     */
     if (    pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
-            /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
         ||  pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
     {
-        /* Force a TLB flush on VM entry. */
         pVCpu->hwaccm.s.fForceTLBFlush = true;
     }
 
-    /* Check for tlb shootdown flushes. */
+    /*
+     * Check for explicit TLB shootdown flushes.
+     */
     if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
         pVCpu->hwaccm.s.fForceTLBFlush = true;
@@ -2390 +2557 @@
 
 /**
- * Setup the tagged TLB for VPID
+ * Setup the tagged TLB for VPID.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
  */
 static DECLCALLBACK(void) hmR0VmxSetupTLBVPID(PVM pVM, PVMCPU pVCpu)
@@ -2403 +2570 @@
     Assert(!pVM->hwaccm.s.fNestedPaging);
 
-    /* Deal with tagged TLBs if VPID or EPT is supported. */
     pCpu = HWACCMR0GetCurrentCpu();
-    /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
-    /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
+
+    /*
+     * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last
+     * This can happen both for start & resume due to long jumps back to ring-3.
+     * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
+     * so we cannot reuse the current ASID anymore.
+     */
     if (    pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
-            /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
         ||  pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
     {
@@ -2415 +2585 @@
     }
 
-    pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
-
-    /* Check for tlb shootdown flushes. */
+    /*
+     * Check for explicit TLB shootdown flushes.
+     */
     if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
         pVCpu->hwaccm.s.fForceTLBFlush = true;
 
-    /* Make sure we flush the TLB when required. */
+    pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
+
     if (pVCpu->hwaccm.s.fForceTLBFlush)
     {
@@ -2485 +2656 @@
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
  */
 VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -2518 +2689 @@
     Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pbVAPIC && pVM->hwaccm.s.vmx.pAPIC));
 
-    /* Check if we need to use TPR shadowing. */
+    /*
+     * Check if we need to use TPR shadowing.
+     */
     if (    CPUMIsGuestInLongModeEx(pCtx)
         || (   ((pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || pVM->hwaccm.s.fTRPPatchingAllowed)
@@ -2535 +2708 @@
         rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val2);
         AssertRC(rc2);
-        Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val2));
+        Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n",  val2));
 
         /* allowed zero */
@@ -2547 +2720 @@
         rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val2);
         AssertRC(rc2);
-        Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val2));
-
-        /* Must be set according to the MSR, but can be cleared in case of EPT. */
+        Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n",  val2));
+
+        /*
+         * Must be set according to the MSR, but can be cleared if nested paging is used.
+         */
         if (pVM->hwaccm.s.fNestedPaging)
+        {
             val2 |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
                     | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
                     | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
+        }
 
         /* allowed zero */
@@ -2565 +2742 @@
         rc2 = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val2);
         AssertRC(rc2);
-        Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val2));
+        Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n",  val2));
 
         /* allowed zero */
@@ -2577 +2754 @@
         rc2 = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val2);
         AssertRC(rc2);
-        Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val2));
+        Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n",  val2));
 
         /* allowed zero */
@@ -2594 +2771 @@
 #endif
 
-    /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
+    /*
+     * We can jump to this point to resume execution after determining that a VM-exit is innocent.
      */
 ResumeExecution:
@@ -2606 +2784 @@
     Assert(fWasInLongMode == CPUMIsGuestInLongModeEx(pCtx));
 
-    /* Safety precaution; looping for too long here can have a very bad effect on the host */
+    /*
+     * Safety precaution; looping for too long here can have a very bad effect on the host.
+     */
     if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
     {
@@ -2614 +2794 @@
     }
 
-    /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
+    /*
+     * Check for IRQ inhibition due to instruction fusing (sti, mov ss).
+     */
     if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     {
@@ -2620 +2802 @@
         if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
         {
-            /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
+            /*
+             * Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
              * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
              * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
@@ -2651 +2834 @@
 #endif
 
-    /* Check for pending actions that force us to go back to ring 3. */
+    /*
+     * Check for pending actions that force us to go back to ring-3.
+     */
     if (    VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
         ||  VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
@@ -2725 +2910 @@
 #endif
 
-    /* When external interrupts are pending, we should exit the VM when IF is set. */
-    /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
+    /*
+     * When external interrupts are pending, we should exit the VM when IF is et.
+     * Note: *After* VM_FF_INHIBIT_INTERRUPTS check!
+     */
     rc = hmR0VmxCheckPendingInterrupt(pVM, pVCpu, pCtx);
     if (RT_FAILURE(rc))
@@ -2733 +2920 @@
     /** @todo check timers?? */
 
-    /* TPR caching using CR8 is only available in 64 bits mode */
-    /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
-    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! (no longer true) */
-    /**
-     * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
-     */
+    /*
+     * TPR caching using CR8 is only available in 64-bit mode.
+     * Note: The 32-bit exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but this appears missing in Intel CPUs.
+     * Note: We can't do this in LoadGuestState() as PDMApicGetTPR can jump back to ring-3 (lock)!! (no longer true)                                                                                                           .
+     */
+    /** @todo query and update the TPR only when it could have been changed (mmio
+     *        access & wrsmr (x2apic) */
     if (fSetupTPRCaching)
     {
@@ -2749 +2937 @@
         pVCpu->hwaccm.s.vmx.pbVAPIC[0x80] = u8LastTPR;
 
-        /* Two options here:
+        /*
+         * Two options here:
          * - external interrupt pending, but masked by the TPR value.
          *   -> a CR8 update that lower the current TPR value should cause an exit
@@ -2771 +2960 @@
             else
             {
-                /* No interrupts are pending, so we don't need to be explicitely notified.
+                /*
+                 * No interrupts are pending, so we don't need to be explicitely notified.
                  * There are enough world switches for detecting pending interrupts.
                  */
@@ -2801 +2991 @@
 
     /*
-     * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
+     * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING-3!
      *       (until the actual world switch)
      */
@@ -2810 +3000 @@
     VMMR0LogFlushDisable(pVCpu);
 #endif
-    /* Save the host state first. */
+
+    /*
+     * Save the host state first.
+     */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
     {
@@ -2821 +3014 @@
     }
 
-    /* Load the guest state */
+    /*
+     * Load the guest state.
+     */
     if (!pVCpu->hwaccm.s.fContextUseFlags)
     {
@@ -2839 +3034 @@
 
 #ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
-    /* Disable interrupts to make sure a poke will interrupt execution.
+    /*
+     * Disable interrupts to make sure a poke will interrupt execution.
      * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
      */
@@ -2856 +3052 @@
     pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
 
-    /* Manual save and restore:
+    /*
+     * Manual save and restore:
      * - General purpose registers except RIP, RSP
      *
@@ -2865 +3062 @@
      * - DR7 (reset to 0x400)
      * - EFLAGS (reset to RT_BIT(1); not relevant)
-     *
      */
 
@@ -2877 +3073 @@
 #endif
 
-    /* Save the current TPR value in the LSTAR msr so our patches can access it. */
+    /*
+     * Save the current TPR value in the LSTAR MSR so our patches can access it.
+     */
     if (pVM->hwaccm.s.fTPRPatchingActive)
     {
@@ -2893 +3091 @@
     ASMAtomicWriteBool(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
     ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExits);
-    /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
+    /* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */
     if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT))
-        TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVCpu->hwaccm.s.vmx.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
+    {
+        TMCpuTickSetLastSeen(pVCpu,
+                             ASMReadTSC() + pVCpu->hwaccm.s.vmx.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
+    }
 
     TMNotifyEndOfExecution(pVCpu);
@@ -2901 +3102 @@
     Assert(!(ASMGetFlags() & X86_EFL_IF));
 
-    /* Restore the host LSTAR msr if the guest could have changed it. */
+    /*
+     * Restore the host LSTAR MSR if the guest could have changed it.
+     */
     if (pVM->hwaccm.s.fTPRPatchingActive)
     {
@@ -2950 +3153 @@
     AssertRC(rc2);
 
-    /* Sync back the guest state */
+    /*
+     * Sync back the guest state.
+     */
     rc2 = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
     AssertRC(rc2);
@@ -2961 +3166 @@
 #endif
 
-    /* Check if an injected event was interrupted prematurely. */
+    /*
+     * Check if an injected event was interrupted prematurely.
+     */
     rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO,            &val);
     AssertRC(rc2);
@@ -2979 +3186 @@
             AssertRC(rc2);
             pVCpu->hwaccm.s.Event.errCode  = val;
-            Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
+            Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n",
+                 pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
         }
         else
         {
-            Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
+            Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo,
+                 (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
             pVCpu->hwaccm.s.Event.errCode  = 0;
         }
     }
 #ifdef VBOX_STRICT
-    else
-    if (    VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
-        /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
-        &&  VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
-    {
-        Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
+    else if (   VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
+                /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
+             && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
+    {
+        Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n",
+             pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
     }
 
@@ -3006 +3215 @@
     Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
 
-    /* Sync back the TPR if it was changed. */
+    /*
+     * Sync back the TPR if it was changed.
+     */
     if (    fSetupTPRCaching
         &&  u8LastTPR != pVCpu->hwaccm.s.vmx.pbVAPIC[0x80])
@@ -3083 +3294 @@
                 Log(("Forward #NM fault to the guest\n"));
                 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
-                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
+                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                         cbInstr, 0);
                 AssertRC(rc2);
                 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
@@ -3093 +3305 @@
 #ifdef VBOX_ALWAYS_TRAP_PF
                 if (pVM->hwaccm.s.fNestedPaging)
-                {   /* A genuine pagefault.
-                     * Forward the trap to the guest by injecting the exception and resuming execution.
+                {
+                    /*
+                     * A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
                      */
-                    Log(("Guest page fault at %RGv cr2=%RGv error code %RGv rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
+                    Log(("Guest page fault at %RGv cr2=%RGv error code %RGv rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification,
+                         errCode, (RTGCPTR)pCtx->rsp));
 
                     Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
@@ -3104 +3318 @@
                     /* Now we must update CR2. */
                     pCtx->cr2 = exitQualification;
-                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                             cbInstr, errCode);
                     AssertRC(rc2);
 
@@ -3110 +3325 @@
                     goto ResumeExecution;
                 }
-#endif
+#else
                 Assert(!pVM->hwaccm.s.fNestedPaging);
+#endif
 
 #ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
@@ -3124 +3340 @@
                 {
                     RTGCPHYS GCPhysApicBase, GCPhys;
-                    PDMApicGetBase(pVM, &GCPhysApicBase);   /* @todo cache this */
+                    PDMApicGetBase(pVM, &GCPhysApicBase);   /** @todo cache this */
                     GCPhysApicBase &= PAGE_BASE_GC_MASK;
 
@@ -3181 +3397 @@
                     goto ResumeExecution;
                 }
-                else
-                if (rc == VINF_EM_RAW_GUEST_TRAP)
-                {   /* A genuine pagefault.
-                     * Forward the trap to the guest by injecting the exception and resuming execution.
+                else if (rc == VINF_EM_RAW_GUEST_TRAP)
+                {
+                    /*
+                     * A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
                      */
                     Log2(("Forward page fault to the guest\n"));
@@ -3196 +3412 @@
                     /* Now we must update CR2. */
                     pCtx->cr2 = exitQualification;
-                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                             cbInstr, errCode);
                     AssertRC(rc2);
 
@@ -3223 +3440 @@
                 }
                 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
-                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                         cbInstr, errCode);
                 AssertRC(rc2);
 
@@ -3234 +3452 @@
                 uint64_t uDR6;
 
-                /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
+                /*
+                 * DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
                  *
                  * Exit qualification bits:
@@ -3259 +3478 @@
                         ASMSetDR6(pCtx->dr[6]);
 
-                    /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
+                    /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
                     pCtx->dr[7] &= ~X86_DR7_GD;
 
@@ -3271 +3490 @@
                     AssertRC(rc2);
 
-                    Log(("Trap %x (debug) at %RGv exit qualification %RX64 dr6=%x dr7=%x\n", vector, (RTGCPTR)pCtx->rip, exitQualification, (uint32_t)pCtx->dr[6], (uint32_t)pCtx->dr[7]));
-                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                    Log(("Trap %x (debug) at %RGv exit qualification %RX64 dr6=%x dr7=%x\n", vector, (RTGCPTR)pCtx->rip,
+                         exitQualification, (uint32_t)pCtx->dr[6], (uint32_t)pCtx->dr[7]));
+                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                             cbInstr, errCode);
                     AssertRC(rc2);
 
@@ -3290 +3511 @@
                 {
                     Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
-                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                             cbInstr, errCode);
                     AssertRC(rc2);
                     STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
@@ -3304 +3526 @@
             }
 
-            case X86_XCPT_GP:   /* General protection failure exception.*/
+            case X86_XCPT_GP:   /* General protection failure exception. */
             {
                 uint32_t     cbOp;
@@ -3315 +3537 @@
                 {
                     Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
-                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                             cbInstr, errCode);
                     AssertRC(rc2);
                     STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
@@ -3343 +3566 @@
                         EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->opsize);
                         Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
-                        rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
+                        rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,
+                                           VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
                         AssertRC(rc2);
                         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
@@ -3415 +3639 @@
                         }
 
-                        rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
+                        rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0,
+                                           &GCPtrStack);
                         if (RT_FAILURE(rc2))
                         {
@@ -3466 +3691 @@
                         pCtx->cs            = aIretFrame[1];
                         pCtx->csHid.u64Base = pCtx->cs << 4;
-                        pCtx->eflags.u      = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
+                        pCtx->eflags.u      =   (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask))
+                                              | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
                         pCtx->sp           += sizeof(aIretFrame);
 
@@ -3537 +3763 @@
                             pCtx->rip += cbOp; /* Move on to the next instruction. */
 
-                        /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
+                        /*
+                         * LIDT, LGDT can end up here. In the future CRx changes as well. Just reload the
+                         * whole context to be done with it.
+                         */
                         pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
 
@@ -3561 +3790 @@
                 switch(vector)
                 {
-                case X86_XCPT_DE:
-                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
-                    break;
-                case X86_XCPT_UD:
-                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
-                    break;
-                case X86_XCPT_SS:
-                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
-                    break;
-                case X86_XCPT_NP:
-                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
-                    break;
-                case X86_XCPT_XF:
-                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestXF);
-                    break;
+                    case X86_XCPT_DE:
+                        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
+                        break;
+                    case X86_XCPT_UD:
+                        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
+                        break;
+                    case X86_XCPT_SS:
+                        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
+                        break;
+                    case X86_XCPT_NP:
+                        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
+                        break;
+                    case X86_XCPT_XF:
+                        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestXF);
+                        break;
                 }
 
                 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
-                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                         cbInstr, errCode);
                 AssertRC(rc2);
 
@@ -3592 +3822 @@
                 {
                     Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
-                    rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
+                    rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                            cbInstr, errCode);
                     AssertRC(VBOXSTRICTRC_VAL(rc)); /* Strict RC check below. */
 
-                    /* Go back to ring 3 in case of a triple fault. */
-                    if (    vector == X86_XCPT_DF
-                        &&  rc == VINF_EM_RESET)
+                    /* Go back to ring-3 in case of a triple fault. */
+                    if (   vector == X86_XCPT_DF
+                        && rc == VINF_EM_RESET)
+                    {
                         break;
+                    }
 
                     STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
@@ -3620 +3853 @@
     }
 
-    case VMX_EXIT_EPT_VIOLATION:        /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
+    /*
+     * 48 EPT violation. An attemp to access memory with a guest-physical address was disallowed
+     * by the configuration of the EPT paging structures.
+     */
+    case VMX_EXIT_EPT_VIOLATION:
     {
         RTGCPHYS GCPhys;
@@ -3640 +3877 @@
         /* If the page is present, then it's a page level protection fault. */
         if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
-        {
             errCode |= X86_TRAP_PF_P;
-        }
         else
         {
             /* Shortcut for APIC TPR reads and writes. */
             if (    (GCPhys & 0xfff) == 0x080
-                &&  GCPhys > 0x1000000   /* to skip VGA frame buffer accesses */
+                &&  GCPhys > 0x1000000          /* to skip VGA frame buffer accesses */
                 &&  fSetupTPRCaching
                 &&  (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
@@ -3678 +3913 @@
             || rc == VERR_PAGE_TABLE_NOT_PRESENT
             || rc == VERR_PAGE_NOT_PRESENT)
-        {   /* We've successfully synced our shadow pages, so let's just continue execution. */
+        {
+            /* We've successfully synced our shadow pages, so let's just continue execution. */
             Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
             STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
@@ -3707 +3943 @@
         /* Shortcut for APIC TPR reads and writes. */
         if (    (GCPhys & 0xfff) == 0x080
-            &&  GCPhys > 0x1000000   /* to skip VGA frame buffer accesses */
+            &&  GCPhys > 0x1000000              /* to skip VGA frame buffer accesses */
             &&  fSetupTPRCaching
             &&  (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
@@ -3745 +3981 @@
     case VMX_EXIT_IRQ_WINDOW:           /* 7 Interrupt window. */
         /* Clear VM-exit on IF=1 change. */
-        LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
+        LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip,
+                 VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
         pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
         rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
@@ -3869 +4106 @@
         STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
 
-        /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
+        /*
+         * Note: The Intel spec. claims there's an REX version of RDMSR that's slightly different,
+         * so we play safe by completely disassembling the instruction.
+         */
         Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
         rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
@@ -3875 +4115 @@
         {
             /* EIP has been updated already. */
-
             /* Only resume if successful. */
             goto ResumeExecution;
         }
-        AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
+        AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n",
+                                              (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
         break;
     }
@@ -3889 +4129 @@
         switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
         {
-        case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
-            Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
-            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
-            rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
-                                     VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
-                                     VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
-
-            switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
+            case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
             {
-            case 0:
-                pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
-                break;
-            case 2:
-                break;
-            case 3:
-                Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
-                pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
-                break;
-            case 4:
-                pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
-                break;
-            case 8:
-                /* CR8 contains the APIC TPR */
-                Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
-                break;
-
-            default:
-                AssertFailed();
+                Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
+                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
+                rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
+                                         VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
+                                         VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
+                switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
+                {
+                    case 0:
+                        pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
+                        break;
+                    case 2:
+                        break;
+                    case 3:
+                        Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
+                        pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
+                        break;
+                    case 4:
+                        pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
+                        break;
+                    case 8:
+                        /* CR8 contains the APIC TPR */
+                        Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1
+                                 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
+                        break;
+
+                    default:
+                        AssertFailed();
+                        break;
+                }
                 break;
             }
-            break;
-
-        case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
-            Log2(("VMX: mov x, crx\n"));
-            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
-
-            Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
-
-            /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
-            Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
-
-            rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
-                                    VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
-                                    VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
-            break;
-
-        case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
-            Log2(("VMX: clts\n"));
-            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
-            rc = EMInterpretCLTS(pVM, pVCpu);
-            pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
-            break;
-
-        case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
-            Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
-            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
-            rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
-            pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
-            break;
+
+            case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
+            {
+                Log2(("VMX: mov x, crx\n"));
+                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
+
+                Assert(   !pVM->hwaccm.s.fNestedPaging
+                       || !CPUMIsGuestInPagedProtectedModeEx(pCtx)
+                       || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
+
+                /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
+                Assert(   VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8
+                       || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
+
+                rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
+                                        VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
+                                        VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
+                break;
+            }
+
+            case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
+            {
+                Log2(("VMX: clts\n"));
+                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
+                rc = EMInterpretCLTS(pVM, pVCpu);
+                pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
+                break;
+            }
+
+            case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
+            {
+                Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
+                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
+                rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
+                pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
+                break;
+            }
         }
 
@@ -3970 +4221 @@
             &&  !CPUMIsHyperDebugStateActive(pVCpu))
         {
-            /* Disable drx move intercepts. */
+            /* Disable DRx move intercepts. */
             pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
             rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
@@ -3981 +4232 @@
 #ifdef LOG_ENABLED
             if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
-                Log(("VMX_EXIT_DRX_MOVE: write DR%d genreg %d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
+            {
+                Log(("VMX_EXIT_DRX_MOVE: write DR%d genreg %d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
+                     VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
+            }
             else
                 Log(("VMX_EXIT_DRX_MOVE: read DR%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification)));
@@ -3997 +4251 @@
         }
 
-        /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
+        /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first
+         *        time and restore DRx registers afterwards */
         if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
         {
-            Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
+            Log2(("VMX: mov DRx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
+                  VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
             STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
             rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
@@ -4010 +4266 @@
         else
         {
-            Log2(("VMX: mov x, drx\n"));
+            Log2(("VMX: mov x, DRx\n"));
             STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
             rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
@@ -4033 +4289 @@
     {
         STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
+        uint32_t uPort;
         uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
-        uint32_t uPort;
         bool     fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
 
         /** @todo necessary to make the distinction? */
         if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
-        {
             uPort = pCtx->edx & 0xffff;
-        }
         else
             uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification);  /* Immediate encoding. */
 
-        /* paranoia */
-        if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
+        if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))         /* paranoia */
         {
             rc = fIOWrite ? VINF_IOM_R3_IOPORT_WRITE : VINF_IOM_R3_IOPORT_READ;
@@ -4054 +4307 @@
 
         uint32_t cbSize = g_aIOSize[uIOWidth];
-
         if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
         {
@@ -4084 +4336 @@
         else
         {
-            /* normal in/out */
+            /* Normal in/out */
             uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
 
@@ -4112 +4364 @@
             }
         }
+
         /*
          * Handled the I/O return codes.
@@ -4126 +4379 @@
                 {
                     STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
-                    for (unsigned i=0;i<4;i++)
+                    for (unsigned i = 0; i < 4; i++)
                     {
                         unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
@@ -4144 +4397 @@
                             uDR6 |= (uint64_t)RT_BIT(i);
 
-                            /* Note: AMD64 Architecture Programmer's Manual 13.1:
-                             * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
-                             * the contents have been read.
+                            /*
+                             * Note: AMD64 Architecture Programmer's Manual 13.1:
+                             * Bits 15:13 of the DR6 register is never cleared by the processor and must
+                             * be cleared by software after the contents have been read.
                              */
                             ASMSetDR6(uDR6);
 
-                            /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
+                            /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
                             pCtx->dr[7] &= ~X86_DR7_GD;
 
@@ -4168 +4422 @@
 
                             Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
-                            rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
+                            rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
+                                                     0 /* cbInstr */, 0 /* errCode */);
                             AssertRC(rc2);
 
@@ -4189 +4444 @@
             Assert(fIOWrite);
         else
-            AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
+        {
+            AssertMsg(   RT_FAILURE(rc)
+                      || rc == VINF_EM_RAW_EMULATE_INSTR
+                      || rc == VINF_EM_RAW_GUEST_TRAP
+                      || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
+        }
 #endif
         STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
@@ -4200 +4460 @@
         goto ResumeExecution;
 
-    case VMX_EXIT_APIC_ACCESS:          /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
+    case VMX_EXIT_APIC_ACCESS:          /* 44 APIC access. Guest software attempted to access memory at a physical address
+                                                            on the APIC-access page. */
     {
         LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
@@ -4207 +4468 @@
         switch(uAccessType)
         {
-        case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
-        case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
-        {
-            RTGCPHYS GCPhys;
-            PDMApicGetBase(pVM, &GCPhys);
-            GCPhys &= PAGE_BASE_GC_MASK;
-            GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
-
-            LogFlow(("Apic access at %RGp\n", GCPhys));
-            rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
-            if (rc == VINF_SUCCESS)
-                goto ResumeExecution;   /* rip already updated */
-            break;
-        }
-
-        default:
-            rc = VINF_EM_RAW_EMULATE_INSTR;
-            break;
+            case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
+            case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
+            {
+                RTGCPHYS GCPhys;
+                PDMApicGetBase(pVM, &GCPhys);
+                GCPhys &= PAGE_BASE_GC_MASK;
+                GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
+
+                LogFlow(("Apic access at %RGp\n", GCPhys));
+                rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW,
+                                        CPUMCTX2CORE(pCtx), GCPhys);
+                if (rc == VINF_SUCCESS)
+                    goto ResumeExecution;   /* rip already updated */
+                break;
+            }
+
+            default:
+                rc = VINF_EM_RAW_EMULATE_INSTR;
+                break;
         }
         break;
@@ -4240 +4502 @@
     }
 
-    /* Note: the guest state isn't entirely synced back at this stage. */
+
+    /*
+     * Note: The guest state is not entirely synced back at this stage!
+     */
 
     /* Investigate why there was a VM-exit. (part 2) */
@@ -4369 +4634 @@
 
     case VMX_EXIT_TPR:                  /* 43 TPR below threshold. Guest software executed MOV to CR8. */
-    case VMX_EXIT_APIC_ACCESS:          /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
     case VMX_EXIT_RDMSR:                /* 31 RDMSR. Guest software attempted to execute RDMSR. */
     case VMX_EXIT_WRMSR:                /* 32 WRMSR. Guest software attempted to execute WRMSR. */
     case VMX_EXIT_PAUSE:                /* 40 Guest software attempted to execute PAUSE. */
     case VMX_EXIT_MONITOR:              /* 39 Guest software attempted to execute MONITOR. */
-        /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
+    case VMX_EXIT_APIC_ACCESS:          /* 44 APIC access. Guest software attempted to access memory at a physical address
+                                                        on the APIC-access page. */
+    {
+        /*
+         * If we decided to emulate them here, then we must sync the MSRs that could have been changed (sysenter, FS/GS base)
+         */
         rc = VERR_EM_INTERPRETER;
         break;
+    }
 
     case VMX_EXIT_IRQ_WINDOW:           /* 7 Interrupt window. */
@@ -4404 +4674 @@
         Log(("VMX_VMCS_GUEST_RFLAGS     %08x\n", val2));
 
-        VMX_LOG_SELREG(CS, "CS", val2);
-        VMX_LOG_SELREG(DS, "DS", val2);
-        VMX_LOG_SELREG(ES, "ES", val2);
-        VMX_LOG_SELREG(FS, "FS", val2);
-        VMX_LOG_SELREG(GS, "GS", val2);
-        VMX_LOG_SELREG(SS, "SS", val2);
-        VMX_LOG_SELREG(TR, "TR", val2);
+        VMX_LOG_SELREG(CS,   "CS",   val2);
+        VMX_LOG_SELREG(DS,   "DS",   val2);
+        VMX_LOG_SELREG(ES,   "ES",   val2);
+        VMX_LOG_SELREG(FS,   "FS",   val2);
+        VMX_LOG_SELREG(GS,   "GS",   val2);
+        VMX_LOG_SELREG(SS,   "SS",   val2);
+        VMX_LOG_SELREG(TR,   "TR",   val2);
         VMX_LOG_SELREG(LDTR, "LDTR", val2);
 
@@ -4430 +4700 @@
 
     }
+
 end:
-
     /* We now going back to ring-3, so clear the action flag. */
     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
 
-    /* Signal changes for the recompiler. */
-    CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
-
-    /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
+    /*
+     * Signal changes for the recompiler.
+     */
+    CPUMSetChangedFlags(pVCpu,
+                          CPUM_CHANGED_SYSENTER_MSR
+                        | CPUM_CHANGED_LDTR
+                        | CPUM_CHANGED_GDTR
+                        | CPUM_CHANGED_IDTR
+                        | CPUM_CHANGED_TR
+                        | CPUM_CHANGED_HIDDEN_SEL_REGS);
+
+    /*
+     * If we executed vmlaunch/vmresume and an external IRQ was pending, then we don't have to do a full sync the next time.
+     */
     if (    exitReason == VMX_EXIT_EXTERNAL_IRQ
         &&  !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
@@ -4454 +4734 @@
     }
 
-    /* translate into a less severe return code */
+    /* Translate into a less severe return code */
     if (rc == VERR_EM_INTERPRETER)
         rc = VINF_EM_RAW_EMULATE_INSTR;
-    else
-    /* Try to extract more information about what might have gone wrong here. */
-    if (rc == VERR_VMX_INVALID_VMCS_PTR)
-    {
+    else if (rc == VERR_VMX_INVALID_VMCS_PTR)
+    {
+        /* Try to extract more information about what might have gone wrong here. */
         VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
         pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pvVMCS;
@@ -4471 +4750 @@
 
 #ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
-    /* Restore interrupts if we exitted after disabling them. */
+    /* Restore interrupts if we exited after disabling them. */
     if (uOldEFlags != ~(RTCCUINTREG)0)
         ASMSetFlags(uOldEFlags);
@@ -4485 +4764 @@
 
 /**
- * Enters the VT-x session
+ * Enters the VT-x session.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCpu        CPU info struct
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCpu        Pointer to the CPU info struct.
  */
 VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
@@ -4504 +4783 @@
     }
 
-    /* Activate the VM Control Structure. */
+    /* Activate the VMCS. */
     int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
     if (RT_FAILURE(rc))
@@ -4515 +4794 @@
 
 /**
- * Leaves the VT-x session
+ * Leaves the VT-x session.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        CPU context
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guests CPU context.
  */
 VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -4534 +4813 @@
     else
 #endif
-    /* Save the guest debug state if necessary. */
+
+    /*
+     * Save the guest debug state if necessary.
+     */
     if (CPUMIsGuestDebugStateActive(pVCpu))
     {
         CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
 
-        /* Enable drx move intercepts again. */
+        /* Enable DRx move intercepts again. */
         pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
         int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
@@ -4550 +4832 @@
         Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
 
-    /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
+    /*
+     * Clear VMCS, marking it inactive, clearing implementation-specific data and writing
+     * VMCS data back to memory.
+     */
     int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
     AssertRC(rc);
@@ -4562 +4847 @@
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VM CPU to operate on.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
  * @param   enmFlush    Type of flush.
  */
@@ -4583 +4868 @@
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VM CPU to operate on (can be NULL depending on @a
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU (can be NULL depending on @a
  *                      enmFlush).
  * @param   enmFlush    Type of flush.
@@ -4593 +4878 @@
 {
 #if HC_ARCH_BITS == 32
-    /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
+    /*
+     * If we get a flush in 64-bit guest mode, then force a full TLB flush. invvpid probably takes only 32-bit addresses.
+     */
     if (   CPUMIsGuestInLongMode(pVCpu)
         && !VMX_IS_64BIT_HOST_MODE())
@@ -4629 +4916 @@
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VM CPU to operate on.
- * @param   GCVirt      Page to invalidate.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   GCVirt      Guest virtual address of the page to invalidate.
  */
 VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
@@ -4671 +4958 @@
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
+ * @param   pVM         Pointer to the VM.
  * @param   pVCpu       The VM CPU to operate on.
- * @param   GCPhys      Page to invalidate.
+ * @param   GCPhys      Guest physical address of the page to invalidate.
  */
 VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
@@ -4690 +4977 @@
 
 /**
- * Report world switch error and dump some useful debug info
+ * Report world switch error and dump some useful debug info.
  *
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   rc          Return code
- * @param   pCtx        Current CPU context (not updated)
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   rc          Return code.
+ * @param   pCtx        Pointer to the current guest CPU context (not updated).
  */
 static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx)
@@ -4703 +4990 @@
     switch (VBOXSTRICTRC_VAL(rc))
     {
-    case VERR_VMX_INVALID_VMXON_PTR:
-        AssertFailed();
-        break;
-
-    case VERR_VMX_UNABLE_TO_START_VM:
-    case VERR_VMX_UNABLE_TO_RESUME_VM:
-    {
-        int         rc2;
-        RTCCUINTREG exitReason, instrError;
-
-        rc2  = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
-        rc2 |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
-        AssertRC(rc2);
-        if (rc2 == VINF_SUCCESS)
-        {
-            Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
-            Log(("Current stack %08x\n", &rc2));
-
-            pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
-            pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
+        case VERR_VMX_INVALID_VMXON_PTR:
+            AssertFailed();
+            break;
+
+        case VERR_VMX_UNABLE_TO_START_VM:
+        case VERR_VMX_UNABLE_TO_RESUME_VM:
+        {
+            int         rc2;
+            RTCCUINTREG exitReason, instrError;
+
+            rc2  = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
+            rc2 |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
+            AssertRC(rc2);
+            if (rc2 == VINF_SUCCESS)
+            {
+                Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason,
+                     (uint32_t)instrError));
+                Log(("Current stack %08x\n", &rc2));
+
+                pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
+                pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
 
 #ifdef VBOX_STRICT
-            RTGDTR      gdtr;
-            PCX86DESCHC pDesc;
-            RTCCUINTREG val;
-
-            ASMGetGDTR(&gdtr);
-
-            VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
-            Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
-            VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
-            Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS   %08x\n", val));
-            VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
-            Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS  %08x\n", val));
-            VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
-            Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS      %08x\n", val));
-            VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
-            Log(("VMX_VMCS_CTRL_EXIT_CONTROLS       %08x\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
-            Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
-            Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
-            Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
-            Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
-
-            VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
-            Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
-
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
-            Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
-            Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
-            Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
-            Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
-            Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
-            Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
-            if (val < gdtr.cbGdt)
-            {
-                pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
-                HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
-            }
-
-            VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
-            Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
-            Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
-            VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
-            Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
-
-            VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
-            Log(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
-            Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
-            Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
-
-            VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
-            Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
-            VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
-            Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
-
+                RTGDTR      gdtr;
+                PCX86DESCHC pDesc;
+                RTCCUINTREG val;
+
+                ASMGetGDTR(&gdtr);
+
+                VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
+                Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
+                VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS,    &val);
+                Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS   %08x\n", val));
+                VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS,   &val);
+                Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS  %08x\n", val));
+                VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS,       &val);
+                Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS      %08x\n", val));
+                VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS,        &val);
+                Log(("VMX_VMCS_CTRL_EXIT_CONTROLS       %08x\n", val));
+
+                VMXReadVMCS(VMX_VMCS_HOST_CR0,  &val);
+                Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
+                VMXReadVMCS(VMX_VMCS_HOST_CR3,  &val);
+                Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
+                VMXReadVMCS(VMX_VMCS_HOST_CR4,  &val);
+                Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
+                Log(("VMX_VMCS_HOST_FIELD_CS %08x\n",  val));
+                VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS,  &val);
+                Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
+
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
+                Log(("VMX_VMCS_HOST_FIELD_DS %08x\n",  val));
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
+                Log(("VMX_VMCS_HOST_FIELD_ES %08x\n",  val));
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
+                Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS,  &val);
+                Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS,  &val);
+                Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR,  &val);
+                Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
+                if (val < gdtr.cbGdt)
+                {
+                    pDesc  = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
+                    HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
+                }
+
+                VMXReadVMCS(VMX_VMCS_HOST_TR_BASE,         &val);
+                Log(("VMX_VMCS_HOST_TR_BASE %RHv\n",        val));
+                VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE,       &val);
+                Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n",      val));
+                VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE,       &val);
+                Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n",      val));
+                VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS,   &val);
+                Log(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n",   val));
+                VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP,    &val);
+                Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n",   val));
+                VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP,    &val);
+                Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n",   val));
+                VMXReadVMCS(VMX_VMCS_HOST_RSP,             &val);
+                Log(("VMX_VMCS_HOST_RSP %RHv\n",            val));
+                VMXReadVMCS(VMX_VMCS_HOST_RIP,             &val);
+                Log(("VMX_VMCS_HOST_RIP %RHv\n",            val));
 # if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-            if (VMX_IS_64BIT_HOST_MODE())
-            {
-                Log(("MSR_K6_EFER       = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
-                Log(("MSR_K6_STAR       = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
-                Log(("MSR_K8_LSTAR      = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
-                Log(("MSR_K8_CSTAR      = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
-                Log(("MSR_K8_SF_MASK    = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
-            }
+                if (VMX_IS_64BIT_HOST_MODE())
+                {
+                    Log(("MSR_K6_EFER       = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
+                    Log(("MSR_K6_STAR       = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
+                    Log(("MSR_K8_LSTAR      = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
+                    Log(("MSR_K8_CSTAR      = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
+                    Log(("MSR_K8_SF_MASK    = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
+                }
 # endif
 #endif /* VBOX_STRICT */
-        }
-        break;
-    }
-
-    default:
-        /* impossible */
-        AssertMsgFailed(("%Rrc (%#x)\n", VBOXSTRICTRC_VAL(rc), VBOXSTRICTRC_VAL(rc)));
-        break;
+            }
+            break;
+        }
+
+        default:
+            /* impossible */
+            AssertMsgFailed(("%Rrc (%#x)\n", VBOXSTRICTRC_VAL(rc), VBOXSTRICTRC_VAL(rc)));
+            break;
     }
 }
 
+
 #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-
 /**
- * Prepares for and executes VMLAUNCH (64 bits guest mode)
+ * Prepares for and executes VMLAUNCH (64 bits guest mode).
  *
- * @returns VBox status code
- * @param   fResume     vmlauch/vmresume
- * @param   pCtx        Guest context
- * @param   pCache      VMCS cache
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
+ * @returns VBox status code.
+ * @param   fResume     Whether to vmlauch/vmresume.
+ * @param   pCtx        Pointer to the guest CPU context.
+ * @param   pCache      Pointer to the VMCS cache.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
  */
 DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
@@ -4914 +5193 @@
 #ifdef DEBUG
     AssertMsg(pCache->TestIn.HCPhysCpuPage== HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
-    AssertMsg(pCache->TestIn.HCPhysVMCS   == pVCpu->hwaccm.s.vmx.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS, pVCpu->hwaccm.s.vmx.HCPhysVMCS));
-    AssertMsg(pCache->TestIn.HCPhysVMCS   == pCache->TestOut.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS, pCache->TestOut.HCPhysVMCS));
-    AssertMsg(pCache->TestIn.pCache       == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
-    AssertMsg(pCache->TestIn.pCache       == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
-    AssertMsg(pCache->TestIn.pCtx         == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
+    AssertMsg(pCache->TestIn.HCPhysVMCS   == pVCpu->hwaccm.s.vmx.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS,
+                                                                              pVCpu->hwaccm.s.vmx.HCPhysVMCS));
+    AssertMsg(pCache->TestIn.HCPhysVMCS   == pCache->TestOut.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS,
+                                                                          pCache->TestOut.HCPhysVMCS));
+    AssertMsg(pCache->TestIn.pCache       == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
+                                                                      pCache->TestOut.pCache));
+    AssertMsg(pCache->TestIn.pCache       == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache),
+              ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
+    AssertMsg(pCache->TestIn.pCtx         == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
+                                                                    pCache->TestOut.pCtx));
     Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
 #endif
@@ -4924 +5208 @@
 }
 
+
 # ifdef VBOX_STRICT
-
 static bool hmR0VmxIsValidReadField(uint32_t idxField)
 {
-    switch(idxField)
-    {
-    case VMX_VMCS64_GUEST_RIP:
-    case VMX_VMCS64_GUEST_RSP:
-    case VMX_VMCS_GUEST_RFLAGS:
-    case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
-    case VMX_VMCS_CTRL_CR0_READ_SHADOW:
-    case VMX_VMCS64_GUEST_CR0:
-    case VMX_VMCS_CTRL_CR4_READ_SHADOW:
-    case VMX_VMCS64_GUEST_CR4:
-    case VMX_VMCS64_GUEST_DR7:
-    case VMX_VMCS32_GUEST_SYSENTER_CS:
-    case VMX_VMCS64_GUEST_SYSENTER_EIP:
-    case VMX_VMCS64_GUEST_SYSENTER_ESP:
-    case VMX_VMCS32_GUEST_GDTR_LIMIT:
-    case VMX_VMCS64_GUEST_GDTR_BASE:
-    case VMX_VMCS32_GUEST_IDTR_LIMIT:
-    case VMX_VMCS64_GUEST_IDTR_BASE:
-    case VMX_VMCS16_GUEST_FIELD_CS:
-    case VMX_VMCS32_GUEST_CS_LIMIT:
-    case VMX_VMCS64_GUEST_CS_BASE:
-    case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_DS:
-    case VMX_VMCS32_GUEST_DS_LIMIT:
-    case VMX_VMCS64_GUEST_DS_BASE:
-    case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_ES:
-    case VMX_VMCS32_GUEST_ES_LIMIT:
-    case VMX_VMCS64_GUEST_ES_BASE:
-    case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_FS:
-    case VMX_VMCS32_GUEST_FS_LIMIT:
-    case VMX_VMCS64_GUEST_FS_BASE:
-    case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_GS:
-    case VMX_VMCS32_GUEST_GS_LIMIT:
-    case VMX_VMCS64_GUEST_GS_BASE:
-    case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_SS:
-    case VMX_VMCS32_GUEST_SS_LIMIT:
-    case VMX_VMCS64_GUEST_SS_BASE:
-    case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_LDTR:
-    case VMX_VMCS32_GUEST_LDTR_LIMIT:
-    case VMX_VMCS64_GUEST_LDTR_BASE:
-    case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
-    case VMX_VMCS16_GUEST_FIELD_TR:
-    case VMX_VMCS32_GUEST_TR_LIMIT:
-    case VMX_VMCS64_GUEST_TR_BASE:
-    case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
-    case VMX_VMCS32_RO_EXIT_REASON:
-    case VMX_VMCS32_RO_VM_INSTR_ERROR:
-    case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
-    case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
-    case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
-    case VMX_VMCS32_RO_EXIT_INSTR_INFO:
-    case VMX_VMCS_RO_EXIT_QUALIFICATION:
-    case VMX_VMCS32_RO_IDT_INFO:
-    case VMX_VMCS32_RO_IDT_ERRCODE:
-    case VMX_VMCS64_GUEST_CR3:
-    case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
-        return true;
+    switch (idxField)
+    {
+        case VMX_VMCS64_GUEST_RIP:
+        case VMX_VMCS64_GUEST_RSP:
+        case VMX_VMCS_GUEST_RFLAGS:
+        case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
+        case VMX_VMCS_CTRL_CR0_READ_SHADOW:
+        case VMX_VMCS64_GUEST_CR0:
+        case VMX_VMCS_CTRL_CR4_READ_SHADOW:
+        case VMX_VMCS64_GUEST_CR4:
+        case VMX_VMCS64_GUEST_DR7:
+        case VMX_VMCS32_GUEST_SYSENTER_CS:
+        case VMX_VMCS64_GUEST_SYSENTER_EIP:
+        case VMX_VMCS64_GUEST_SYSENTER_ESP:
+        case VMX_VMCS32_GUEST_GDTR_LIMIT:
+        case VMX_VMCS64_GUEST_GDTR_BASE:
+        case VMX_VMCS32_GUEST_IDTR_LIMIT:
+        case VMX_VMCS64_GUEST_IDTR_BASE:
+        case VMX_VMCS16_GUEST_FIELD_CS:
+        case VMX_VMCS32_GUEST_CS_LIMIT:
+        case VMX_VMCS64_GUEST_CS_BASE:
+        case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_DS:
+        case VMX_VMCS32_GUEST_DS_LIMIT:
+        case VMX_VMCS64_GUEST_DS_BASE:
+        case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_ES:
+        case VMX_VMCS32_GUEST_ES_LIMIT:
+        case VMX_VMCS64_GUEST_ES_BASE:
+        case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_FS:
+        case VMX_VMCS32_GUEST_FS_LIMIT:
+        case VMX_VMCS64_GUEST_FS_BASE:
+        case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_GS:
+        case VMX_VMCS32_GUEST_GS_LIMIT:
+        case VMX_VMCS64_GUEST_GS_BASE:
+        case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_SS:
+        case VMX_VMCS32_GUEST_SS_LIMIT:
+        case VMX_VMCS64_GUEST_SS_BASE:
+        case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_LDTR:
+        case VMX_VMCS32_GUEST_LDTR_LIMIT:
+        case VMX_VMCS64_GUEST_LDTR_BASE:
+        case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
+        case VMX_VMCS16_GUEST_FIELD_TR:
+        case VMX_VMCS32_GUEST_TR_LIMIT:
+        case VMX_VMCS64_GUEST_TR_BASE:
+        case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
+        case VMX_VMCS32_RO_EXIT_REASON:
+        case VMX_VMCS32_RO_VM_INSTR_ERROR:
+        case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
+        case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
+        case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
+        case VMX_VMCS32_RO_EXIT_INSTR_INFO:
+        case VMX_VMCS_RO_EXIT_QUALIFICATION:
+        case VMX_VMCS32_RO_IDT_INFO:
+        case VMX_VMCS32_RO_IDT_ERRCODE:
+        case VMX_VMCS64_GUEST_CR3:
+        case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
+            return true;
     }
     return false;
 }
 
+
 static bool hmR0VmxIsValidWriteField(uint32_t idxField)
 {
-    switch(idxField)
-    {
-    case VMX_VMCS64_GUEST_LDTR_BASE:
-    case VMX_VMCS64_GUEST_TR_BASE:
-    case VMX_VMCS64_GUEST_GDTR_BASE:
-    case VMX_VMCS64_GUEST_IDTR_BASE:
-    case VMX_VMCS64_GUEST_SYSENTER_EIP:
-    case VMX_VMCS64_GUEST_SYSENTER_ESP:
-    case VMX_VMCS64_GUEST_CR0:
-    case VMX_VMCS64_GUEST_CR4:
-    case VMX_VMCS64_GUEST_CR3:
-    case VMX_VMCS64_GUEST_DR7:
-    case VMX_VMCS64_GUEST_RIP:
-    case VMX_VMCS64_GUEST_RSP:
-    case VMX_VMCS64_GUEST_CS_BASE:
-    case VMX_VMCS64_GUEST_DS_BASE:
-    case VMX_VMCS64_GUEST_ES_BASE:
-    case VMX_VMCS64_GUEST_FS_BASE:
-    case VMX_VMCS64_GUEST_GS_BASE:
-    case VMX_VMCS64_GUEST_SS_BASE:
-        return true;
+    switch (idxField)
+    {
+        case VMX_VMCS64_GUEST_LDTR_BASE:
+        case VMX_VMCS64_GUEST_TR_BASE:
+        case VMX_VMCS64_GUEST_GDTR_BASE:
+        case VMX_VMCS64_GUEST_IDTR_BASE:
+        case VMX_VMCS64_GUEST_SYSENTER_EIP:
+        case VMX_VMCS64_GUEST_SYSENTER_ESP:
+        case VMX_VMCS64_GUEST_CR0:
+        case VMX_VMCS64_GUEST_CR4:
+        case VMX_VMCS64_GUEST_CR3:
+        case VMX_VMCS64_GUEST_DR7:
+        case VMX_VMCS64_GUEST_RIP:
+        case VMX_VMCS64_GUEST_RSP:
+        case VMX_VMCS64_GUEST_CS_BASE:
+        case VMX_VMCS64_GUEST_DS_BASE:
+        case VMX_VMCS64_GUEST_ES_BASE:
+        case VMX_VMCS64_GUEST_FS_BASE:
+        case VMX_VMCS64_GUEST_GS_BASE:
+        case VMX_VMCS64_GUEST_SS_BASE:
+            return true;
     }
     return false;
 }
-
 # endif /* VBOX_STRICT */
 
+
 /**
- * Executes the specified handler in 64 mode
+ * Executes the specified handler in 64-bit mode.
  *
  * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- * @param   pVCpu       The VMCPU to operate on.
- * @param   pCtx        Guest context
- * @param   pfnHandler  RC handler
- * @param   cbParam     Number of parameters
- * @param   paParam     Array of 32 bits parameters
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pCtx        Pointer to the guest CPU context.
+ * @param   pfnHandler  Pointer to the RC handler function.
+ * @param   cbParam     Number of parameters.
+ * @param   paParam     Array of 32-bit parameters.
  */
-VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
+VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam,
+                                         uint32_t *paParam)
 {
     int             rc, rc2;
@@ -5060 +5346 @@
     HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
 
-    /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
+    /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
     VMXClearVMCS(pVCpu->hwaccm.s.vmx.HCPhysVMCS);
 
@@ -5074 +5360 @@
 
     STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
+
     /* Call switcher. */
     rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
@@ -5096 +5383 @@
     return rc;
 }
-
 #endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
 
@@ -5102 +5388 @@
 #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
 /**
- * Executes VMWRITE
+ * Executes VMWRITE.
  *
  * @returns VBox status code
- * @param   pVCpu           The VMCPU to operate on.
- * @param   idxField        VMCS index
- * @param   u64Val          16, 32 or 64 bits value
+ * @param   pVCpu           Pointer to the VMCPU.
+ * @param   idxField        VMCS field index.
+ * @param   u64Val          16, 32 or 64 bits value.
  */
 VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
 {
     int rc;
-
     switch (idxField)
     {
-    case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
-    case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
-    case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
-    case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
-    case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
-    case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
-    case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
-    case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
-    case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
-    case VMX_VMCS_GUEST_LINK_PTR_FULL:
-    case VMX_VMCS_GUEST_PDPTR0_FULL:
-    case VMX_VMCS_GUEST_PDPTR1_FULL:
-    case VMX_VMCS_GUEST_PDPTR2_FULL:
-    case VMX_VMCS_GUEST_PDPTR3_FULL:
-    case VMX_VMCS_GUEST_DEBUGCTL_FULL:
-    case VMX_VMCS_GUEST_EFER_FULL:
-    case VMX_VMCS_CTRL_EPTP_FULL:
-        /* These fields consist of two parts, which are both writable in 32 bits mode. */
-        rc  = VMXWriteVMCS32(idxField, u64Val);
-        rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
-        AssertRC(rc);
-        return rc;
-
-    case VMX_VMCS64_GUEST_LDTR_BASE:
-    case VMX_VMCS64_GUEST_TR_BASE:
-    case VMX_VMCS64_GUEST_GDTR_BASE:
-    case VMX_VMCS64_GUEST_IDTR_BASE:
-    case VMX_VMCS64_GUEST_SYSENTER_EIP:
-    case VMX_VMCS64_GUEST_SYSENTER_ESP:
-    case VMX_VMCS64_GUEST_CR0:
-    case VMX_VMCS64_GUEST_CR4:
-    case VMX_VMCS64_GUEST_CR3:
-    case VMX_VMCS64_GUEST_DR7:
-    case VMX_VMCS64_GUEST_RIP:
-    case VMX_VMCS64_GUEST_RSP:
-    case VMX_VMCS64_GUEST_CS_BASE:
-    case VMX_VMCS64_GUEST_DS_BASE:
-    case VMX_VMCS64_GUEST_ES_BASE:
-    case VMX_VMCS64_GUEST_FS_BASE:
-    case VMX_VMCS64_GUEST_GS_BASE:
-    case VMX_VMCS64_GUEST_SS_BASE:
-        /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
-        if (u64Val >> 32ULL)
-            rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
-        else
-            rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
-
-        return rc;
-
-    default:
-        AssertMsgFailed(("Unexpected field %x\n", idxField));
-        return VERR_INVALID_PARAMETER;
+        case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
+        case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
+        case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
+        case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
+        case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
+        case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
+        case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
+        case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
+        case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
+        case VMX_VMCS_GUEST_LINK_PTR_FULL:
+        case VMX_VMCS_GUEST_PDPTR0_FULL:
+        case VMX_VMCS_GUEST_PDPTR1_FULL:
+        case VMX_VMCS_GUEST_PDPTR2_FULL:
+        case VMX_VMCS_GUEST_PDPTR3_FULL:
+        case VMX_VMCS_GUEST_DEBUGCTL_FULL:
+        case VMX_VMCS_GUEST_EFER_FULL:
+        case VMX_VMCS_CTRL_EPTP_FULL:
+            /* These fields consist of two parts, which are both writable in 32 bits mode. */
+            rc  = VMXWriteVMCS32(idxField, u64Val);
+            rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
+            AssertRC(rc);
+            return rc;
+
+        case VMX_VMCS64_GUEST_LDTR_BASE:
+        case VMX_VMCS64_GUEST_TR_BASE:
+        case VMX_VMCS64_GUEST_GDTR_BASE:
+        case VMX_VMCS64_GUEST_IDTR_BASE:
+        case VMX_VMCS64_GUEST_SYSENTER_EIP:
+        case VMX_VMCS64_GUEST_SYSENTER_ESP:
+        case VMX_VMCS64_GUEST_CR0:
+        case VMX_VMCS64_GUEST_CR4:
+        case VMX_VMCS64_GUEST_CR3:
+        case VMX_VMCS64_GUEST_DR7:
+        case VMX_VMCS64_GUEST_RIP:
+        case VMX_VMCS64_GUEST_RSP:
+        case VMX_VMCS64_GUEST_CS_BASE:
+        case VMX_VMCS64_GUEST_DS_BASE:
+        case VMX_VMCS64_GUEST_ES_BASE:
+        case VMX_VMCS64_GUEST_FS_BASE:
+        case VMX_VMCS64_GUEST_GS_BASE:
+        case VMX_VMCS64_GUEST_SS_BASE:
+            /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
+            if (u64Val >> 32ULL)
+                rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
+            else
+                rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
+
+            return rc;
+
+        default:
+            AssertMsgFailed(("Unexpected field %x\n", idxField));
+            return VERR_INVALID_PARAMETER;
     }
 }
+
 
 /**
  * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
  *
- * @param   pVCpu       The VMCPU to operate on.
- * @param   idxField    VMCS field
- * @param   u64Val      Value
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   idxField    VMCS field index.
+ * @param   u64Val      16, 32 or 64 bits value..
  */
 VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
@@ -5181 +5467 @@
     PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
 
-    AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
+    AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
+                    ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
 
     /* Make sure there are no duplicates. */
-    for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
+    for (unsigned i = 0; i < pCache->Write.cValidEntries; i++)
     {
         if (pCache->Write.aField[i] == idxField)