Index: trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp
===================================================================
--- trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp	(revision 41477)
+++ trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp	(revision 41501)
@@ -108,321 +108,4 @@
 
 /**
- * Checks if the encoding of the current instruction is something
- * we can never get the assembler to produce.
- *
- * @returns true if it's odd, false if it isn't.
- * @param   pCpu        The disassembler output.
- */
-static bool MyDisasYasmFormatterIsOddEncoding(PMYDISSTATE pState)
-{
-    /*
-     * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
-     */
-    if (    pState->Cpu.addrmode != CPUMODE_16BIT ///@todo correct?
-        &&  pState->Cpu.ModRM.Bits.Rm == 4
-        &&  pState->Cpu.ModRM.Bits.Mod != 3)
-    {
-        /* No scaled index SIB (index=4), except for ESP. */
-        if (    pState->Cpu.SIB.Bits.Index == 4
-            &&  pState->Cpu.SIB.Bits.Base != 4)
-            return true;
-
-        /* EBP + displacement */
-        if (    pState->Cpu.ModRM.Bits.Mod != 0
-             && pState->Cpu.SIB.Bits.Base == 5
-             && pState->Cpu.SIB.Bits.Scale == 0)
-            return true;
-    }
-
-    /*
-     * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
-     */
-    if (    pState->Cpu.pCurInstr->opcode == OP_SHL
-        &&  pState->Cpu.ModRM.Bits.Reg == 6)
-        return true;
-
-    /*
-     * Check for multiple prefixes of the same kind.
-     */
-    uint32_t fPrefixes = 0;
-    for (uint8_t const *pu8 = pState->pbInstr;; pu8++)
-    {
-        uint32_t f;
-        switch (*pu8)
-        {
-            case 0xf0:
-                f = PREFIX_LOCK;
-                break;
-
-            case 0xf2:
-            case 0xf3:
-                f = PREFIX_REP; /* yes, both */
-                break;
-
-            case 0x2e:
-            case 0x3e:
-            case 0x26:
-            case 0x36:
-            case 0x64:
-            case 0x65:
-                f = PREFIX_SEG;
-                break;
-
-            case 0x66:
-                f = PREFIX_OPSIZE;
-                break;
-
-            case 0x67:
-                f = PREFIX_ADDRSIZE;
-                break;
-
-            case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
-            case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
-                f = pState->Cpu.mode == CPUMODE_64BIT ? PREFIX_REX : 0;
-                break;
-
-            default:
-                f = 0;
-                break;
-        }
-        if (!f)
-            break; /* done */
-        if (fPrefixes & f)
-            return true;
-        fPrefixes |= f;
-    }
-
-    /* segment overrides are fun */
-    if (fPrefixes & PREFIX_SEG)
-    {
-        /* no effective address which it may apply to. */
-        Assert((pState->Cpu.prefix & PREFIX_SEG) || pState->Cpu.mode == CPUMODE_64BIT);
-        if (    !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param1.flags)
-            &&  !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param2.flags)
-            &&  !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param3.flags))
-            return true;
-    }
-
-    /* fixed register + addr override doesn't go down all that well. */
-    if (fPrefixes & PREFIX_ADDRSIZE)
-    {
-        Assert(pState->Cpu.prefix & PREFIX_ADDRSIZE);
-        if (    pState->Cpu.pCurInstr->param3 == OP_PARM_NONE
-            &&  pState->Cpu.pCurInstr->param2 == OP_PARM_NONE
-            &&  (   pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_GEN32_START
-                 && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_GEN32_END))
-            return true;
-    }
-
-    /* Almost all prefixes are bad. */
-    if (fPrefixes)
-    {
-        switch (pState->Cpu.pCurInstr->opcode)
-        {
-            /* nop w/ prefix(es). */
-            case OP_NOP:
-                return true;
-
-            case OP_JMP:
-                if (    pState->Cpu.pCurInstr->param1 != OP_PARM_Jb
-                    &&  pState->Cpu.pCurInstr->param1 != OP_PARM_Jv)
-                    break;
-                /* fall thru */
-            case OP_JO:
-            case OP_JNO:
-            case OP_JC:
-            case OP_JNC:
-            case OP_JE:
-            case OP_JNE:
-            case OP_JBE:
-            case OP_JNBE:
-            case OP_JS:
-            case OP_JNS:
-            case OP_JP:
-            case OP_JNP:
-            case OP_JL:
-            case OP_JNL:
-            case OP_JLE:
-            case OP_JNLE:
-                /** @todo branch hinting 0x2e/0x3e... */
-                return true;
-        }
-
-    }
-
-    /* All but the segment prefix is bad news. */
-    if (fPrefixes & ~PREFIX_SEG)
-    {
-        switch (pState->Cpu.pCurInstr->opcode)
-        {
-            case OP_POP:
-            case OP_PUSH:
-                if (    pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_SEG_START
-                    &&  pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_SEG_END)
-                    return true;
-                if (    (fPrefixes & ~PREFIX_OPSIZE)
-                    &&  pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_GEN32_START
-                    &&  pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_GEN32_END)
-                    return true;
-                break;
-
-            case OP_POPA:
-            case OP_POPF:
-            case OP_PUSHA:
-            case OP_PUSHF:
-                if (fPrefixes & ~PREFIX_OPSIZE)
-                    return true;
-                break;
-        }
-    }
-
-    /* Implicit 8-bit register instructions doesn't mix with operand size. */
-    if (    (fPrefixes & PREFIX_OPSIZE)
-        &&  (   (   pState->Cpu.pCurInstr->param1 == OP_PARM_Gb /* r8 */
-                 && pState->Cpu.pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
-             || (   pState->Cpu.pCurInstr->param2 == OP_PARM_Gb /* r8 */
-                 && pState->Cpu.pCurInstr->param1 == OP_PARM_Eb /* r8/mem8 */))
-       )
-    {
-        switch (pState->Cpu.pCurInstr->opcode)
-        {
-            case OP_ADD:
-            case OP_OR:
-            case OP_ADC:
-            case OP_SBB:
-            case OP_AND:
-            case OP_SUB:
-            case OP_XOR:
-            case OP_CMP:
-                return true;
-            default:
-                break;
-        }
-    }
-
-
-    /*
-     * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
-     *
-     * For example:
-     *    expected: 1aee   sbb ch, dh     ; SBB r8, r/m8
-     *        yasm: 18F5   sbb ch, dh     ; SBB r/m8, r8
-     */
-    if (pState->Cpu.ModRM.Bits.Mod == 3 /* reg,reg */)
-    {
-        switch (pState->Cpu.pCurInstr->opcode)
-        {
-            case OP_ADD:
-            case OP_OR:
-            case OP_ADC:
-            case OP_SBB:
-            case OP_AND:
-            case OP_SUB:
-            case OP_XOR:
-            case OP_CMP:
-                if (    (    pState->Cpu.pCurInstr->param1 == OP_PARM_Gb /* r8 */
-                         && pState->Cpu.pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
-                    ||  (    pState->Cpu.pCurInstr->param1 == OP_PARM_Gv /* rX */
-                         && pState->Cpu.pCurInstr->param2 == OP_PARM_Ev /* rX/memX */))
-                    return true;
-
-                /* 82 (see table A-6). */
-                if (pState->Cpu.opcode == 0x82)
-                    return true;
-                break;
-
-            /* ff /0, fe /0, ff /1, fe /0 */
-            case OP_DEC:
-            case OP_INC:
-                return true;
-
-            case OP_POP:
-            case OP_PUSH:
-                Assert(pState->Cpu.opcode == 0x8f);
-                return true;
-
-            default:
-                break;
-        }
-    }
-
-    /* shl eax,1 will be assembled to the form without the immediate byte. */
-    if (    pState->Cpu.pCurInstr->param2 == OP_PARM_Ib
-        &&  (uint8_t)pState->Cpu.param2.parval == 1)
-    {
-        switch (pState->Cpu.pCurInstr->opcode)
-        {
-            case OP_SHL:
-            case OP_SHR:
-            case OP_SAR:
-            case OP_RCL:
-            case OP_RCR:
-            case OP_ROL:
-            case OP_ROR:
-                return true;
-        }
-    }
-
-    /* And some more - see table A-6. */
-    if (pState->Cpu.opcode == 0x82)
-    {
-        switch (pState->Cpu.pCurInstr->opcode)
-        {
-            case OP_ADD:
-            case OP_OR:
-            case OP_ADC:
-            case OP_SBB:
-            case OP_AND:
-            case OP_SUB:
-            case OP_XOR:
-            case OP_CMP:
-                return true;
-                break;
-        }
-    }
-
-
-    /* check for REX.X = 1 without SIB. */
-
-    /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
-       says (intel doesn't appear to care). */
-    switch (pState->Cpu.pCurInstr->opcode)
-    {
-        case OP_SETO:
-        case OP_SETNO:
-        case OP_SETC:
-        case OP_SETNC:
-        case OP_SETE:
-        case OP_SETNE:
-        case OP_SETBE:
-        case OP_SETNBE:
-        case OP_SETS:
-        case OP_SETNS:
-        case OP_SETP:
-        case OP_SETNP:
-        case OP_SETL:
-        case OP_SETNL:
-        case OP_SETLE:
-        case OP_SETNLE:
-            AssertMsg(pState->Cpu.opcode >= 0x90 && pState->Cpu.opcode <= 0x9f, ("%#x\n", pState->Cpu.opcode));
-            if (pState->Cpu.ModRM.Bits.Reg != 2)
-                return true;
-            break;
-    }
-
-    /*
-     * The MOVZX reg32,mem16 instruction without an operand size prefix
-     * doesn't quite make sense...
-     */
-    if (    pState->Cpu.pCurInstr->opcode == OP_MOVZX
-        &&  pState->Cpu.opcode == 0xB7
-        &&  (pState->Cpu.mode == CPUMODE_16BIT) != !!(fPrefixes & PREFIX_OPSIZE))
-        return true;
-
-    return false;
-}
-
-
-/**
  * Masm style.
  *
@@ -689,5 +372,5 @@
                 /* Use db for odd encodings that we can't make the assembler use. */
                 if (    State.enmUndefOp == kUndefOp_DefineByte
-                    &&  MyDisasYasmFormatterIsOddEncoding(&State))
+                    &&  DISFormatYasmIsOddEncoding(&State.Cpu))
                 {
                     RTPrintf("    db");
