Changeset 41675 in vbox for trunk/src/VBox/VMM/VMMAll/EMAll.cpp
- Timestamp:
- Jun 12, 2012 8:27:37 PM (12 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r41674 r41675 789 789 case OP_LMSW: return "Lmsw"; 790 790 case OP_SMSW: return "Smsw"; 791 case OP_CMPXCHG: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";792 case OP_CMPXCHG8B: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";791 case OP_CMPXCHG: return pDis->prefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg"; 792 case OP_CMPXCHG8B: return pDis->prefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b"; 793 793 794 794 default: … … 1009 1009 static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1010 1010 { 1011 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */1011 Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ 1012 1012 OP_PARAMVAL param1; 1013 1013 NOREF(pvFault); … … 1028 1028 1029 1029 /* Read stack value first */ 1030 if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)1030 if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == DISCPUMODE_16BIT) 1031 1031 return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */ 1032 1032 … … 1561 1561 } 1562 1562 #ifdef LOG_ENABLED 1563 if (pDis->mode == CPUMODE_64BIT)1563 if (pDis->mode == DISCPUMODE_64BIT) 1564 1564 LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64)); 1565 1565 else … … 1624 1624 } 1625 1625 #ifdef LOG_ENABLED 1626 if (pDis->mode == CPUMODE_64BIT)1626 if (pDis->mode == DISCPUMODE_64BIT) 1627 1627 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size)); 1628 1628 else … … 1652 1652 1653 1653 /* Don't support any but these three prefix bytes. */ 1654 if ((pDis->prefix & ~( PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))1654 if ((pDis->prefix & ~(DISPREFIX_ADDRSIZE|DISPREFIX_OPSIZE|DISPREFIX_REP|DISPREFIX_REX))) 1655 1655 return VERR_EM_INTERPRETER; 1656 1656 1657 1657 switch (pDis->addrmode) 1658 1658 { 1659 case CPUMODE_16BIT:1659 case DISCPUMODE_16BIT: 1660 1660 GCOffset = pRegFrame->di; 1661 1661 cTransfers = pRegFrame->cx; 1662 1662 break; 1663 case CPUMODE_32BIT:1663 case DISCPUMODE_32BIT: 1664 1664 GCOffset = pRegFrame->edi; 1665 1665 cTransfers = pRegFrame->ecx; 1666 1666 break; 1667 case CPUMODE_64BIT:1667 case DISCPUMODE_64BIT: 1668 1668 GCOffset = pRegFrame->rdi; 1669 1669 cTransfers = pRegFrame->rcx; … … 1677 1677 switch (pDis->opmode) 1678 1678 { 1679 case CPUMODE_16BIT:1679 case DISCPUMODE_16BIT: 1680 1680 cbSize = 2; 1681 1681 break; 1682 case CPUMODE_32BIT:1682 case DISCPUMODE_32BIT: 1683 1683 cbSize = 4; 1684 1684 break; 1685 case CPUMODE_64BIT:1685 case DISCPUMODE_64BIT: 1686 1686 cbSize = 8; 1687 1687 break; … … 1693 1693 offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize; 1694 1694 1695 if (!(pDis->prefix & PREFIX_REP))1695 if (!(pDis->prefix & DISPREFIX_REP)) 1696 1696 { 1697 1697 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize)); … … 1705 1705 switch (pDis->addrmode) 1706 1706 { 1707 case CPUMODE_16BIT:1707 case DISCPUMODE_16BIT: 1708 1708 pRegFrame->di += offIncrement; 1709 1709 break; 1710 case CPUMODE_32BIT:1710 case DISCPUMODE_32BIT: 1711 1711 pRegFrame->edi += offIncrement; 1712 1712 break; 1713 case CPUMODE_64BIT:1713 case DISCPUMODE_64BIT: 1714 1714 pRegFrame->rdi += offIncrement; 1715 1715 break; … … 1770 1770 switch (pDis->addrmode) 1771 1771 { 1772 case CPUMODE_16BIT:1772 case DISCPUMODE_16BIT: 1773 1773 pRegFrame->di = GCOffset; 1774 1774 pRegFrame->cx = cTransfers; 1775 1775 break; 1776 case CPUMODE_32BIT:1776 case DISCPUMODE_32BIT: 1777 1777 pRegFrame->edi = GCOffset; 1778 1778 pRegFrame->ecx = cTransfers; 1779 1779 break; 1780 case CPUMODE_64BIT:1780 case DISCPUMODE_64BIT: 1781 1781 pRegFrame->rdi = GCOffset; 1782 1782 pRegFrame->rcx = cTransfers; … … 1848 1848 LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar)); 1849 1849 1850 if (pDis->prefix & PREFIX_LOCK)1850 if (pDis->prefix & DISPREFIX_LOCK) 1851 1851 eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.cb); 1852 1852 else … … 1870 1870 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1871 1871 { 1872 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */1872 Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ 1873 1873 OP_PARAMVAL param1; 1874 1874 NOREF(pvFault); … … 1901 1901 LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax)); 1902 1902 1903 if (pDis->prefix & PREFIX_LOCK)1903 if (pDis->prefix & DISPREFIX_LOCK) 1904 1904 eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx); 1905 1905 else … … 1924 1924 static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1925 1925 { 1926 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */1926 Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ 1927 1927 OP_PARAMVAL param1; 1928 1928 void *pvParamReg2; … … 1970 1970 LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, *(uint64_t *)pvParamReg2)); 1971 1971 1972 if (pDis->prefix & PREFIX_LOCK)1972 if (pDis->prefix & DISPREFIX_LOCK) 1973 1973 eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2); 1974 1974 else … … 2654 2654 AssertRCReturn(rc, VERR_EM_INTERPRETER); 2655 2655 2656 if (!(pDis->prefix & PREFIX_OPSIZE))2656 if (!(pDis->prefix & DISPREFIX_OPSIZE)) 2657 2657 dtr32.uAddr &= 0xffffff; /* 16 bits operand size */ 2658 2658 … … 3030 3030 /* Note: The Intel manual claims there's a REX version of RDMSR that's slightly 3031 3031 different, so we play safe by completely disassembling the instruction. */ 3032 Assert(!(pDis->prefix & PREFIX_REX));3032 Assert(!(pDis->prefix & DISPREFIX_REX)); 3033 3033 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize); 3034 3034 return EMInterpretRdmsr(pVM, pVCpu, pRegFrame); … … 3104 3104 3105 3105 #ifdef IN_RC 3106 if ( (pDis->prefix & ( PREFIX_REPNE |PREFIX_REP))3107 || ( (pDis->prefix & PREFIX_LOCK)3106 if ( (pDis->prefix & (DISPREFIX_REPNE | DISPREFIX_REP)) 3107 || ( (pDis->prefix & DISPREFIX_LOCK) 3108 3108 && pDis->pCurInstr->opcode != OP_CMPXCHG 3109 3109 && pDis->pCurInstr->opcode != OP_CMPXCHG8B … … 3116 3116 ) 3117 3117 #else 3118 if ( (pDis->prefix & PREFIX_REPNE)3119 || ( (pDis->prefix & PREFIX_REP)3118 if ( (pDis->prefix & DISPREFIX_REPNE) 3119 || ( (pDis->prefix & DISPREFIX_REP) 3120 3120 && pDis->pCurInstr->opcode != OP_STOSWD 3121 3121 ) 3122 || ( (pDis->prefix & PREFIX_LOCK)3122 || ( (pDis->prefix & DISPREFIX_LOCK) 3123 3123 && pDis->pCurInstr->opcode != OP_OR 3124 3124 && pDis->pCurInstr->opcode != OP_AND … … 3228 3228 # define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \ 3229 3229 case opcode:\ 3230 if (pDis->prefix & PREFIX_LOCK) \3230 if (pDis->prefix & DISPREFIX_LOCK) \ 3231 3231 rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \ 3232 3232 else \
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