Changeset 41732 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Jun 14, 2012 11:57:45 PM (13 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 16 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r41731 r41732 507 507 if (RT_SUCCESS(rc)) 508 508 { 509 Assert(cbOp == pDis-> opsize);509 Assert(cbOp == pDis->cbInstr); 510 510 uint32_t cbIgnored; 511 511 rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored); … … 561 561 if (RT_SUCCESS(rc)) 562 562 { 563 Assert(cbOp == pDis-> opsize);563 Assert(cbOp == pDis->cbInstr); 564 564 rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten); 565 565 if (RT_SUCCESS(rc)) … … 617 617 VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored); 618 618 if (RT_SUCCESS(rc)) 619 pRegFrame->rip += pDis-> opsize; /* Move on to the next instruction. */619 pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */ 620 620 return rc; 621 621 #endif … … 2688 2688 Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip)); 2689 2689 2690 pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis-> opsize;2690 pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr; 2691 2691 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); 2692 2692 -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r41727 r41732 936 936 pRegFrame->rcx--; 937 937 } 938 pRegFrame->rip += pDis-> opsize;938 pRegFrame->rip += pDis->cbInstr; 939 939 940 940 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n")); -
trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
r40449 r41732 352 352 * @param pRegFrame Pointer to the register frame for the trap. 353 353 * @param iGate Trap or interrupt gate number 354 * @param opsizeInstruction size (only relevant for software interrupts)354 * @param cbInstr Instruction size (only relevant for software interrupts) 355 355 * @param enmError TRPM_TRAP_HAS_ERRORCODE or TRPM_TRAP_NO_ERRORCODE. 356 356 * @param enmType TRPM event type … … 358 358 * @internal 359 359 */ 360 VMMDECL(int) TRPMForwardTrap(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t iGate, uint32_t opsize,360 VMMDECL(int) TRPMForwardTrap(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t iGate, uint32_t cbInstr, 361 361 TRPMERRORCODE enmError, TRPMEVENT enmType, int32_t iOrgTrap) 362 362 { … … 639 639 if (enmType == TRPM_SOFTWARE_INT) 640 640 { 641 Assert( opsize);642 pTrapStack[--idx] = pRegFrame->eip + opsize; /* return address = next instruction */641 Assert(cbInstr); 642 pTrapStack[--idx] = pRegFrame->eip + cbInstr; /* return address = next instruction */ 643 643 } 644 644 else -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r41729 r41732 2987 2987 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG) 2988 2988 { 2989 Assert(cbOp == pDis-> opsize);2989 Assert(cbOp == pDis->cbInstr); 2990 2990 rc = hmR0svmInterpretInvlPg(pVCpu, pDis, pRegFrame, uASID); 2991 2991 if (RT_SUCCESS(rc)) -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r41728 r41732 3553 3553 3554 3554 rc = VINF_SUCCESS; 3555 Assert(cbOp == pDis-> opsize);3555 Assert(cbOp == pDis->cbInstr); 3556 3556 switch (pDis->pCurInstr->opcode) 3557 3557 { … … 3563 3563 case OP_STI: 3564 3564 pCtx->eflags.Bits.u1IF = 1; 3565 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis-> opsize);3565 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->cbInstr); 3566 3566 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)); 3567 3567 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, … … 3574 3574 fUpdateRIP = false; 3575 3575 rc = VINF_EM_HALT; 3576 pCtx->rip += pDis-> opsize;3576 pCtx->rip += pDis->cbInstr; 3577 3577 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt); 3578 3578 break; -
trunk/src/VBox/VMM/VMMR3/CSAM.cpp
r41731 r41732 835 835 case OP_CLI: 836 836 { 837 uint32_t cbInstr = 0;838 uint32_t opsize = pCpu->opsize;839 bool fCode32 = pPage->fCode32;837 uint32_t cbInstrs = 0; 838 uint32_t cbCurInstr = pCpu->cbInstr; 839 bool fCode32 = pPage->fCode32; 840 840 841 841 Assert(fCode32); … … 848 848 DISCPUSTATE cpu; 849 849 850 if (cbInstr + opsize>= SIZEOF_NEARJUMP32)850 if (cbInstrs + cbCurInstr >= SIZEOF_NEARJUMP32) 851 851 break; 852 852 853 if (csamIsCodeScanned(pVM, pCurInstrGC + opsize, &pPage) == true)853 if (csamIsCodeScanned(pVM, pCurInstrGC + cbCurInstr, &pPage) == true) 854 854 { 855 855 /* We've scanned the next instruction(s) already. This means we've followed a branch that ended up there before -> dangerous!! */ 856 PATMR3DetectConflict(pVM, pCurInstrGC, pCurInstrGC + opsize);856 PATMR3DetectConflict(pVM, pCurInstrGC, pCurInstrGC + cbCurInstr); 857 857 break; 858 858 } 859 pCurInstrGC += opsize;860 cbInstr += opsize;859 pCurInstrGC += cbCurInstr; 860 cbInstrs += cbCurInstr; 861 861 862 862 { /* Force pCurInstrHC out of scope after we stop using it (page lock!) */ … … 871 871 872 872 rc = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 873 &cpu, & opsize, NULL, 0);873 &cpu, &cbCurInstr, NULL, 0); 874 874 } 875 875 AssertRC(rc); … … 1018 1018 { 1019 1019 DISCPUSTATE cpu; 1020 uint32_t opsize;1020 uint32_t cbInstr; 1021 1021 int rc2; 1022 1022 #ifdef DEBUG … … 1054 1054 #ifdef DEBUG 1055 1055 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1056 &cpu, & opsize, szOutput, sizeof(szOutput));1056 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 1057 1057 if (RT_SUCCESS(rc2)) Log(("CSAM Call Analysis: %s", szOutput)); 1058 1058 #else 1059 1059 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1060 &cpu, & opsize, NULL, 0);1060 &cpu, &cbInstr, NULL, 0); 1061 1061 #endif 1062 1062 STAM_PROFILE_STOP(&pVM->csam.s.StatTimeDisasm, a); … … 1067 1067 } 1068 1068 1069 STAM_COUNTER_ADD(&pVM->csam.s.StatNrBytesRead, opsize);1069 STAM_COUNTER_ADD(&pVM->csam.s.StatNrBytesRead, cbInstr); 1070 1070 1071 1071 RCPTRTYPE(uint8_t *) addr = 0; 1072 1072 PCSAMPAGE pJmpPage = NULL; 1073 1073 1074 if (PAGE_ADDRESS(pCurInstrGC) != PAGE_ADDRESS(pCurInstrGC + opsize- 1))1074 if (PAGE_ADDRESS(pCurInstrGC) != PAGE_ADDRESS(pCurInstrGC + cbInstr - 1)) 1075 1075 { 1076 if (!PGMGstIsPagePresent(pVM, pCurInstrGC + opsize- 1))1076 if (!PGMGstIsPagePresent(pVM, pCurInstrGC + cbInstr - 1)) 1077 1077 { 1078 1078 /// @todo fault in the page … … 1081 1081 } 1082 1082 //all is fine, let's continue 1083 csamR3CheckPageRecord(pVM, pCurInstrGC + opsize- 1);1083 csamR3CheckPageRecord(pVM, pCurInstrGC + cbInstr - 1); 1084 1084 } 1085 1085 … … 1169 1169 } 1170 1170 /* Mark it as scanned. */ 1171 csamMarkCode(pVM, pPage, pCurInstrGC, opsize, true);1172 pCurInstrGC += opsize;1171 csamMarkCode(pVM, pPage, pCurInstrGC, cbInstr, true); 1172 pCurInstrGC += cbInstr; 1173 1173 } /* for at most 16 instructions */ 1174 1174 next_function: … … 1202 1202 PCSAMPAGE pPage = (PCSAMPAGE)pUserData; 1203 1203 int rc = VWRN_CONTINUE_ANALYSIS; 1204 uint32_t opsize;1204 uint32_t cbInstr; 1205 1205 int rc2; 1206 1206 Assert(pVM->cCpus == 1); … … 1267 1267 #ifdef DEBUG 1268 1268 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1269 &cpu, & opsize, szOutput, sizeof(szOutput));1269 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 1270 1270 if (RT_SUCCESS(rc2)) Log(("CSAM Analysis: %s", szOutput)); 1271 1271 #else 1272 1272 rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, 1273 &cpu, & opsize, NULL, 0);1273 &cpu, &cbInstr, NULL, 0); 1274 1274 #endif 1275 1275 STAM_PROFILE_STOP(&pVM->csam.s.StatTimeDisasm, a); … … 1282 1282 } 1283 1283 1284 STAM_COUNTER_ADD(&pVM->csam.s.StatNrBytesRead, opsize);1285 1286 csamMarkCode(pVM, pPage, pCurInstrGC, opsize, true);1284 STAM_COUNTER_ADD(&pVM->csam.s.StatNrBytesRead, cbInstr); 1285 1286 csamMarkCode(pVM, pPage, pCurInstrGC, cbInstr, true); 1287 1287 1288 1288 RCPTRTYPE(uint8_t *) addr = 0; 1289 1289 PCSAMPAGE pJmpPage = NULL; 1290 1290 1291 if (PAGE_ADDRESS(pCurInstrGC) != PAGE_ADDRESS(pCurInstrGC + opsize- 1))1292 { 1293 if (!PGMGstIsPagePresent(pVCpu, pCurInstrGC + opsize- 1))1291 if (PAGE_ADDRESS(pCurInstrGC) != PAGE_ADDRESS(pCurInstrGC + cbInstr - 1)) 1292 { 1293 if (!PGMGstIsPagePresent(pVCpu, pCurInstrGC + cbInstr - 1)) 1294 1294 { 1295 1295 /// @todo fault in the page … … 1299 1299 } 1300 1300 //all is fine, let's continue 1301 csamR3CheckPageRecord(pVM, pCurInstrGC + opsize- 1);1301 csamR3CheckPageRecord(pVM, pCurInstrGC + cbInstr - 1); 1302 1302 } 1303 1303 /* … … 1317 1317 && pCacheRec->pCallExitRec->cInstrAfterRet < CSAM_MAX_CALLEXIT_RET) 1318 1318 { 1319 pCacheRec->pCallExitRec->pInstrAfterRetGC[pCacheRec->pCallExitRec->cInstrAfterRet] = pCurInstrGC + opsize;1319 pCacheRec->pCallExitRec->pInstrAfterRetGC[pCacheRec->pCallExitRec->cInstrAfterRet] = pCurInstrGC + cbInstr; 1320 1320 pCacheRec->pCallExitRec->cInstrAfterRet++; 1321 1321 } … … 1463 1463 goto done; 1464 1464 } 1465 pCurInstrGC += opsize;1465 pCurInstrGC += cbInstr; 1466 1466 } 1467 1467 done: … … 2181 2181 * @param pPage Patch structure pointer 2182 2182 * @param pInstr Instruction pointer 2183 * @param opsizeInstruction size2183 * @param cbInstr Instruction size 2184 2184 * @param fScanned Mark as scanned or not 2185 2185 */ 2186 static void csamMarkCode(PVM pVM, PCSAMPAGE pPage, RTRCPTR pInstr, uint32_t opsize, bool fScanned)2187 { 2188 LogFlow(("csamMarkCodeAsScanned %RRv opsize=%d\n", pInstr, opsize));2186 static void csamMarkCode(PVM pVM, PCSAMPAGE pPage, RTRCPTR pInstr, uint32_t cbInstr, bool fScanned) 2187 { 2188 LogFlow(("csamMarkCodeAsScanned %RRv cbInstr=%d\n", pInstr, cbInstr)); 2189 2189 CSAMMarkPage(pVM, pInstr, fScanned); 2190 2190 … … 2198 2198 if (ASMBitTest(pPage->pBitmap, pInstr & PAGE_OFFSET_MASK) == 0) 2199 2199 { 2200 pPage->uSize += opsize;2200 pPage->uSize += cbInstr; 2201 2201 STAM_COUNTER_ADD(&pVM->csam.s.StatNrInstr, 1); 2202 2202 } … … 2220 2220 * @param pVM The VM to operate on. 2221 2221 * @param pInstr Instruction pointer 2222 * @param opsizeInstruction size2222 * @param cbInstr Instruction size 2223 2223 * @param fScanned Mark as scanned or not 2224 2224 */ 2225 VMMR3DECL(int) CSAMR3MarkCode(PVM pVM, RTRCPTR pInstr, uint32_t opsize, bool fScanned)2225 VMMR3DECL(int) CSAMR3MarkCode(PVM pVM, RTRCPTR pInstr, uint32_t cbInstr, bool fScanned) 2226 2226 { 2227 2227 PCSAMPAGE pPage = 0; … … 2236 2236 } 2237 2237 2238 Log(("CSAMR3MarkCode: %RRv size=%d fScanned=%d\n", pInstr, opsize, fScanned));2239 csamMarkCode(pVM, pPage, pInstr, opsize, fScanned);2238 Log(("CSAMR3MarkCode: %RRv size=%d fScanned=%d\n", pInstr, cbInstr, fScanned)); 2239 csamMarkCode(pVM, pPage, pInstr, cbInstr, fScanned); 2240 2240 return VINF_SUCCESS; 2241 2241 } -
trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp
r41727 r41732 500 500 else 501 501 { 502 uint32_t cbBits = State.Cpu. opsize;502 uint32_t cbBits = State.Cpu.cbInstr; 503 503 uint8_t *pau8Bits = (uint8_t *)alloca(cbBits); 504 504 rc = dbgfR3DisasInstrRead(&State.Cpu, pau8Bits, GCPtr, cbBits); … … 542 542 543 543 if (pcbInstr) 544 *pcbInstr = State.Cpu. opsize;544 *pcbInstr = State.Cpu.cbInstr; 545 545 546 546 dbgfR3DisasInstrDone(&State); -
trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp
r41727 r41732 354 354 if (IOM_SUCCESS(rcStrict)) 355 355 { 356 pCtx->rip += Cpu. opsize;356 pCtx->rip += Cpu.cbInstr; 357 357 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 358 358 return VBOXSTRICTRC_TODO(rcStrict); -
trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
r41728 r41732 475 475 if (IOM_SUCCESS(rcStrict)) 476 476 { 477 pCtx->rip += Cpu. opsize;477 pCtx->rip += Cpu.cbInstr; 478 478 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a); 479 479 return VBOXSTRICTRC_TODO(rcStrict); … … 1048 1048 case OP_CLI: 1049 1049 pCtx->eflags.u32 &= ~X86_EFL_IF; 1050 Assert(Cpu. opsize== 1);1051 pCtx->rip += Cpu. opsize;1050 Assert(Cpu.cbInstr == 1); 1051 pCtx->rip += Cpu.cbInstr; 1052 1052 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a); 1053 1053 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */ … … 1055 1055 case OP_STI: 1056 1056 pCtx->eflags.u32 |= X86_EFL_IF; 1057 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu. opsize);1058 Assert(Cpu. opsize== 1);1059 pCtx->rip += Cpu. opsize;1057 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr); 1058 Assert(Cpu.cbInstr == 1); 1059 pCtx->rip += Cpu.cbInstr; 1060 1060 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a); 1061 1061 return VINF_SUCCESS; -
trunk/src/VBox/VMM/VMMR3/PATM.cpp
r41731 r41732 1414 1414 { 1415 1415 if ( pCurInstrGC > pPatch->pPrivInstrGC 1416 && pCurInstrGC + pCpu-> opsize< pPatch->pPrivInstrGC + SIZEOF_NEARJUMP32) /* hardcoded patch jump size; cbPatchJump is still zero */1416 && pCurInstrGC + pCpu->cbInstr < pPatch->pPrivInstrGC + SIZEOF_NEARJUMP32) /* hardcoded patch jump size; cbPatchJump is still zero */ 1417 1417 { 1418 1418 Log(("Dangerous unconditional jump ends in our generated patch jump!! (%x vs %x)\n", pCurInstrGC, pPatch->pPrivInstrGC)); … … 1449 1449 } 1450 1450 1451 pPatch->cbPatchBlockSize += pCpu-> opsize;1451 pPatch->cbPatchBlockSize += pCpu->cbInstr; 1452 1452 1453 1453 /* Illegal instruction -> end of analysis phase for this code block */ … … 1514 1514 { 1515 1515 /* The end marker for this kind of patch is any instruction at a location outside our patch jump. */ 1516 Log(("End of block at %RRv size %d\n", pCurInstrGC, pCpu-> opsize));1516 Log(("End of block at %RRv size %d\n", pCurInstrGC, pCpu->cbInstr)); 1517 1517 return VINF_SUCCESS; 1518 1518 } … … 1591 1591 } 1592 1592 1593 pPatch->cbPatchBlockSize += pCpu-> opsize;1593 pPatch->cbPatchBlockSize += pCpu->cbInstr; 1594 1594 1595 1595 /* Illegal instruction -> end of analysis phase for this code block */ … … 1681 1681 else 1682 1682 if (pCurInstrGC > pPatch->pInstrGCHighest) 1683 pPatch->pInstrGCHighest = pCurInstrGC + pCpu-> opsize;1683 pPatch->pInstrGCHighest = pCurInstrGC + pCpu->cbInstr; 1684 1684 1685 1685 /* Illegal instruction -> end of recompile phase for this code block. */ … … 1790 1790 pPatch->flags |= PATMFL_INHIBIT_IRQS | PATMFL_GENERATE_JUMPTOGUEST; 1791 1791 fInhibitIRQInstr = true; 1792 pNextInstrGC = pCurInstrGC + pCpu-> opsize;1792 pNextInstrGC = pCurInstrGC + pCpu->cbInstr; 1793 1793 Log(("Inhibit irqs for instruction OP_STI at %RRv\n", pCurInstrGC)); 1794 1794 } … … 1798 1798 { 1799 1799 DISCPUSTATE cpu = *pCpu; 1800 unsigned opsize;1800 unsigned cbInstr; 1801 1801 int disret; 1802 1802 RCPTRTYPE(uint8_t *) pReturnInstrGC; … … 1804 1804 pPatch->flags |= PATMFL_FOUND_PATCHEND; 1805 1805 1806 pNextInstrGC = pCurInstrGC + pCpu-> opsize;1806 pNextInstrGC = pCurInstrGC + pCpu->cbInstr; 1807 1807 { /* Force pNextInstrHC out of scope after using it */ 1808 1808 uint8_t *pNextInstrHC = PATMGCVirtToHCVirt(pVM, pCacheRec, pNextInstrGC); … … 1814 1814 1815 1815 // Disassemble the next instruction 1816 disret = patmR3DisInstr(pVM, pPatch, pNextInstrGC, pNextInstrHC, PATMREAD_ORGCODE, &cpu, & opsize);1816 disret = patmR3DisInstr(pVM, pPatch, pNextInstrGC, pNextInstrHC, PATMREAD_ORGCODE, &cpu, &cbInstr); 1817 1817 } 1818 1818 if (disret == false) … … 1821 1821 return VERR_PATCHING_REFUSED; 1822 1822 } 1823 pReturnInstrGC = pNextInstrGC + opsize;1823 pReturnInstrGC = pNextInstrGC + cbInstr; 1824 1824 1825 1825 if ( (pPatch->flags & (PATMFL_DUPLICATE_FUNCTION)) … … 1848 1848 case OP_POPF: 1849 1849 { 1850 bool fGenerateJmpBack = (pCurInstrGC + pCpu-> opsize- pInstrGC >= SIZEOF_NEARJUMP32);1850 bool fGenerateJmpBack = (pCurInstrGC + pCpu->cbInstr - pInstrGC >= SIZEOF_NEARJUMP32); 1851 1851 1852 1852 /* Not an exit point for IDT handler or function replacement patches */ … … 1855 1855 fGenerateJmpBack = false; 1856 1856 1857 rc = patmPatchGenPopf(pVM, pPatch, pCurInstrGC + pCpu-> opsize, !!(pCpu->prefix & DISPREFIX_OPSIZE), fGenerateJmpBack);1857 rc = patmPatchGenPopf(pVM, pPatch, pCurInstrGC + pCpu->cbInstr, !!(pCpu->prefix & DISPREFIX_OPSIZE), fGenerateJmpBack); 1858 1858 if (RT_SUCCESS(rc)) 1859 1859 { … … 2024 2024 { 2025 2025 int rc2; 2026 RTRCPTR pNextInstrGC = pCurInstrGC + pCpu-> opsize;2026 RTRCPTR pNextInstrGC = pCurInstrGC + pCpu->cbInstr; 2027 2027 2028 2028 pPatch->flags &= ~PATMFL_INHIBIT_IRQS; … … 2048 2048 // If single instruction patch, we've copied enough instructions *and* the current instruction is not a relative jump 2049 2049 if ( (pPatch->flags & PATMFL_CHECK_SIZE) 2050 && pCurInstrGC + pCpu-> opsize- pInstrGC >= SIZEOF_NEARJUMP322050 && pCurInstrGC + pCpu->cbInstr - pInstrGC >= SIZEOF_NEARJUMP32 2051 2051 && !(pCpu->pCurInstr->optype & DISOPTYPE_RELATIVE_CONTROLFLOW) 2052 2052 && !(pPatch->flags & PATMFL_RECOMPILE_NEXT) /* do not do this when the next instruction *must* be executed! */ 2053 2053 ) 2054 2054 { 2055 RTRCPTR pNextInstrGC = pCurInstrGC + pCpu-> opsize;2055 RTRCPTR pNextInstrGC = pCurInstrGC + pCpu->cbInstr; 2056 2056 2057 2057 // The end marker for this kind of patch is any instruction at a location outside our patch jump 2058 Log(("patmRecompileCallback: end found for single instruction patch at %RRv opsize %d\n", pNextInstrGC, pCpu->opsize));2058 Log(("patmRecompileCallback: end found for single instruction patch at %RRv cbInstr %d\n", pNextInstrGC, pCpu->cbInstr)); 2059 2059 2060 2060 rc = patmPatchGenJumpToGuest(pVM, pPatch, pNextInstrGC); … … 2179 2179 PPATCHINFO pPatch = (PPATCHINFO)pCacheRec->pPatch; 2180 2180 int rc = VWRN_CONTINUE_ANALYSIS; 2181 uint32_t opsize, delta;2181 uint32_t cbInstr, delta; 2182 2182 R3PTRTYPE(uint8_t *) pCurInstrHC = 0; 2183 2183 bool disret; … … 2199 2199 2200 2200 disret = patmR3DisInstrToStr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_RAWCODE, 2201 &cpu, & opsize, szOutput, sizeof(szOutput));2201 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 2202 2202 if (PATMIsPatchGCAddr(pVM, pCurInstrGC)) 2203 2203 { … … 2283 2283 rc = VWRN_CONTINUE_ANALYSIS; 2284 2284 } 2285 pCurInstrGC += opsize;2285 pCurInstrGC += cbInstr; 2286 2286 } 2287 2287 end: … … 2349 2349 PPATCHINFO pPatch = (PPATCHINFO)pCacheRec->pPatch; 2350 2350 int rc = VWRN_CONTINUE_ANALYSIS; 2351 uint32_t opsize;2351 uint32_t cbInstr; 2352 2352 R3PTRTYPE(uint8_t *) pCurInstrHC = 0; 2353 2353 bool disret; … … 2366 2366 #ifdef LOG_ENABLED 2367 2367 disret = patmR3DisInstrToStr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, 2368 &cpu, & opsize, szOutput, sizeof(szOutput));2368 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 2369 2369 Log(("Recompile: %s", szOutput)); 2370 2370 #else 2371 disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpu, & opsize);2371 disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpu, &cbInstr); 2372 2372 #endif 2373 2373 if (disret == false) … … 2392 2392 uint32_t opsizenext; 2393 2393 uint8_t *pNextInstrHC; 2394 RTRCPTR pNextInstrGC = pCurInstrGC + opsize;2394 RTRCPTR pNextInstrGC = pCurInstrGC + cbInstr; 2395 2395 2396 2396 Log(("patmRecompileCodeStream: irqs inhibited by instruction %RRv\n", pNextInstrGC)); … … 2473 2473 Log(("patmRecompileCodeStream continue passed conditional jump\n")); 2474 2474 /* First we need to finish this linear code stream until the next exit point. */ 2475 rc = patmRecompileCodeStream(pVM, pInstrGC, pCurInstrGC+ opsize, pfnPATMR3Recompile, pCacheRec);2475 rc = patmRecompileCodeStream(pVM, pInstrGC, pCurInstrGC+cbInstr, pfnPATMR3Recompile, pCacheRec); 2476 2476 if (RT_FAILURE(rc)) 2477 2477 { … … 2522 2522 goto end; 2523 2523 } 2524 pCurInstrGC += opsize;2524 pCurInstrGC += cbInstr; 2525 2525 } 2526 2526 end: … … 2631 2631 DISCPUSTATE cpu; 2632 2632 char szOutput[256]; 2633 uint32_t opsize, i = 0;2633 uint32_t cbInstr, i = 0; 2634 2634 bool disret; 2635 2635 … … 2637 2637 { 2638 2638 disret = patmR3DisInstrToStr(pVM, pPatch, pPatch->pPrivInstrGC + i, NULL, PATMREAD_ORGCODE, 2639 &cpu, & opsize, szOutput, sizeof(szOutput));2639 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 2640 2640 if (disret == false) 2641 2641 break; 2642 2642 2643 2643 Log(("Org patch jump: %s", szOutput)); 2644 Assert( opsize);2645 i += opsize;2644 Assert(cbInstr); 2645 i += cbInstr; 2646 2646 } 2647 2647 #endif … … 2656 2656 { 2657 2657 disret = patmR3DisInstrToStr(pVM, pPatch, pPatch->pPrivInstrGC + i, NULL, PATMREAD_ORGCODE, 2658 &cpu, & opsize, szOutput, sizeof(szOutput));2658 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 2659 2659 if (disret == false) 2660 2660 break; 2661 2661 2662 2662 Log(("Org instr: %s", szOutput)); 2663 Assert( opsize);2664 i += opsize;2663 Assert(cbInstr); 2664 i += cbInstr; 2665 2665 } 2666 2666 } … … 2963 2963 bool disret; 2964 2964 DISCPUSTATE cpuPush, cpuJmp; 2965 uint32_t opsize;2965 uint32_t cbInstr; 2966 2966 RTRCPTR pCurInstrGC = pInstrGC; 2967 2967 uint8_t *pCurInstrHC, *pInstrHC; … … 2976 2976 * condition here and only patch the common entypoint once. 2977 2977 */ 2978 disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpuPush, & opsize);2978 disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpuPush, &cbInstr); 2979 2979 Assert(disret); 2980 2980 if (disret && cpuPush.pCurInstr->opcode == OP_PUSH) … … 2982 2982 RTRCPTR pJmpInstrGC; 2983 2983 int rc; 2984 pCurInstrGC += opsize;2985 2986 disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpuJmp, & opsize);2984 pCurInstrGC += cbInstr; 2985 2986 disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpuJmp, &cbInstr); 2987 2987 if ( disret 2988 2988 && cpuJmp.pCurInstr->opcode == OP_JMP … … 3569 3569 RTRCPTR pTargetGC; 3570 3570 PPATMPATCHREC pPatchFunction; 3571 uint32_t opsize;3571 uint32_t cbInstr; 3572 3572 bool disret; 3573 3573 3574 3574 Assert(pPatch->flags & PATMFL_REPLACE_FUNCTION_CALL); 3575 Assert((pCpu->pCurInstr->opcode == OP_CALL || pCpu->pCurInstr->opcode == OP_JMP) && pCpu-> opsize== SIZEOF_NEARJUMP32);3576 3577 if ((pCpu->pCurInstr->opcode != OP_CALL && pCpu->pCurInstr->opcode != OP_JMP) || pCpu-> opsize!= SIZEOF_NEARJUMP32)3575 Assert((pCpu->pCurInstr->opcode == OP_CALL || pCpu->pCurInstr->opcode == OP_JMP) && pCpu->cbInstr == SIZEOF_NEARJUMP32); 3576 3577 if ((pCpu->pCurInstr->opcode != OP_CALL && pCpu->pCurInstr->opcode != OP_JMP) || pCpu->cbInstr != SIZEOF_NEARJUMP32) 3578 3578 { 3579 3579 rc = VERR_PATCHING_REFUSED; … … 3604 3604 break; 3605 3605 3606 disret = patmR3DisInstr(pVM, pPatch, pTargetGC, pTmpInstrHC, PATMREAD_ORGCODE, &cpu, & opsize);3606 disret = patmR3DisInstr(pVM, pPatch, pTargetGC, pTmpInstrHC, PATMREAD_ORGCODE, &cpu, &cbInstr); 3607 3607 if (disret == false || cpu.pCurInstr->opcode != OP_JMP) 3608 3608 break; … … 3639 3639 /* Lowest and highest address for write monitoring. */ 3640 3640 pPatch->pInstrGCLowest = pInstrGC; 3641 pPatch->pInstrGCHighest = pInstrGC + pCpu-> opsize;3641 pPatch->pInstrGCHighest = pInstrGC + pCpu->cbInstr; 3642 3642 PATM_LOG_ORG_PATCH_INSTR(pVM, pPatch, "Call"); 3643 3643 … … 3684 3684 3685 3685 /* Add relocation record for cached data access. */ 3686 if (patmPatchAddReloc32(pVM, pPatch, &pPB[pCpu-> opsize- sizeof(RTRCPTR)], FIXUP_ABSOLUTE, pPatch->pPrivInstrGC, pVM->patm.s.mmio.pCachedData) != VINF_SUCCESS)3686 if (patmPatchAddReloc32(pVM, pPatch, &pPB[pCpu->cbInstr - sizeof(RTRCPTR)], FIXUP_ABSOLUTE, pPatch->pPrivInstrGC, pVM->patm.s.mmio.pCachedData) != VINF_SUCCESS) 3687 3687 { 3688 3688 Log(("Relocation failed for cached mmio address!!\n")); … … 3698 3698 3699 3699 /* Replace address with that of the cached item. */ 3700 rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pInstrGC + pCpu-> opsize- sizeof(RTRCPTR), &pVM->patm.s.mmio.pCachedData, sizeof(RTRCPTR));3700 rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pInstrGC + pCpu->cbInstr - sizeof(RTRCPTR), &pVM->patm.s.mmio.pCachedData, sizeof(RTRCPTR)); 3701 3701 AssertRC(rc); 3702 3702 if (RT_FAILURE(rc)) … … 3733 3733 { 3734 3734 DISCPUSTATE cpu; 3735 uint32_t opsize;3735 uint32_t cbInstr; 3736 3736 bool disret; 3737 3737 uint8_t *pInstrHC; … … 3745 3745 /* Disassemble mmio instruction. */ 3746 3746 disret = patmR3DisInstrNoStrOpMode(pVM, pPatch, pInstrGC, pInstrHC, PATMREAD_ORGCODE, 3747 &cpu, & opsize);3747 &cpu, &cbInstr); 3748 3748 if (disret == false) 3749 3749 { … … 3752 3752 } 3753 3753 3754 AssertMsg( opsize <= MAX_INSTR_SIZE, ("privileged instruction too big %d!!\n", opsize));3755 if ( opsize> MAX_INSTR_SIZE)3754 AssertMsg(cbInstr <= MAX_INSTR_SIZE, ("privileged instruction too big %d!!\n", cbInstr)); 3755 if (cbInstr > MAX_INSTR_SIZE) 3756 3756 return VERR_PATCHING_REFUSED; 3757 3757 if (cpu.param2.fUse != DISUSE_DISPLACEMENT32) … … 3759 3759 3760 3760 /* Add relocation record for cached data access. */ 3761 if (patmPatchAddReloc32(pVM, pPatch, &pInstrHC[cpu. opsize- sizeof(RTRCPTR)], FIXUP_ABSOLUTE) != VINF_SUCCESS)3761 if (patmPatchAddReloc32(pVM, pPatch, &pInstrHC[cpu.cbInstr - sizeof(RTRCPTR)], FIXUP_ABSOLUTE) != VINF_SUCCESS) 3762 3762 { 3763 3763 Log(("Relocation failed for cached mmio address!!\n")); … … 3765 3765 } 3766 3766 /* Replace address with that of the cached item. */ 3767 *(RTRCPTR *)&pInstrHC[cpu. opsize- sizeof(RTRCPTR)] = pVM->patm.s.mmio.pCachedData;3767 *(RTRCPTR *)&pInstrHC[cpu.cbInstr - sizeof(RTRCPTR)] = pVM->patm.s.mmio.pCachedData; 3768 3768 3769 3769 /* Lowest and highest address for write monitoring. */ 3770 3770 pPatch->pInstrGCLowest = pInstrGC; 3771 pPatch->pInstrGCHighest = pInstrGC + cpu. opsize;3771 pPatch->pInstrGCHighest = pInstrGC + cpu.cbInstr; 3772 3772 3773 3773 PATM_LOG_ORG_PATCH_INSTR(pVM, pPatch, "MMIO"); … … 3859 3859 /* Lowest and highest address for write monitoring. */ 3860 3860 pPatch->pInstrGCLowest = pInstrGC; 3861 pPatch->pInstrGCHighest = pInstrGC + pCpu-> opsize;3861 pPatch->pInstrGCHighest = pInstrGC + pCpu->cbInstr; 3862 3862 3863 3863 pPatch->uState = PATCH_ENABLED; … … 3921 3921 goto failure; 3922 3922 3923 Assert(pCpu-> opsize == SIZEOF_NEARJUMP32 || pCpu->opsize== SIZEOF_NEAR_COND_JUMP32);3924 if (pCpu-> opsize != SIZEOF_NEARJUMP32 && pCpu->opsize!= SIZEOF_NEAR_COND_JUMP32)3923 Assert(pCpu->cbInstr == SIZEOF_NEARJUMP32 || pCpu->cbInstr == SIZEOF_NEAR_COND_JUMP32); 3924 if (pCpu->cbInstr != SIZEOF_NEARJUMP32 && pCpu->cbInstr != SIZEOF_NEAR_COND_JUMP32) 3925 3925 goto failure; 3926 3926 3927 if (PAGE_ADDRESS(pInstrGC) != PAGE_ADDRESS(pInstrGC + pCpu-> opsize))3927 if (PAGE_ADDRESS(pInstrGC) != PAGE_ADDRESS(pInstrGC + pCpu->cbInstr)) 3928 3928 { 3929 3929 STAM_COUNTER_INC(&pVM->patm.s.StatPageBoundaryCrossed); … … 3940 3940 3941 3941 // make a copy of the guest code bytes that will be overwritten 3942 Assert(pCpu-> opsize<= sizeof(pPatch->aPrivInstr));3943 Assert(pCpu-> opsize>= SIZEOF_NEARJUMP32);3944 pPatch->cbPatchJump = pCpu-> opsize;3942 Assert(pCpu->cbInstr <= sizeof(pPatch->aPrivInstr)); 3943 Assert(pCpu->cbInstr >= SIZEOF_NEARJUMP32); 3944 pPatch->cbPatchJump = pCpu->cbInstr; 3945 3945 3946 3946 rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump); … … 3952 3952 * references the target instruction in the conflict patch. 3953 3953 */ 3954 RTRCPTR pJmpDest = PATMR3GuestGCPtrToPatchGCPtr(pVM, pInstrGC + pCpu-> opsize+ (int32_t)pCpu->param1.parval);3955 3956 AssertMsg(pJmpDest, ("PATMR3GuestGCPtrToPatchGCPtr failed for %RRv\n", pInstrGC + pCpu-> opsize+ (int32_t)pCpu->param1.parval));3954 RTRCPTR pJmpDest = PATMR3GuestGCPtrToPatchGCPtr(pVM, pInstrGC + pCpu->cbInstr + (int32_t)pCpu->param1.parval); 3955 3956 AssertMsg(pJmpDest, ("PATMR3GuestGCPtrToPatchGCPtr failed for %RRv\n", pInstrGC + pCpu->cbInstr + (int32_t)pCpu->param1.parval)); 3957 3957 pPatch->pPatchJumpDestGC = pJmpDest; 3958 3958 … … 4026 4026 DISCPUSTATE cpu; 4027 4027 R3PTRTYPE(uint8_t *) pInstrHC; 4028 uint32_t opsize;4028 uint32_t cbInstr; 4029 4029 PPATMPATCHREC pPatchRec; 4030 4030 PCPUMCTX pCtx = 0; … … 4242 4242 } 4243 4243 4244 disret = patmR3DisInstrNoStrOpMode(pVM, &pPatchRec->patch, pInstrGC, NULL, PATMREAD_ORGCODE, &cpu, & opsize);4244 disret = patmR3DisInstrNoStrOpMode(pVM, &pPatchRec->patch, pInstrGC, NULL, PATMREAD_ORGCODE, &cpu, &cbInstr); 4245 4245 if (disret == false) 4246 4246 { … … 4249 4249 } 4250 4250 4251 AssertMsg( opsize <= MAX_INSTR_SIZE, ("privileged instruction too big %d!!\n", opsize));4252 if ( opsize> MAX_INSTR_SIZE)4251 AssertMsg(cbInstr <= MAX_INSTR_SIZE, ("privileged instruction too big %d!!\n", cbInstr)); 4252 if (cbInstr > MAX_INSTR_SIZE) 4253 4253 return VERR_PATCHING_REFUSED; 4254 4254 4255 pPatchRec->patch.cbPrivInstr = opsize;4255 pPatchRec->patch.cbPrivInstr = cbInstr; 4256 4256 pPatchRec->patch.opcode = cpu.pCurInstr->opcode; 4257 4257 … … 4308 4308 pPatchRec->patch.flags |= PATMFL_IDTHANDLER; /* we treat a sysenter handler as an IDT handler */ 4309 4309 4310 rc = patmIdtHandler(pVM, pInstrGC, opsize, pPatchRec, &cacheRec);4310 rc = patmIdtHandler(pVM, pInstrGC, cbInstr, pPatchRec, &cacheRec); 4311 4311 #ifdef VBOX_WITH_STATISTICS 4312 4312 if ( rc == VINF_SUCCESS … … 4384 4384 case OP_CLI: 4385 4385 Log(("PATMR3InstallPatch %s %RRv code32=%d\n", patmGetInstructionString(pPatchRec->patch.opcode, pPatchRec->patch.flags), pInstrGC, (flags & PATMFL_CODE32) ? 1 : 0)); 4386 rc = PATMR3PatchBlock(pVM, pInstrGC, pInstrHC, cpu.pCurInstr->opcode, opsize, pPatchRec);4386 rc = PATMR3PatchBlock(pVM, pInstrGC, pInstrHC, cpu.pCurInstr->opcode, cbInstr, pPatchRec); 4387 4387 break; 4388 4388 … … 4493 4493 DISCPUSTATE cpu; 4494 4494 bool disret; 4495 uint32_t opsize;4496 4497 disret = patmR3DisInstr(pVM, pPatch, pInstrGC, pInstrHC, PATMREAD_ORGCODE | PATMREAD_NOCHECK, &cpu, & opsize);4495 uint32_t cbInstr; 4496 4497 disret = patmR3DisInstr(pVM, pPatch, pInstrGC, pInstrHC, PATMREAD_ORGCODE | PATMREAD_NOCHECK, &cpu, &cbInstr); 4498 4498 PGMPhysReleasePageMappingLock(pVM, &Lock); 4499 4499 if (disret) 4500 return opsize;4500 return cbInstr; 4501 4501 } 4502 4502 return 0; … … 5187 5187 DISCPUSTATE cpu; 5188 5188 R3PTRTYPE(uint8_t *) pInstrHC; 5189 uint32_t opsize;5189 uint32_t cbInstr; 5190 5190 bool disret; 5191 5191 int rc; … … 5193 5193 RT_ZERO(patch); 5194 5194 pInstrHC = PATMGCVirtToHCVirt(pVM, &patch, pInstrGC); 5195 disret = patmR3DisInstr(pVM, &patch, pInstrGC, pInstrHC, PATMREAD_ORGCODE, &cpu, & opsize);5195 disret = patmR3DisInstr(pVM, &patch, pInstrGC, pInstrHC, PATMREAD_ORGCODE, &cpu, &cbInstr); 5196 5196 /* 5197 5197 * If it's a 5 byte relative jump, then we can work around the problem by replacing the 32 bits relative offset … … 5335 5335 DISCPUSTATE cpu; 5336 5336 char szOutput[256]; 5337 uint32_t opsize;5337 uint32_t cbInstr; 5338 5338 uint32_t i = 0; 5339 5339 bool disret; … … 5341 5341 { 5342 5342 disret = patmR3DisInstrToStr(pVM, pPatch, pPatch->pPrivInstrGC + i, NULL, PATMREAD_ORGCODE, 5343 &cpu, & opsize, szOutput, sizeof(szOutput));5343 &cpu, &cbInstr, szOutput, sizeof(szOutput)); 5344 5344 Log(("Renewed patch instr: %s", szOutput)); 5345 i += opsize;5345 i += cbInstr; 5346 5346 } 5347 5347 } … … 6020 6020 { 6021 6021 if (RT_SUCCESS(rc)) 6022 cbDirty += CpuOld. opsize;6022 cbDirty += CpuOld.cbInstr; 6023 6023 else 6024 6024 if (!cbDirty) … … 6040 6040 pPatchToGuestRec = NULL; 6041 6041 6042 pCurPatchInstrGC += CpuOld. opsize;6043 cbDirty += CpuOld. opsize;6042 pCurPatchInstrGC += CpuOld.cbInstr; 6043 cbDirty += CpuOld.cbInstr; 6044 6044 6045 6045 /* Let's see if there's another dirty instruction right after. */ … … 6086 6086 /* If the instruction is completely harmless (which implies a 1:1 patch copy). */ 6087 6087 if ( rc == VINF_SUCCESS 6088 && CpuNew. opsize<= cbLeft /* must still fit */6088 && CpuNew.cbInstr <= cbLeft /* must still fit */ 6089 6089 && fValidInstr 6090 6090 ) … … 6098 6098 6099 6099 /* Copy the new instruction. */ 6100 rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pCurPatchInstrHC, pCurInstrGC, CpuNew. opsize);6100 rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pCurPatchInstrHC, pCurInstrGC, CpuNew.cbInstr); 6101 6101 AssertRC(rc); 6102 6102 … … 6119 6119 break; 6120 6120 } 6121 pCurInstrGC += CpuNew. opsize;6122 pCurPatchInstrHC += CpuNew. opsize;6123 pCurPatchInstrGC += CpuNew. opsize;6124 cbLeft -= CpuNew. opsize;6121 pCurInstrGC += CpuNew.cbInstr; 6122 pCurPatchInstrHC += CpuNew.cbInstr; 6123 pCurPatchInstrGC += CpuNew.cbInstr; 6124 cbLeft -= CpuNew.cbInstr; 6125 6125 6126 6126 /* Check if we expanded a complex guest instruction into a patch stream (e.g. call) */ … … 6402 6402 DISCPUSTATE cpu; 6403 6403 bool disret; 6404 uint32_t opsize;6404 uint32_t cbInstr; 6405 6405 PATMP2GLOOKUPREC cacheRec; 6406 6406 RT_ZERO(cacheRec); … … 6408 6408 6409 6409 disret = patmR3DisInstr(pVM, &pPatch->patch, pNewEip, PATMGCVirtToHCVirt(pVM, &cacheRec, pNewEip), PATMREAD_RAWCODE, 6410 &cpu, & opsize);6410 &cpu, &cbInstr); 6411 6411 if (cacheRec.Lock.pvMap) 6412 6412 PGMPhysReleasePageMappingLock(pVM, &cacheRec.Lock); … … 6441 6441 DISCPUSTATE cpu; 6442 6442 bool disret; 6443 uint32_t opsize;6443 uint32_t cbInstr; 6444 6444 PATMP2GLOOKUPREC cacheRec; 6445 6445 RT_ZERO(cacheRec); … … 6447 6447 6448 6448 disret = patmR3DisInstr(pVM, &pPatch->patch, pNewEip, PATMGCVirtToHCVirt(pVM, &cacheRec, pNewEip), PATMREAD_ORGCODE, 6449 &cpu, & opsize);6449 &cpu, &cbInstr); 6450 6450 if (cacheRec.Lock.pvMap) 6451 6451 PGMPhysReleasePageMappingLock(pVM, &cacheRec.Lock); … … 6455 6455 cpu.mode = (pPatch->patch.flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 6456 6456 disret = patmR3DisInstr(pVM, &pPatch->patch, pNewEip, PATMGCVirtToHCVirt(pVM, &cacheRec, pNewEip), PATMREAD_RAWCODE, 6457 &cpu, & opsize);6457 &cpu, &cbInstr); 6458 6458 if (cacheRec.Lock.pvMap) 6459 6459 PGMPhysReleasePageMappingLock(pVM, &cacheRec.Lock); -
trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
r41728 r41732 421 421 PATCHGEN_PROLOG(pVM, pPatch); 422 422 423 uint32_t const cbInstrShutUpGcc = pCpu-> opsize;423 uint32_t const cbInstrShutUpGcc = pCpu->cbInstr; 424 424 rc = patmPatchReadBytes(pVM, pPB, pCurInstrGC, cbInstrShutUpGcc); 425 425 AssertRC(rc); … … 712 712 i++; //skip segment prefix 713 713 714 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu-> opsize- i);714 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu->cbInstr - i); 715 715 AssertRCReturn(rc, rc); 716 offset += (pCpu-> opsize- i);716 offset += (pCpu->cbInstr - i); 717 717 } 718 718 else … … 725 725 726 726 /* Relative call to patch code (patch to patch -> no fixup). */ 727 Log(("PatchGenCall from %RRv (next=%RRv) to %RRv\n", pCurInstrGC, pCurInstrGC + pCpu-> opsize, pTargetGC));727 Log(("PatchGenCall from %RRv (next=%RRv) to %RRv\n", pCurInstrGC, pCurInstrGC + pCpu->cbInstr, pTargetGC)); 728 728 729 729 /* We push it onto the stack here, so the guest's context isn't ruined when this happens to cause … … 749 749 /* 3: Generate code to lookup address in our local cache; call hypervisor PATM code if it can't be located. */ 750 750 PATCHGEN_PROLOG_NODEF(pVM, pPatch); 751 callInfo.pReturnGC = pCurInstrGC + pCpu-> opsize;751 callInfo.pReturnGC = pCurInstrGC + pCpu->cbInstr; 752 752 callInfo.pTargetGC = (fIndirect) ? 0xDEADBEEF : pTargetGC; 753 753 size = patmPatchGenCode(pVM, pPatch, pPB, (fIndirect) ? &PATMCallIndirectRecord : &PATMCallRecord, 0, false, &callInfo); … … 809 809 i++; //skip segment prefix 810 810 811 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu-> opsize- i);811 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu->cbInstr - i); 812 812 AssertRCReturn(rc, rc); 813 offset += (pCpu-> opsize- i);813 offset += (pCpu->cbInstr - i); 814 814 815 815 /* align this block properly to make sure the jump table will not be misaligned. */ … … 826 826 /* 3: Generate code to lookup address in our local cache; call hypervisor PATM code if it can't be located. */ 827 827 PATCHGEN_PROLOG_NODEF(pVM, pPatch); 828 callInfo.pReturnGC = pCurInstrGC + pCpu-> opsize;828 callInfo.pReturnGC = pCurInstrGC + pCpu->cbInstr; 829 829 callInfo.pTargetGC = 0xDEADBEEF; 830 830 size = patmPatchGenCode(pVM, pPatch, pPB, &PATMJumpIndirectRecord, 0, false, &callInfo); … … 1375 1375 i++; //skip segment prefix 1376 1376 1377 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu-> opsize- i);1377 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu->cbInstr - i); 1378 1378 AssertRCReturn(rc, rc); 1379 offset += (pCpu-> opsize- i);1379 offset += (pCpu->cbInstr - i); 1380 1380 1381 1381 pPB[offset++] = 0x66; // mov ax, CPUMCTX.tr/ldtr … … 1469 1469 if (pCpu->prefix == DISPREFIX_SEG) 1470 1470 i++; //skip segment prefix 1471 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu-> opsize- i);1471 rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu->cbInstr - i); 1472 1472 AssertRCReturn(rc, rc); 1473 offset += (pCpu-> opsize- i);1473 offset += (pCpu->cbInstr - i); 1474 1474 1475 1475 pPB[offset++] = 0x66; // mov ax, CPUMCTX.gdtr.limit -
trunk/src/VBox/VMM/VMMRC/TRPMRC.cpp
r40449 r41732 187 187 { 188 188 /* Just ignore the write. */ 189 pRegFrame->eip += Cpu. opsize;189 pRegFrame->eip += Cpu.cbInstr; 190 190 return VINF_SUCCESS; 191 191 } -
trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
r41678 r41732 754 754 } 755 755 } 756 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu-> opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);756 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd); 757 757 if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP) 758 758 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame); … … 775 775 break; 776 776 777 pRegFrame->eip += pCpu-> opsize;777 pRegFrame->eip += pCpu->cbInstr; 778 778 return trpmGCExitTrap(pVM, pVCpu, VINF_EM_HALT, pRegFrame); 779 779 … … 846 846 { 847 847 Assert(pCpu->param1.fUse & DISUSE_IMMEDIATE8); 848 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu-> opsize, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);848 rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd); 849 849 if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP) 850 850 return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame); -
trunk/src/VBox/VMM/include/CSAMInternal.h
r41678 r41732 271 271 } 272 272 #ifdef IN_RC 273 return (RTRCPTR)((uint8_t *)pBranchInstrGC + pCpu-> opsize+ disp);273 return (RTRCPTR)((uint8_t *)pBranchInstrGC + pCpu->cbInstr + disp); 274 274 #else 275 return pBranchInstrGC + pCpu-> opsize+ disp;275 return pBranchInstrGC + pCpu->cbInstr + disp; 276 276 #endif 277 277 } -
trunk/src/VBox/VMM/include/PATMInternal.h
r41678 r41732 781 781 } 782 782 #ifdef IN_RC 783 return (RTRCPTR)((uint8_t *)pBranchInstrGC + pCpu-> opsize+ disp);783 return (RTRCPTR)((uint8_t *)pBranchInstrGC + pCpu->cbInstr + disp); 784 784 #else 785 return pBranchInstrGC + pCpu-> opsize+ disp;785 return pBranchInstrGC + pCpu->cbInstr + disp; 786 786 #endif 787 787 } -
trunk/src/VBox/VMM/testcase/tstVMStruct.h
r41692 r41732 1404 1404 GEN_CHECK_OFF(DISCPUSTATE, fFilter); 1405 1405 GEN_CHECK_OFF(DISCPUSTATE, uInstrAddr); 1406 #endif 1406 GEN_CHECK_OFF(DISCPUSTATE, abInstr); 1407 GEN_CHECK_OFF(DISCPUSTATE, pvUser); 1408 #endif
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