Changeset 41737 in vbox for trunk/src/VBox/Disassembler/testcase

Timestamp:

Jun 15, 2012 1:01:49 AM (12 years ago)

Author:

vboxsync

Message:

DISOPCODE: s/opcode/uOpcode/

File:

• trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp (modified) (4 diffs)

trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp

@@ -132 +132 @@
 static bool MyDisasIsValidInstruction(DISCPUSTATE const *pCpu)
 {
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         /* These doesn't take memory operands. */
@@ -338 +338 @@
             State.fUndefOp = rc == VERR_DIS_INVALID_OPCODE
                           || rc == VERR_DIS_GEN_FAILURE
-                          || State.Cpu.pCurInstr->opcode == OP_INVALID
-                          || State.Cpu.pCurInstr->opcode == OP_ILLUD2
+                          || State.Cpu.pCurInstr->uOpcode == OP_INVALID
+                          || State.Cpu.pCurInstr->uOpcode == OP_ILLUD2
                           || (    State.enmUndefOp == kUndefOp_DefineByte
                               && !MyDisasIsValidInstruction(&State.Cpu));
@@ -357 +357 @@
             else if (!State.fUndefOp && State.enmUndefOp == kUndefOp_All)
             {
-                RTPrintf("%s: error at %#RX64: unexpected valid instruction (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
+                RTPrintf("%s: error at %#RX64: unexpected valid instruction (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->uOpcode);
                 pfnFormatter(&State);
                 rcRet = VERR_GENERAL_FAILURE;
@@ -363 +363 @@
             else if (State.fUndefOp && State.enmUndefOp == kUndefOp_Fail)
             {
-                RTPrintf("%s: error at %#RX64: undefined opcode (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
+                RTPrintf("%s: error at %#RX64: undefined opcode (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->uOpcode);
                 pfnFormatter(&State);
                 rcRet = VERR_GENERAL_FAILURE;