VirtualBox

Changeset 41739 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jun 15, 2012 1:31:29 AM (13 years ago)
Author:
vboxsync
Message:

DISCPUSTATE: s/param/Param/

Location:
trunk/src/VBox/VMM
Files:
15 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r41737 r41739  
    809809
    810810    /* Source to make DISQueryParamVal read the register value - ugly hack */
    811     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     811    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    812812    if(RT_FAILURE(rc))
    813813        return VERR_EM_INTERPRETER;
    814814
    815     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     815    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    816816    if(RT_FAILURE(rc))
    817817        return VERR_EM_INTERPRETER;
    … …  
    826826            uint64_t valpar1, valpar2;
    827827
    828             AssertReturn(pDis->param1.cb == pDis->param2.cb, VERR_EM_INTERPRETER);
     828            AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
    829829            switch(param1.type)
    830830            {
    … …  
    835835            case DISQPV_TYPE_ADDRESS:
    836836                pParam1 = (RTGCPTR)param1.val.val64;
    837                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     837                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    838838                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
    839839                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
    … …  
    854854            case DISQPV_TYPE_ADDRESS:
    855855                pParam2 = (RTGCPTR)param2.val.val64;
    856                 pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pParam2);
     856                pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
    857857                EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
    858858                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
    … …  
    879879                {
    880880                case 1: //special case for AH etc
    881                         rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen,  (uint8_t )valpar2); break;
    882                 case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)valpar2); break;
    883                 case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)valpar2); break;
    884                 case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, valpar2); break;
     881                        rc = DISWriteReg8(pRegFrame, pDis->Param1.base.reg_gen,  (uint8_t )valpar2); break;
     882                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, (uint16_t)valpar2); break;
     883                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.base.reg_gen, (uint32_t)valpar2); break;
     884                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.base.reg_gen, valpar2); break;
    885885                default: AssertFailedReturn(VERR_EM_INTERPRETER);
    886886                }
    … …  
    905905                {
    906906                case 1: //special case for AH etc
    907                         rc = DISWriteReg8(pRegFrame, pDis->param2.base.reg_gen,  (uint8_t )valpar1);    break;
    908                 case 2: rc = DISWriteReg16(pRegFrame, pDis->param2.base.reg_gen, (uint16_t)valpar1);    break;
    909                 case 4: rc = DISWriteReg32(pRegFrame, pDis->param2.base.reg_gen, (uint32_t)valpar1);    break;
    910                 case 8: rc = DISWriteReg64(pRegFrame, pDis->param2.base.reg_gen, valpar1);              break;
     907                        rc = DISWriteReg8(pRegFrame, pDis->Param2.base.reg_gen,  (uint8_t )valpar1);    break;
     908                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.base.reg_gen, (uint16_t)valpar1);    break;
     909                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.base.reg_gen, (uint32_t)valpar1);    break;
     910                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.base.reg_gen, valpar1);              break;
    911911                default: AssertFailedReturn(VERR_EM_INTERPRETER);
    912912                }
    … …  
    943943    NOREF(pvFault);
    944944
    945     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     945    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    946946    if(RT_FAILURE(rc))
    947947        return VERR_EM_INTERPRETER;
    … …  
    959959            {
    960960                pParam1 = (RTGCPTR)param1.val.val64;
    961                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     961                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    962962#ifdef IN_RC
    963963                /* Safety check (in theory it could cross a page boundary and fault there though) */
    … …  
    10131013    NOREF(pvFault);
    10141014
    1015     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1015    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    10161016    if(RT_FAILURE(rc))
    10171017        return VERR_EM_INTERPRETER;
    … …  
    10491049                /* pop [esp+xx] uses esp after the actual pop! */
    10501050                AssertCompile(DISGREG_ESP == DISGREG_SP);
    1051                 if (    (pDis->param1.fUse & DISUSE_BASE)
    1052                     &&  (pDis->param1.fUse & (DISUSE_REG_GEN16|DISUSE_REG_GEN32))
    1053                     &&  pDis->param1.base.reg_gen == DISGREG_ESP
     1051                if (    (pDis->Param1.fUse & DISUSE_BASE)
     1052                    &&  (pDis->Param1.fUse & (DISUSE_REG_GEN16|DISUSE_REG_GEN32))
     1053                    &&  pDis->Param1.base.reg_gen == DISGREG_ESP
    10541054                   )
    10551055                   pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
    10561056
    1057                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     1057                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    10581058                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
    10591059                rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
    … …  
    10951095    NOREF(pvFault);
    10961096
    1097     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1097    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    10981098    if(RT_FAILURE(rc))
    10991099        return VERR_EM_INTERPRETER;
    11001100
    1101     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1101    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    11021102    if(RT_FAILURE(rc))
    11031103        return VERR_EM_INTERPRETER;
    … …  
    11121112            uint64_t valpar1, valpar2;
    11131113
    1114             if (pDis->param1.cb != pDis->param2.cb)
     1114            if (pDis->Param1.cb != pDis->Param2.cb)
    11151115            {
    1116                 if (pDis->param1.cb < pDis->param2.cb)
     1116                if (pDis->Param1.cb < pDis->Param2.cb)
    11171117                {
    1118                     AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.cb, pDis->param2.cb)); /* should never happen! */
     1118                    AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
    11191119                    return VERR_EM_INTERPRETER;
    11201120                }
    11211121                /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
    1122                 pDis->param2.cb = pDis->param1.cb;
     1122                pDis->Param2.cb = pDis->Param1.cb;
    11231123                param2.size     = param1.size;
    11241124            }
    … …  
    11281128            {
    11291129                pParam1 = (RTGCPTR)param1.val.val64;
    1130                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     1130                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    11311131                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
    11321132                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
    … …  
    11931193
    11941194#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
    1195     Assert(pDis->param1.cb <= 4);
    1196 #endif
    1197 
    1198     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1195    Assert(pDis->Param1.cb <= 4);
     1196#endif
     1197
     1198    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    11991199    if(RT_FAILURE(rc))
    12001200        return VERR_EM_INTERPRETER;
    12011201
    1202     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1202    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    12031203    if(RT_FAILURE(rc))
    12041204        return VERR_EM_INTERPRETER;
    12051205
    1206     if (pDis->param1.cb != pDis->param2.cb)
    1207     {
    1208         AssertMsgReturn(pDis->param1.cb >= pDis->param2.cb, /* should never happen! */
    1209                         ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.cb, pDis->param2.cb),
     1206    if (pDis->Param1.cb != pDis->Param2.cb)
     1207    {
     1208        AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
     1209                        ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
    12101210                        VERR_EM_INTERPRETER);
    12111211
    12121212        /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
    1213         pDis->param2.cb = pDis->param1.cb;
     1213        pDis->Param2.cb = pDis->Param1.cb;
    12141214        param2.size       = param1.size;
    12151215    }
    … …  
    12301230
    12311231    RTGCPTR GCPtrPar1 = param1.val.val64;
    1232     GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
     1232    GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
    12331233    PGMPAGEMAPLOCK Lock;
    12341234    rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
    … …  
    12361236
    12371237    /* Try emulate it with a one-shot #PF handler in place. (RC) */
    1238     Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.cb*8, ValPar2));
     1238    Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
    12391239
    12401240    RTGCUINTREG32 eflags = 0;
    1241     rc = pfnEmulate(pvParam1, ValPar2, pDis->param2.cb, &eflags);
     1241    rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
    12421242    PGMPhysReleasePageMappingLock(pVM, &Lock);
    12431243    if (RT_FAILURE(rc))
    12441244    {
    1245         Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.cb*8, ValPar2));
     1245        Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
    12461246        return VERR_EM_INTERPRETER;
    12471247    }
    … …  
    12641264    NOREF(pvFault);
    12651265    DISQPVPARAMVAL param1, param2;
    1266     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1266    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    12671267    if(RT_FAILURE(rc))
    12681268        return VERR_EM_INTERPRETER;
    12691269
    1270     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1270    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    12711271    if(RT_FAILURE(rc))
    12721272        return VERR_EM_INTERPRETER;
    … …  
    12811281            uint64_t valpar1, valpar2;
    12821282
    1283             if (pDis->param1.cb != pDis->param2.cb)
     1283            if (pDis->Param1.cb != pDis->Param2.cb)
    12841284            {
    1285                 if (pDis->param1.cb < pDis->param2.cb)
     1285                if (pDis->Param1.cb < pDis->Param2.cb)
    12861286                {
    1287                     AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.cb, pDis->param2.cb)); /* should never happen! */
     1287                    AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
    12881288                    return VERR_EM_INTERPRETER;
    12891289                }
    12901290                /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
    1291                 pDis->param2.cb = pDis->param1.cb;
     1291                pDis->Param2.cb = pDis->Param1.cb;
    12921292                param2.size     = param1.size;
    12931293            }
    … …  
    12971297            {
    12981298                pParam1 = (RTGCPTR)param1.val.val64;
    1299                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     1299                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    13001300                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
    13011301                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
    … …  
    13681368{
    13691369    DISQPVPARAMVAL param1, param2;
    1370     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1370    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    13711371    if(RT_FAILURE(rc))
    13721372        return VERR_EM_INTERPRETER;
    13731373
    1374     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1374    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    13751375    if(RT_FAILURE(rc))
    13761376        return VERR_EM_INTERPRETER;
    … …  
    13911391
    13921392            pParam1 = (RTGCPTR)param1.val.val64;
    1393             pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     1393            pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    13941394
    13951395            /* Register or immediate data */
    … …  
    14501450
    14511451    DISQPVPARAMVAL param1, param2;
    1452     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1452    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    14531453    if(RT_FAILURE(rc))
    14541454        return VERR_EM_INTERPRETER;
    14551455
    1456     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1456    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    14571457    if(RT_FAILURE(rc))
    14581458        return VERR_EM_INTERPRETER;
    … …  
    14711471    ValPar2 &= 7;
    14721472
    1473     GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
     1473    GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
    14741474#ifdef IN_RC
    14751475    Assert(TRPMHasTrap(pVCpu));
    … …  
    14901490    {
    14911491        Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
    1492              emGetMnemonic(pDis), GCPtrPar1, pDis->param2.cb*8, ValPar2));
     1492             emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
    14931493        return VERR_EM_INTERPRETER;
    14941494    }
    … …  
    15121512    NOREF(pvFault);
    15131513    DISQPVPARAMVAL param1, param2;
    1514     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_DST);
     1514    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
    15151515    if(RT_FAILURE(rc))
    15161516        return VERR_EM_INTERPRETER;
    15171517
    1518     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1518    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    15191519    if(RT_FAILURE(rc))
    15201520        return VERR_EM_INTERPRETER;
    … …  
    15421542            case DISQPV_TYPE_ADDRESS:
    15431543                pDest = (RTGCPTR)param1.val.val64;
    1544                 pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pDest);
     1544                pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
    15451545                break;
    15461546
    … …  
    15901590            case DISQPV_TYPE_ADDRESS:
    15911591                pSrc = (RTGCPTR)param2.val.val64;
    1592                 pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pSrc);
     1592                pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
    15931593                break;
    15941594
    … …  
    16091609                switch(param1.size)
    16101610                {
    1611                 case 1: rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen,  (uint8_t) val64); break;
    1612                 case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)val64); break;
    1613                 case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)val64); break;
    1614                 case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, val64); break;
     1611                case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.base.reg_gen,  (uint8_t) val64); break;
     1612                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, (uint16_t)val64); break;
     1613                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.base.reg_gen, (uint32_t)val64); break;
     1614                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.base.reg_gen, val64); break;
    16151615                default:
    16161616                    return VERR_EM_INTERPRETER;
    … …  
    18031803
    18041804#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
    1805     Assert(pDis->param1.cb <= 4);
     1805    Assert(pDis->Param1.cb <= 4);
    18061806#endif
    18071807
    18081808    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1809     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     1809    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    18101810    if(RT_FAILURE(rc))
    18111811        return VERR_EM_INTERPRETER;
    18121812
    1813     rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, DISQPVWHICH_SRC);
     1813    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
    18141814    if(RT_FAILURE(rc))
    18151815        return VERR_EM_INTERPRETER;
    … …  
    18311831    uint64_t eflags;
    18321832
    1833     AssertReturn(pDis->param1.cb == pDis->param2.cb, VERR_EM_INTERPRETER);
     1833    AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
    18341834    switch(param1.type)
    18351835    {
    18361836    case DISQPV_TYPE_ADDRESS:
    18371837        GCPtrPar1 = param1.val.val64;
    1838         GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
     1838        GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
    18391839
    18401840        rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
    … …  
    18491849
    18501850    if (pDis->fPrefix & DISPREFIX_LOCK)
    1851         eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.cb);
     1851        eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
    18521852    else
    1853         eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.cb);
     1853        eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
    18541854
    18551855    LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
    … …  
    18751875
    18761876    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1877     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     1877    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    18781878    if(RT_FAILURE(rc))
    18791879        return VERR_EM_INTERPRETER;
    … …  
    18841884    PGMPAGEMAPLOCK Lock;
    18851885
    1886     AssertReturn(pDis->param1.cb == 8, VERR_EM_INTERPRETER);
     1886    AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
    18871887    switch(param1.type)
    18881888    {
    18891889    case DISQPV_TYPE_ADDRESS:
    18901890        GCPtrPar1 = param1.val.val64;
    1891         GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
     1891        GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
    18921892
    18931893        rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
    … …  
    19311931
    19321932    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1933     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     1933    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    19341934    if(RT_FAILURE(rc))
    19351935        return VERR_EM_INTERPRETER;
    19361936
    1937     rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->param2, &pvParamReg2, &cbParamReg2);
     1937    rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
    19381938    Assert(cbParamReg2 <= 4);
    19391939    if(RT_FAILURE(rc))
    … …  
    19511951            PGMPAGEMAPLOCK  Lock;
    19521952
    1953             AssertReturn(pDis->param1.cb == pDis->param2.cb, VERR_EM_INTERPRETER);
     1953            AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
    19541954            switch(param1.type)
    19551955            {
    19561956            case DISQPV_TYPE_ADDRESS:
    1957                 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTRCUINTPTR)param1.val.val64);
     1957                GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
    19581958#ifdef IN_RC
    19591959                EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
    … …  
    20542054    NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
    20552055
    2056     VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     2056    VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    20572057    if(RT_FAILURE(rc))
    20582058        return VERR_EM_INTERPRETER;
    … …  
    23892389    NOREF(pvFault); NOREF(pcbSize);
    23902390
    2391     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     2391    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    23922392    if(RT_FAILURE(rc))
    23932393        return VERR_EM_INTERPRETER;
    … …  
    24192419    uint64_t    cr0 = CPUMGetGuestCR0(pVCpu);
    24202420
    2421     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     2421    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    24222422    if(RT_FAILURE(rc))
    24232423        return VERR_EM_INTERPRETER;
    … …  
    24282428        if(param1.size != sizeof(uint16_t))
    24292429            return VERR_EM_INTERPRETER;
    2430         LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->param1.base.reg_gen, cr0));
    2431         rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, cr0);
     2430        LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.base.reg_gen, cr0));
     2431        rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, cr0);
    24322432        break;
    24332433
    … …  
    24412441
    24422442        pParam1 = (RTGCPTR)param1.val.val64;
    2443         pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
     2443        pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
    24442444        LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
    24452445
    … …  
    24682468{
    24692469    NOREF(pvFault); NOREF(pcbSize);
    2470     if ((pDis->param1.fUse == DISUSE_REG_GEN32 || pDis->param1.fUse == DISUSE_REG_GEN64) && pDis->param2.fUse == DISUSE_REG_CR)
    2471         return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_ctrl);
    2472 
    2473     if (pDis->param1.fUse == DISUSE_REG_CR && (pDis->param2.fUse == DISUSE_REG_GEN32 || pDis->param2.fUse == DISUSE_REG_GEN64))
    2474         return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_ctrl, pDis->param2.base.reg_gen);
     2470    if ((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
     2471        return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_gen, pDis->Param2.base.reg_ctrl);
     2472
     2473    if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
     2474        return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_ctrl, pDis->Param2.base.reg_gen);
    24752475
    24762476    AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
    … …  
    25582558    NOREF(pvFault); NOREF(pcbSize);
    25592559
    2560     if((pDis->param1.fUse == DISUSE_REG_GEN32 || pDis->param1.fUse == DISUSE_REG_GEN64) && pDis->param2.fUse == DISUSE_REG_DBG)
    2561     {
    2562         rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_dbg);
     2560    if((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
     2561    {
     2562        rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_gen, pDis->Param2.base.reg_dbg);
    25632563    }
    25642564    else
    2565     if(pDis->param1.fUse == DISUSE_REG_DBG && (pDis->param2.fUse == DISUSE_REG_GEN32 || pDis->param2.fUse == DISUSE_REG_GEN64))
    2566     {
    2567         rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_dbg, pDis->param2.base.reg_gen);
     2565    if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
     2566    {
     2567        rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_dbg, pDis->Param2.base.reg_gen);
    25682568    }
    25692569    else
    … …  
    25832583    NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
    25842584
    2585     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     2585    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    25862586    if(RT_FAILURE(rc))
    25872587        return VERR_EM_INTERPRETER;
    … …  
    26372637    AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
    26382638
    2639     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, DISQPVWHICH_SRC);
     2639    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
    26402640    if(RT_FAILURE(rc))
    26412641        return VERR_EM_INTERPRETER;
    … …  
    26442644    {
    26452645    case DISQPV_TYPE_ADDRESS:
    2646         pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, param1.val.val16);
     2646        pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
    26472647        break;
    26482648
    … …  
    31413141     * Whitelisted instructions are safe.
    31423142     */
    3143     if (    pDis->param1.cb > 4
     3143    if (    pDis->Param1.cb > 4
    31443144        &&  CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
    31453145    {

  • trunk/src/VBox/VMM/VMMAll/IOMAll.cpp

    r41730 r41739  
    958958    uint64_t    uPort = 0;
    959959    unsigned    cbSize = 0;
    960     bool fRc = iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uPort, &cbSize);
     960    bool fRc = iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uPort, &cbSize);
    961961    AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
    962962
    963     cbSize = DISGetParamSize(pCpu, &pCpu->param1);
     963    cbSize = DISGetParamSize(pCpu, &pCpu->Param1);
    964964    Assert(cbSize > 0);
    965965    VBOXSTRICTRC rcStrict = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, uPort, cbSize);
    … …  
    976976             * Store the result in the AL|AX|EAX register.
    977977             */
    978             fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, u32Data);
     978            fRc = iomSaveDataToReg(pCpu, &pCpu->Param1, pRegFrame, u32Data);
    979979            AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
    980980        }
    … …  
    10181018    uint64_t    uPort = 0;
    10191019    unsigned    cbSize = 0;
    1020     bool fRc = iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uPort, &cbSize);
     1020    bool fRc = iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &uPort, &cbSize);
    10211021    AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
    10221022
    … …  
    10251025    {
    10261026        uint64_t u64Data = 0;
    1027         fRc = iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &u64Data, &cbSize);
     1027        fRc = iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &u64Data, &cbSize);
    10281028        AssertMsg(fRc, ("Failed to get reg value!\n")); NOREF(fRc);
    10291029

  • trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp

    r41737 r41739  
    538538     * and call the handler function to get the data.
    539539     */
    540     unsigned cb = DISGetParamSize(pCpu, &pCpu->param2);
     540    unsigned cb = DISGetParamSize(pCpu, &pCpu->Param2);
    541541    AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
    542542
    … …  
    568568         * Store the result to register (parameter 1).
    569569         */
    570         bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, u64Data);
     570        bool fRc = iomSaveDataToReg(pCpu, &pCpu->Param1, pRegFrame, u64Data);
    571571        AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
    572572    }
    … …  
    599599    unsigned cb = 0;
    600600    uint64_t u64Data  = 0;
    601     bool fRc = iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &u64Data, &cb);
     601    bool fRc = iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &u64Data, &cb);
    602602    AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
    603603
    … …  
    701701     * Get data size.
    702702     */
    703     unsigned cb = DISGetParamSize(pCpu, &pCpu->param1);
     703    unsigned cb = DISGetParamSize(pCpu, &pCpu->Param1);
    704704    AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
    705705    int      offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
    … …  
    954954     * Get data size.
    955955     */
    956     unsigned cb = DISGetParamSize(pCpu, &pCpu->param1);
     956    unsigned cb = DISGetParamSize(pCpu, &pCpu->Param1);
    957957    AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
    958958    int      offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
    … …  
    10681068     * Get data size.
    10691069     */
    1070     unsigned cb = DISGetParamSize(pCpu, &pCpu->param2);
     1070    unsigned cb = DISGetParamSize(pCpu, &pCpu->Param2);
    10711071    AssertMsg(cb > 0 && cb <= sizeof(uint64_t), ("cb=%d\n", cb));
    10721072    int     offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
    … …  
    11181118    uint64_t uData2 = 0;
    11191119    int rc;
    1120     if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
     1120    if (iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &uData1, &cb))
    11211121        /* cmp reg, [MMIO]. */
    11221122        rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
    1123     else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
     1123    else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb))
    11241124        /* cmp [MMIO], reg|imm. */
    11251125        rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
    … …  
    11871187#endif
    11881188
    1189     if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
     1189    if (iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &uData1, &cb))
    11901190    {
    11911191#if HC_ARCH_BITS == 32
    … …  
    11991199        rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
    12001200    }
    1201     else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
     1201    else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb))
    12021202    {
    12031203#if HC_ARCH_BITS == 32
    … …  
    12331233        {
    12341234            /* Store result to register. */
    1235             bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData1);
     1235            bool fRc = iomSaveDataToReg(pCpu, &pCpu->Param1, pRegFrame, uData1);
    12361236            AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
    12371237        }
    … …  
    12731273    int         rc;
    12741274
    1275     if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
     1275    if (iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &uData1, &cb))
    12761276    {
    12771277        /* and test, [MMIO]. */
    12781278        rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
    12791279    }
    1280     else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
     1280    else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb))
    12811281    {
    12821282        /* test [MMIO], reg|imm. */
    … …  
    13301330    unsigned    cbIgnored;
    13311331
    1332     if (!iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uBit, &cbIgnored))
     1332    if (!iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uBit, &cbIgnored))
    13331333    {
    13341334        AssertMsgFailed(("Disassember BT problem..\n"));
    … …  
    13361336    }
    13371337    /* The size of the memory operand only matters here. */
    1338     unsigned cbData = DISGetParamSize(pCpu, &pCpu->param1);
     1338    unsigned cbData = DISGetParamSize(pCpu, &pCpu->Param1);
    13391339
    13401340    /* bt [MMIO], reg|imm. */
    … …  
    13761376    uint64_t    uData1 = 0;
    13771377    uint64_t    uData2 = 0;
    1378     if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
     1378    if (iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &uData1, &cb))
    13791379    {
    13801380        /* xchg reg, [MMIO]. */
    … …  
    13881388            {
    13891389                /* Store result to register. */
    1390                 bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData2);
     1390                bool fRc = iomSaveDataToReg(pCpu, &pCpu->Param1, pRegFrame, uData2);
    13911391                AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
    13921392            }
    … …  
    13971397            Assert(rc == VINF_IOM_R3_MMIO_READ || rc == VINF_PATM_HC_MMIO_PATCH_READ);
    13981398    }
    1399     else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
     1399    else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb))
    14001400    {
    14011401        /* xchg [MMIO], reg. */
    … …  
    14081408            {
    14091409                /* Store result to register. */
    1410                 bool fRc = iomSaveDataToReg(pCpu, &pCpu->param2, pRegFrame, uData1);
     1410                bool fRc = iomSaveDataToReg(pCpu, &pCpu->Param2, pRegFrame, uData1);
    14111411                AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
    14121412            }
    … …  
    15351535        {
    15361536            STAM_PROFILE_START(&pVM->iom.s.StatRZInstMov, b);
    1537             AssertMsg(uErrorCode == UINT32_MAX || DISUSE_IS_EFFECTIVE_ADDR(pDis->param1.fUse) == !!(uErrorCode & X86_TRAP_PF_RW), ("flags1=%#llx/%RTbool flags2=%#llx/%RTbool ErrCd=%#x\n", pDis->param1.fUse, DISUSE_IS_EFFECTIVE_ADDR(pDis->param1.fUse), pDis->param2.fUse, DISUSE_IS_EFFECTIVE_ADDR(pDis->param2.fUse), uErrorCode));
     1537            AssertMsg(uErrorCode == UINT32_MAX || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse) == !!(uErrorCode & X86_TRAP_PF_RW), ("flags1=%#llx/%RTbool flags2=%#llx/%RTbool ErrCd=%#x\n", pDis->Param1.fUse, DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse), pDis->Param2.fUse, DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse), uErrorCode));
    15381538            if (uErrorCode != UINT32_MAX    /* EPT+MMIO optimization */
    15391539                ? uErrorCode & X86_TRAP_PF_RW
    1540                 : DISUSE_IS_EFFECTIVE_ADDR(pDis->param1.fUse))
     1540                : DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse))
    15411541                rc = iomInterpretMOVxXWrite(pVM, pCtxCore, pDis, pRange, GCPhysFault);
    15421542            else
    … …  
    23112311    uint64_t    Port = 0;
    23122312    unsigned    cb = 0;
    2313     bool fRc = iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &Port, &cb);
     2313    bool fRc = iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &Port, &cb);
    23142314    AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
    23152315    if (pCpu->pCurInstr->uOpcode == OP_OUTSB)

  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r41737 r41739  
    761761#endif
    762762
    763     LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->param1.fUse,  pDis->param1.base.reg_gen));
     763    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse,  pDis->Param1.base.reg_gen));
    764764
    765765    /* Non-supervisor mode write means it's used for something else. */
    … …  
    804804            return false;
    805805    }
    806     if (    (    (pDis->param1.fUse & DISUSE_REG_GEN32)
    807              ||  (pDis->param1.fUse & DISUSE_REG_GEN64))
    808         &&  (pDis->param1.base.reg_gen == DISGREG_ESP))
     806    if (    (    (pDis->Param1.fUse & DISUSE_REG_GEN32)
     807             ||  (pDis->Param1.fUse & DISUSE_REG_GEN64))
     808        &&  (pDis->Param1.base.reg_gen == DISGREG_ESP))
    809809    {
    810810        Log4(("pgmPoolMonitorIsReused: ESP\n"));
    … …  
    887887                                          PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
    888888{
    889     unsigned uIncrement = pDis->param1.cb;
     889    unsigned uIncrement = pDis->Param1.cb;
    890890    NOREF(pVM);
    891891
    … …  
    975975#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
    976976    uint32_t    iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
    977     pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
     977    pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->Param1));
    978978    PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
    979979#else
    980     pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
     980    pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->Param1));
    981981#endif
    982982
    … …  
    11231123    if (    pPage->GCPtrLastAccessHandlerRip >= pRegFrame->rip - 0x40      /* observed loops in Windows 7 x64 */
    11241124        &&  pPage->GCPtrLastAccessHandlerRip <  pRegFrame->rip + 0x40
    1125         &&  pvFault == (pPage->GCPtrLastAccessHandlerFault + pDis->param1.cb)
     1125        &&  pvFault == (pPage->GCPtrLastAccessHandlerFault + pDis->Param1.cb)
    11261126        &&  pVCpu->pgm.s.cPoolAccessHandler == pPage->cLastAccessHandler + 1)
    11271127    {

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r41737 r41739  
    29232923    NOREF(uASID);
    29242924
    2925     int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, DISQPVWHICH_SRC);
     2925    int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &param1, DISQPVWHICH_SRC);
    29262926    if (RT_FAILURE(rc))
    29272927        return VERR_EM_INTERPRETER;

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r41737 r41739  
    37043704                        uint32_t intInfo2;
    37053705
    3706                         LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
    3707                         intInfo2  = pDis->param1.parval & 0xff;
     3706                        LogFlow(("Realmode: INT %x\n", pDis->Param1.parval & 0xff));
     3707                        intInfo2  = pDis->Param1.parval & 0xff;
    37083708                        intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
    37093709                        intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);

  • trunk/src/VBox/VMM/VMMR3/CSAM.cpp

    r41738 r41739  
    800800    {
    801801    case OP_INT:
    802         Assert(pCpu->param1.fUse & DISUSE_IMMEDIATE8);
    803         if (pCpu->param1.parval == 3)
     802        Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
     803        if (pCpu->Param1.parval == 3)
    804804        {
    805805            //two byte int 3
    … …  
    10971097                     * Any register is allowed as long as source and destination are identical.
    10981098                     */
    1099                     if (    cpu.param1.fUse != DISUSE_REG_GEN32
    1100                         ||  (   cpu.param2.flags != DISUSE_REG_GEN32
    1101                              && (   !(cpu.param2.flags & DISUSE_REG_GEN32)
    1102                                  || !(cpu.param2.flags & (DISUSE_DISPLACEMENT8|DISUSE_DISPLACEMENT16|DISUSE_DISPLACEMENT32))
    1103                                  ||  cpu.param2.parval != 0
     1099                    if (    cpu.Param1.fUse != DISUSE_REG_GEN32
     1100                        ||  (   cpu.Param2.flags != DISUSE_REG_GEN32
     1101                             && (   !(cpu.Param2.flags & DISUSE_REG_GEN32)
     1102                                 || !(cpu.Param2.flags & (DISUSE_DISPLACEMENT8|DISUSE_DISPLACEMENT16|DISUSE_DISPLACEMENT32))
     1103                                 ||  cpu.Param2.parval != 0
    11041104                                )
    11051105                            )
    1106                         ||  cpu.param1.base.reg_gen32 != cpu.param2.base.reg_gen32
     1106                        ||  cpu.Param1.base.reg_gen32 != cpu.Param2.base.reg_gen32
    11071107                       )
    11081108                    {
    … …  
    11151115                {
    11161116                    if (    (pCurInstrGC & 0x3) != 0
    1117                         ||  cpu.param1.fUse != DISUSE_REG_GEN32
    1118                         ||  cpu.param1.base.reg_gen32 != USE_REG_EBP
     1117                        ||  cpu.Param1.fUse != DISUSE_REG_GEN32
     1118                        ||  cpu.Param1.base.reg_gen32 != USE_REG_EBP
    11191119                       )
    11201120                    {
    … …  
    11411141                {
    11421142                    if (    (pCurInstrGC & 0x3) != 0
    1143                         ||  cpu.param1.fUse != DISUSE_REG_GEN32
    1144                         ||  cpu.param1.base.reg_gen32 != USE_REG_ESP
     1143                        ||  cpu.Param1.fUse != DISUSE_REG_GEN32
     1144                        ||  cpu.Param1.base.reg_gen32 != USE_REG_ESP
    11451145                       )
    11461146                    {
    … …  
    13281328        // For our first attempt, we'll handle only simple relative jumps and calls (immediate offset coded in instruction)
    13291329        if (    ((cpu.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->fParam1) == OP_PARM_J))
    1330             ||  (cpu.pCurInstr->uOpcode == OP_CALL && cpu.param1.fUse == DISUSE_DISPLACEMENT32))  /* simple indirect call (call dword ptr [address]) */
     1330            ||  (cpu.pCurInstr->uOpcode == OP_CALL && cpu.Param1.fUse == DISUSE_DISPLACEMENT32))  /* simple indirect call (call dword ptr [address]) */
    13311331        {
    13321332            /* We need to parse 'call dword ptr [address]' type of calls to catch cpuid instructions in some recent Linux distributions (e.g. OpenSuse 10.3) */
    13331333            if (    cpu.pCurInstr->uOpcode == OP_CALL
    1334                 &&  cpu.param1.fUse == DISUSE_DISPLACEMENT32)
     1334                &&  cpu.Param1.fUse == DISUSE_DISPLACEMENT32)
    13351335            {
    13361336                addr = 0;
    1337                 PGMPhysSimpleReadGCPtr(pVCpu, &addr, (RTRCUINTPTR)cpu.param1.uDisp.i32, sizeof(addr));
     1337                PGMPhysSimpleReadGCPtr(pVCpu, &addr, (RTRCUINTPTR)cpu.Param1.uDisp.i32, sizeof(addr));
    13381338            }
    13391339            else
    … …  
    13421342            if (addr == 0)
    13431343            {
    1344                 Log(("We don't support far jumps here!! (%08X)\n", cpu.param1.fUse));
     1344                Log(("We don't support far jumps here!! (%08X)\n", cpu.Param1.fUse));
    13451345                rc = VINF_SUCCESS;
    13461346                break;
    … …  
    13991399        else
    14001400        if (    cpu.pCurInstr->uOpcode == OP_JMP
    1401             &&  (cpu.param1.fUse & (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)) == (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)
     1401            &&  (cpu.Param1.fUse & (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)) == (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)
    14021402           )
    14031403        {
    1404             RTRCPTR  pJumpTableGC = (RTRCPTR)cpu.param1.disp32;
     1404            RTRCPTR  pJumpTableGC = (RTRCPTR)cpu.Param1.disp32;
    14051405            uint8_t *pJumpTableHC;
    14061406            int      rc2;
    … …  
    14151415                    uint64_t fFlags;
    14161416
    1417                     addr = pJumpTableGC + cpu.param1.scale * i;
     1417                    addr = pJumpTableGC + cpu.Param1.scale * i;
    14181418                    /* Same page? */
    14191419                    if (PAGE_ADDRESS(addr) != PAGE_ADDRESS(pJumpTableGC))
    14201420                        break;
    14211421
    1422                     addr = *(RTRCPTR *)(pJumpTableHC + cpu.param1.scale * i);
     1422                    addr = *(RTRCPTR *)(pJumpTableHC + cpu.Param1.scale * i);
    14231423
    14241424                    rc2 = PGMGstGetPage(pVCpu, addr, &fFlags, NULL);

  • trunk/src/VBox/VMM/VMMR3/EMRaw.cpp

    r41738 r41739  
    990990
    991991            case OP_MOV_CR:
    992                 if (Cpu.param1.fUse & DISUSE_REG_GEN32)
     992                if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
    993993                {
    994994                    //read
    995                     Assert(Cpu.param2.fUse & DISUSE_REG_CR);
    996                     Assert(Cpu.param2.base.reg_ctrl <= DISCREG_CR4);
    997                     STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
     995                    Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
     996                    Assert(Cpu.Param2.base.reg_ctrl <= DISCREG_CR4);
     997                    STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.base.reg_ctrl]);
    998998                }
    999999                else
    10001000                {
    10011001                    //write
    1002                     Assert(Cpu.param1.fUse & DISUSE_REG_CR);
    1003                     Assert(Cpu.param1.base.reg_ctrl <= DISCREG_CR4);
    1004                     STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
     1002                    Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
     1003                    Assert(Cpu.Param1.base.reg_ctrl <= DISCREG_CR4);
     1004                    STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.base.reg_ctrl]);
    10051005                }
    10061006                break;
    … …  
    11001100
    11011101                        if (    Cpu.pCurInstr->uOpcode == OP_MOV_CR
    1102                             &&  Cpu.param1.fUse == DISUSE_REG_CR /* write */
     1102                            &&  Cpu.Param1.fUse == DISUSE_REG_CR /* write */
    11031103                           )
    11041104                        {

  • trunk/src/VBox/VMM/VMMR3/HWACCM.cpp

    r41737 r41739  
    18331833        pPatch->cbOp     = cbOp;
    18341834
    1835         if (pDis->param1.fUse == DISUSE_DISPLACEMENT32)
     1835        if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
    18361836        {
    18371837            /* write. */
    1838             if (pDis->param2.fUse == DISUSE_REG_GEN32)
     1838            if (pDis->Param2.fUse == DISUSE_REG_GEN32)
    18391839            {
    18401840                pPatch->enmType     = HWACCMTPRINSTR_WRITE_REG;
    1841                 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
     1841                pPatch->uSrcOperand = pDis->Param2.base.reg_gen;
    18421842            }
    18431843            else
    18441844            {
    1845                 Assert(pDis->param2.fUse == DISUSE_IMMEDIATE32);
     1845                Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
    18461846                pPatch->enmType     = HWACCMTPRINSTR_WRITE_IMM;
    1847                 pPatch->uSrcOperand = pDis->param2.parval;
     1847                pPatch->uSrcOperand = pDis->Param2.parval;
    18481848            }
    18491849            rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
    … …  
    18571857            RTGCPTR  oldrip   = pCtx->rip;
    18581858            uint32_t oldcbOp  = cbOp;
    1859             uint32_t uMmioReg = pDis->param1.base.reg_gen;
     1859            uint32_t uMmioReg = pDis->Param1.base.reg_gen;
    18601860
    18611861            /* read */
    1862             Assert(pDis->param1.fUse == DISUSE_REG_GEN32);
     1862            Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
    18631863
    18641864            /* Found:
    … …  
    18721872            if (    rc == VINF_SUCCESS
    18731873                &&  pDis->pCurInstr->uOpcode == OP_SHR
    1874                 &&  pDis->param1.fUse == DISUSE_REG_GEN32
    1875                 &&  pDis->param1.base.reg_gen == uMmioReg
    1876                 &&  pDis->param2.fUse == DISUSE_IMMEDIATE8
    1877                 &&  pDis->param2.parval == 4
     1874                &&  pDis->Param1.fUse == DISUSE_REG_GEN32
     1875                &&  pDis->Param1.base.reg_gen == uMmioReg
     1876                &&  pDis->Param2.fUse == DISUSE_IMMEDIATE8
     1877                &&  pDis->Param2.parval == 4
    18781878                &&  oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
    18791879            {
    … …  
    18901890                szInstr[1] = 0x0F;
    18911891                szInstr[2] = 0x20;
    1892                 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
     1892                szInstr[3] = 0xC0 | pDis->Param1.base.reg_gen;
    18931893                for (unsigned i = 4; i < pPatch->cbOp; i++)
    18941894                    szInstr[i] = 0x90;  /* nop */
    … …  
    19061906            {
    19071907                pPatch->enmType     = HWACCMTPRINSTR_READ;
    1908                 pPatch->uDstOperand = pDis->param1.base.reg_gen;
     1908                pPatch->uDstOperand = pDis->Param1.base.reg_gen;
    19091909
    19101910                rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
    … …  
    20082008        pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
    20092009
    2010         if (pDis->param1.fUse == DISUSE_DISPLACEMENT32)
     2010        if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
    20112011        {
    20122012            /*
    … …  
    20282028                *
    20292029                */
    2030             bool fUsesEax = (pDis->param2.fUse == DISUSE_REG_GEN32 && pDis->param2.base.reg_gen == DISGREG_EAX);
     2030            bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.base.reg_gen == DISGREG_EAX);
    20312031
    20322032            aPatch[off++] = 0x51;    /* push ecx */
    … …  
    20362036            aPatch[off++] = 0x31;    /* xor edx, edx */
    20372037            aPatch[off++] = 0xD2;
    2038             if (pDis->param2.fUse == DISUSE_REG_GEN32)
     2038            if (pDis->Param2.fUse == DISUSE_REG_GEN32)
    20392039            {
    20402040                if (!fUsesEax)
    20412041                {
    20422042                    aPatch[off++] = 0x89;    /* mov eax, src_reg */
    2043                     aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, DISGREG_EAX);
     2043                    aPatch[off++] = MAKE_MODRM(3, pDis->Param2.base.reg_gen, DISGREG_EAX);
    20442044                }
    20452045            }
    20462046            else
    20472047            {
    2048                 Assert(pDis->param2.fUse == DISUSE_IMMEDIATE32);
     2048                Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
    20492049                aPatch[off++] = 0xB8;    /* mov eax, immediate */
    2050                 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
     2050                *(uint32_t *)&aPatch[off] = pDis->Param2.parval;
    20512051                off += sizeof(uint32_t);
    20522052            }
    … …  
    20792079                *
    20802080                */
    2081             Assert(pDis->param1.fUse == DISUSE_REG_GEN32);
    2082 
    2083             if (pDis->param1.base.reg_gen != DISGREG_ECX)
     2081            Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
     2082
     2083            if (pDis->Param1.base.reg_gen != DISGREG_ECX)
    20842084                aPatch[off++] = 0x51;    /* push ecx */
    2085             if (pDis->param1.base.reg_gen != DISGREG_EDX )
     2085            if (pDis->Param1.base.reg_gen != DISGREG_EDX )
    20862086                aPatch[off++] = 0x52;    /* push edx */
    2087             if (pDis->param1.base.reg_gen != DISGREG_EAX)
     2087            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
    20882088                aPatch[off++] = 0x50;    /* push eax */
    20892089
    … …  
    20982098            aPatch[off++] = 0x32;
    20992099
    2100             if (pDis->param1.base.reg_gen != DISGREG_EAX)
     2100            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
    21012101            {
    21022102                aPatch[off++] = 0x89;    /* mov dst_reg, eax */
    2103                 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->param1.base.reg_gen);
     2103                aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.base.reg_gen);
    21042104            }
    21052105
    2106             if (pDis->param1.base.reg_gen != DISGREG_EAX)
     2106            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
    21072107                aPatch[off++] = 0x58;    /* pop eax */
    2108             if (pDis->param1.base.reg_gen != DISGREG_EDX )
     2108            if (pDis->Param1.base.reg_gen != DISGREG_EDX )
    21092109                aPatch[off++] = 0x5A;    /* pop edx */
    2110             if (pDis->param1.base.reg_gen != DISGREG_ECX)
     2110            if (pDis->Param1.base.reg_gen != DISGREG_ECX)
    21112111                aPatch[off++] = 0x59;    /* pop ecx */
    21122112        }

  • trunk/src/VBox/VMM/VMMR3/PATM.cpp

    r41738 r41739  
    13991399           )
    14001400        {
    1401             Assert(pCpu->param1.cb <= 4 || pCpu->param1.cb == 6);
    1402             if (    pCpu->param1.cb == 6 /* far call/jmp */
     1401            Assert(pCpu->Param1.cb <= 4 || pCpu->Param1.cb == 6);
     1402            if (    pCpu->Param1.cb == 6 /* far call/jmp */
    14031403                ||  (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
    14041404                ||  (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
    … …  
    15581558           )
    15591559        {
    1560             Assert(pCpu->param1.cb <= 4 || pCpu->param1.cb == 6);
    1561             if (    pCpu->param1.cb == 6 /* far call/jmp */
     1560            Assert(pCpu->Param1.cb <= 4 || pCpu->Param1.cb == 6);
     1561            if (    pCpu->Param1.cb == 6 /* far call/jmp */
    15621562                ||  (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
    15631563                ||  (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
    … …  
    17011701        if (pTargetGC == 0)
    17021702        {
    1703             Log(("We don't support far jumps here!! (%08X)\n", pCpu->param1.fUse));
     1703            Log(("We don't support far jumps here!! (%08X)\n", pCpu->Param1.fUse));
    17041704            return VERR_PATCHING_REFUSED;
    17051705        }
    … …  
    17481748        {
    17491749            /* mov ss, src? */
    1750             if (    (pCpu->param1.fUse & DISUSE_REG_SEG)
    1751                 &&  (pCpu->param1.base.reg_seg == DISSELREG_SS))
     1750            if (    (pCpu->Param1.fUse & DISUSE_REG_SEG)
     1751                &&  (pCpu->Param1.base.reg_seg == DISSELREG_SS))
    17521752            {
    17531753                Log(("Force recompilation of next instruction for OP_MOV at %RRv\n", pCurInstrGC));
    … …  
    17571757#if 0 /* necessary for Haiku */
    17581758            else
    1759             if (    (pCpu->param2.fUse & DISUSE_REG_SEG)
    1760                 &&  (pCpu->param2.base.reg_seg == USE_REG_SS)
    1761                 &&  (pCpu->param1.fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN16)))     /** @todo memory operand must in theory be handled too */
     1759            if (    (pCpu->Param2.fUse & DISUSE_REG_SEG)
     1760                &&  (pCpu->Param2.base.reg_seg == USE_REG_SS)
     1761                &&  (pCpu->Param1.fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN16)))     /** @todo memory operand must in theory be handled too */
    17621762            {
    17631763                /* mov GPR, ss */
    … …  
    19451945         * In that case we'll jump to the original instruction and continue from there. Otherwise an int 3 is executed.
    19461946         */
    1947         Assert(pCpu->param1.cb == 4 || pCpu->param1.cb == 6);
    1948         if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu->param1.cb == 4 /* no far calls! */)
     1947        Assert(pCpu->Param1.cb == 4 || pCpu->Param1.cb == 6);
     1948        if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu->Param1.cb == 4 /* no far calls! */)
    19491949        {
    19501950            rc = patmPatchGenCall(pVM, pPatch, pCpu, pCurInstrGC, (RTRCPTR)0xDEADBEEF, true);
    … …  
    19621962         * In that case we'll jump to the original instruction and continue from there. Otherwise an int 3 is executed.
    19631963         */
    1964         Assert(pCpu->param1.cb == 4 || pCpu->param1.cb == 6);
    1965         if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu->param1.cb == 4 /* no far jumps! */)
     1964        Assert(pCpu->Param1.cb == 4 || pCpu->Param1.cb == 6);
     1965        if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu->Param1.cb == 4 /* no far jumps! */)
    19661966        {
    19671967            rc = patmPatchGenJump(pVM, pPatch, pCpu, pCurInstrGC);
    … …  
    21332133
    21342134            bool disret = patmR3DisInstr(pVM, pPatch, pOrgJumpGC, pOrgJumpHC, PATMREAD_ORGCODE, &cpu, NULL);
    2135             if (!disret || cpu.pCurInstr->uOpcode != OP_CALL || cpu.param1.cb != 4 /* only near calls */)
     2135            if (!disret || cpu.pCurInstr->uOpcode != OP_CALL || cpu.Param1.cb != 4 /* only near calls */)
    21362136                return VINF_SUCCESS;
    21372137        }
    … …  
    22422242            if (pTargetGC == 0)
    22432243            {
    2244                 Log(("We don't support far jumps here!! (%08X)\n", cpu.param1.fUse));
     2244                Log(("We don't support far jumps here!! (%08X)\n", cpu.Param1.fUse));
    22452245                rc = VERR_PATCHING_REFUSED;
    22462246                break;
    … …  
    24612461            if (addr == 0)
    24622462            {
    2463                 Log(("We don't support far jumps here!! (%08X)\n", cpu.param1.fUse));
     2463                Log(("We don't support far jumps here!! (%08X)\n", cpu.Param1.fUse));
    24642464                rc = VERR_PATCHING_REFUSED;
    24652465                break;
    … …  
    35813581    if (pTargetGC == 0)
    35823582    {
    3583         Log(("We don't support far jumps here!! (%08X)\n", pCpu->param1.fUse));
     3583        Log(("We don't support far jumps here!! (%08X)\n", pCpu->Param1.fUse));
    35843584        rc = VERR_PATCHING_REFUSED;
    35853585        goto failure;
    … …  
    36733673        goto failure;
    36743674
    3675     if (pCpu->param2.fUse != DISUSE_DISPLACEMENT32)
     3675    if (pCpu->Param2.fUse != DISUSE_DISPLACEMENT32)
    36763676        goto failure;
    36773677
    … …  
    37523752    if (cbInstr > MAX_INSTR_SIZE)
    37533753        return VERR_PATCHING_REFUSED;
    3754     if (cpu.param2.fUse != DISUSE_DISPLACEMENT32)
     3754    if (cpu.Param2.fUse != DISUSE_DISPLACEMENT32)
    37553755        return VERR_PATCHING_REFUSED;
    37563756
    … …  
    39143914    case OP_JMP:
    39153915        Assert(pPatch->flags & PATMFL_JUMP_CONFLICT);
    3916         Assert(pCpu->param1.fUse & DISUSE_IMMEDIATE32_REL);
    3917         if (!(pCpu->param1.fUse & DISUSE_IMMEDIATE32_REL))
     3916        Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL);
     3917        if (!(pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL))
    39183918            goto failure;
    39193919
    … …  
    39493949     * references the target instruction in the conflict patch.
    39503950     */
    3951     RTRCPTR pJmpDest = PATMR3GuestGCPtrToPatchGCPtr(pVM, pInstrGC + pCpu->cbInstr + (int32_t)pCpu->param1.parval);
    3952 
    3953     AssertMsg(pJmpDest, ("PATMR3GuestGCPtrToPatchGCPtr failed for %RRv\n", pInstrGC + pCpu->cbInstr + (int32_t)pCpu->param1.parval));
     3951    RTRCPTR pJmpDest = PATMR3GuestGCPtrToPatchGCPtr(pVM, pInstrGC + pCpu->cbInstr + (int32_t)pCpu->Param1.parval);
     3952
     3953    AssertMsg(pJmpDest, ("PATMR3GuestGCPtrToPatchGCPtr failed for %RRv\n", pInstrGC + pCpu->cbInstr + (int32_t)pCpu->Param1.parval));
    39543954    pPatch->pPatchJumpDestGC = pJmpDest;
    39553955
    … …  
    51995199        && (pConflictPatch->flags & PATMFL_CODE32)
    52005200        && (cpu.pCurInstr->uOpcode == OP_JMP || (cpu.pCurInstr->fOpType & DISOPTYPE_COND_CONTROLFLOW))
    5201         && (cpu.param1.fUse & DISUSE_IMMEDIATE32_REL))
     5201        && (cpu.Param1.fUse & DISUSE_IMMEDIATE32_REL))
    52025202    {
    52035203        /* Hint patches must be enabled first. */

  • trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp

    r41738 r41739  
    694694    {
    695695        Log(("patmPatchGenIndirectCall\n"));
    696         Assert(pCpu->param1.cb == 4);
     696        Assert(pCpu->Param1.cb == 4);
    697697        Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J);
    698698
    … …  
    790790
    791791    Log(("patmPatchGenIndirectJump\n"));
    792     Assert(pCpu->param1.cb == 4);
     792    Assert(pCpu->Param1.cb == 4);
    793793    Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J);
    794794
    … …  
    857857    /** @note optimization: multiple identical ret instruction in a single patch can share a single patched ret. */
    858858    if (    pPatch->pTempInfo->pPatchRetInstrGC
    859         &&  pPatch->pTempInfo->uPatchRetParam1 == (uint32_t)pCpu->param1.parval) /* nr of bytes popped off the stack should be identical of course! */
     859        &&  pPatch->pTempInfo->uPatchRetParam1 == (uint32_t)pCpu->Param1.parval) /* nr of bytes popped off the stack should be identical of course! */
    860860    {
    861861        Assert(pCpu->pCurInstr->uOpcode == OP_RETN);
    … …  
    891891    {
    892892        pPatch->pTempInfo->pPatchRetInstrGC = pPatchRetInstrGC;
    893         pPatch->pTempInfo->uPatchRetParam1  = pCpu->param1.parval;
     893        pPatch->pTempInfo->uPatchRetParam1  = pCpu->Param1.parval;
    894894    }
    895895    return rc;
    … …  
    11641164        // mov DRx, GPR
    11651165        pPB[0] = 0x89;      //mov disp32, GPR
    1166         Assert(pCpu->param1.fUse & DISUSE_REG_DBG);
    1167         Assert(pCpu->param2.fUse & DISUSE_REG_GEN32);
    1168 
    1169         dbgreg = pCpu->param1.base.reg_dbg;
    1170         reg    = pCpu->param2.base.reg_gen;
     1166        Assert(pCpu->Param1.fUse & DISUSE_REG_DBG);
     1167        Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32);
     1168
     1169        dbgreg = pCpu->Param1.base.reg_dbg;
     1170        reg    = pCpu->Param2.base.reg_gen;
    11711171    }
    11721172    else
    11731173    {
    11741174        // mov GPR, DRx
    1175         Assert(pCpu->param1.fUse & DISUSE_REG_GEN32);
    1176         Assert(pCpu->param2.fUse & DISUSE_REG_DBG);
     1175        Assert(pCpu->Param1.fUse & DISUSE_REG_GEN32);
     1176        Assert(pCpu->Param2.fUse & DISUSE_REG_DBG);
    11771177
    11781178        pPB[0] = 0x8B;      // mov GPR, disp32
    1179         reg    = pCpu->param1.base.reg_gen;
    1180         dbgreg = pCpu->param2.base.reg_dbg;
     1179        reg    = pCpu->Param1.base.reg_gen;
     1180        dbgreg = pCpu->Param2.base.reg_dbg;
    11811181    }
    11821182
    … …  
    12141214        // mov CRx, GPR
    12151215        pPB[0] = 0x89;      //mov disp32, GPR
    1216         ctrlreg = pCpu->param1.base.reg_ctrl;
    1217         reg     = pCpu->param2.base.reg_gen;
    1218         Assert(pCpu->param1.fUse & DISUSE_REG_CR);
    1219         Assert(pCpu->param2.fUse & DISUSE_REG_GEN32);
     1216        ctrlreg = pCpu->Param1.base.reg_ctrl;
     1217        reg     = pCpu->Param2.base.reg_gen;
     1218        Assert(pCpu->Param1.fUse & DISUSE_REG_CR);
     1219        Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32);
    12201220    }
    12211221    else
    12221222    {
    12231223        // mov GPR, DRx
    1224         Assert(pCpu->param1.fUse & DISUSE_REG_GEN32);
    1225         Assert(pCpu->param2.fUse & DISUSE_REG_CR);
     1224        Assert(pCpu->Param1.fUse & DISUSE_REG_GEN32);
     1225        Assert(pCpu->Param2.fUse & DISUSE_REG_CR);
    12261226
    12271227        pPB[0]  = 0x8B;      // mov GPR, disp32
    1228         reg     = pCpu->param1.base.reg_gen;
    1229         ctrlreg = pCpu->param2.base.reg_ctrl;
     1228        reg     = pCpu->Param1.base.reg_gen;
     1229        ctrlreg = pCpu->Param2.base.reg_ctrl;
    12301230    }
    12311231
    … …  
    12921292    if (pCpu->fPrefix & DISPREFIX_OPSIZE)
    12931293        pPB[offset++] = 0x66; /* size override -> 16 bits pop */
    1294     pPB[offset++] = 0x58 + pCpu->param1.base.reg_gen;
     1294    pPB[offset++] = 0x58 + pCpu->Param1.base.reg_gen;
    12951295    PATCHGEN_EPILOG(pPatch, offset);
    12961296
    … …  
    13251325    PATCHGEN_PROLOG(pVM, pPatch);
    13261326
    1327     if (pCpu->param1.fUse == DISUSE_REG_GEN32 || pCpu->param1.fUse == DISUSE_REG_GEN16)
     1327    if (pCpu->Param1.fUse == DISUSE_REG_GEN32 || pCpu->Param1.fUse == DISUSE_REG_GEN16)
    13281328    {
    13291329        /* Register operand */
    … …  
    13351335        pPB[offset++] = 0x8B;              // mov       destreg, CPUMCTX.tr/ldtr
    13361336        /* Modify REG part according to destination of original instruction */
    1337         pPB[offset++] = MAKE_MODRM(0, pCpu->param1.base.reg_gen, 5);
     1337        pPB[offset++] = MAKE_MODRM(0, pCpu->Param1.base.reg_gen, 5);
    13381338        if (pCpu->pCurInstr->uOpcode == OP_STR)
    13391339        {

  • trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp

    r41738 r41739  
    738738             * Little hack to make the code below not fail
    739739             */
    740             pCpu->param1.fUse  = DISUSE_IMMEDIATE8;
    741             pCpu->param1.parval = 3;
     740            pCpu->Param1.fUse  = DISUSE_IMMEDIATE8;
     741            pCpu->Param1.parval = 3;
    742742            /* fallthru */
    743743        case OP_INT:
    744744        {
    745             Assert(pCpu->param1.fUse & DISUSE_IMMEDIATE8);
     745            Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
    746746            Assert(!(PATMIsPatchGCAddr(pVM, PC)));
    747             if (pCpu->param1.parval == 3)
     747            if (pCpu->Param1.parval == 3)
    748748            {
    749749                /* Int 3 replacement patch? */
    … …  
    754754                }
    755755            }
    756             rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
     756            rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.parval, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
    757757            if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
    758758                return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);
    … …  
    840840             * Little hack to make the code below not fail
    841841             */
    842             pCpu->param1.fUse  = DISUSE_IMMEDIATE8;
    843             pCpu->param1.parval = 3;
     842            pCpu->Param1.fUse  = DISUSE_IMMEDIATE8;
     843            pCpu->Param1.parval = 3;
    844844            /* fall thru */
    845845        case OP_INT:
    846846        {
    847             Assert(pCpu->param1.fUse & DISUSE_IMMEDIATE8);
    848             rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->param1.parval, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
     847            Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8);
     848            rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.parval, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd);
    849849            if (RT_SUCCESS(rc) && rc != VINF_EM_RAW_GUEST_TRAP)
    850850                return trpmGCExitTrap(pVM, pVCpu, VINF_SUCCESS, pRegFrame);

  • trunk/src/VBox/VMM/include/CSAMInternal.h

    r41732 r41739  
    251251{
    252252    uint32_t disp;
    253     if (pCpu->param1.fUse & DISUSE_IMMEDIATE8_REL)
    254     {
    255         disp = (int32_t)(char)pCpu->param1.parval;
     253    if (pCpu->Param1.fUse & DISUSE_IMMEDIATE8_REL)
     254    {
     255        disp = (int32_t)(char)pCpu->Param1.parval;
    256256    }
    257257    else
    258     if (pCpu->param1.fUse & DISUSE_IMMEDIATE16_REL)
    259     {
    260         disp = (int32_t)(uint16_t)pCpu->param1.parval;
     258    if (pCpu->Param1.fUse & DISUSE_IMMEDIATE16_REL)
     259    {
     260        disp = (int32_t)(uint16_t)pCpu->Param1.parval;
    261261    }
    262262    else
    263     if (pCpu->param1.fUse & DISUSE_IMMEDIATE32_REL)
    264     {
    265         disp = (int32_t)pCpu->param1.parval;
     263    if (pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL)
     264    {
     265        disp = (int32_t)pCpu->Param1.parval;
    266266    }
    267267    else
    268268    {
    269         Log(("We don't support far jumps here!! (%08X)\n", pCpu->param1.fUse));
     269        Log(("We don't support far jumps here!! (%08X)\n", pCpu->Param1.fUse));
    270270        return 0;
    271271    }

  • trunk/src/VBox/VMM/include/PATMInternal.h

    r41732 r41739  
    761761{
    762762    uint32_t disp;
    763     if (pCpu->param1.fUse & DISUSE_IMMEDIATE8_REL)
     763    if (pCpu->Param1.fUse & DISUSE_IMMEDIATE8_REL)
    764764    {
    765         disp = (int32_t)(char)pCpu->param1.parval;
     765        disp = (int32_t)(char)pCpu->Param1.parval;
    766766    }
    767767    else
    768     if (pCpu->param1.fUse & DISUSE_IMMEDIATE16_REL)
     768    if (pCpu->Param1.fUse & DISUSE_IMMEDIATE16_REL)
    769769    {
    770         disp = (int32_t)(uint16_t)pCpu->param1.parval;
     770        disp = (int32_t)(uint16_t)pCpu->Param1.parval;
    771771    }
    772772    else
    773     if (pCpu->param1.fUse & DISUSE_IMMEDIATE32_REL)
     773    if (pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL)
    774774    {
    775         disp = (int32_t)pCpu->param1.parval;
     775        disp = (int32_t)pCpu->Param1.parval;
    776776    }
    777777    else
    778778    {
    779         Log(("We don't support far jumps here!! (%08X)\n", pCpu->param1.fUse));
     779        Log(("We don't support far jumps here!! (%08X)\n", pCpu->Param1.fUse));
    780780        return 0;
    781781    }

  • trunk/src/VBox/VMM/testcase/tstVMStruct.h

    r41732 r41739  
    13981398#ifndef VBOX_FOR_DTRACE_LIB
    13991399    GEN_CHECK_SIZE(DISCPUSTATE);
    1400     GEN_CHECK_OFF(DISCPUSTATE, param1);
    1401     GEN_CHECK_OFF(DISCPUSTATE, param2);
    1402     GEN_CHECK_OFF(DISCPUSTATE, param3);
     1400    GEN_CHECK_OFF(DISCPUSTATE, Param1);
     1401    GEN_CHECK_OFF(DISCPUSTATE, Param2);
     1402    GEN_CHECK_OFF(DISCPUSTATE, Param3);
    14031403    GEN_CHECK_OFF(DISCPUSTATE, i32SibDisp);
    14041404    GEN_CHECK_OFF(DISCPUSTATE, fFilter);
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