Changeset 41739 in vbox for trunk/src/VBox/VMM/VMMR3
- Timestamp:
- Jun 15, 2012 1:31:29 AM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 78547
- Location:
- trunk/src/VBox/VMM/VMMR3
- Files:
-
- 5 edited
-
CSAM.cpp (modified) (8 diffs)
-
EMRaw.cpp (modified) (2 diffs)
-
HWACCM.cpp (modified) (10 diffs)
-
PATM.cpp (modified) (16 diffs)
-
PATMPatch.cpp (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/CSAM.cpp
r41738 r41739 800 800 { 801 801 case OP_INT: 802 Assert(pCpu-> param1.fUse & DISUSE_IMMEDIATE8);803 if (pCpu-> param1.parval == 3)802 Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8); 803 if (pCpu->Param1.parval == 3) 804 804 { 805 805 //two byte int 3 … … 1097 1097 * Any register is allowed as long as source and destination are identical. 1098 1098 */ 1099 if ( cpu. param1.fUse != DISUSE_REG_GEN321100 || ( cpu. param2.flags != DISUSE_REG_GEN321101 && ( !(cpu. param2.flags & DISUSE_REG_GEN32)1102 || !(cpu. param2.flags & (DISUSE_DISPLACEMENT8|DISUSE_DISPLACEMENT16|DISUSE_DISPLACEMENT32))1103 || cpu. param2.parval != 01099 if ( cpu.Param1.fUse != DISUSE_REG_GEN32 1100 || ( cpu.Param2.flags != DISUSE_REG_GEN32 1101 && ( !(cpu.Param2.flags & DISUSE_REG_GEN32) 1102 || !(cpu.Param2.flags & (DISUSE_DISPLACEMENT8|DISUSE_DISPLACEMENT16|DISUSE_DISPLACEMENT32)) 1103 || cpu.Param2.parval != 0 1104 1104 ) 1105 1105 ) 1106 || cpu. param1.base.reg_gen32 != cpu.param2.base.reg_gen321106 || cpu.Param1.base.reg_gen32 != cpu.Param2.base.reg_gen32 1107 1107 ) 1108 1108 { … … 1115 1115 { 1116 1116 if ( (pCurInstrGC & 0x3) != 0 1117 || cpu. param1.fUse != DISUSE_REG_GEN321118 || cpu. param1.base.reg_gen32 != USE_REG_EBP1117 || cpu.Param1.fUse != DISUSE_REG_GEN32 1118 || cpu.Param1.base.reg_gen32 != USE_REG_EBP 1119 1119 ) 1120 1120 { … … 1141 1141 { 1142 1142 if ( (pCurInstrGC & 0x3) != 0 1143 || cpu. param1.fUse != DISUSE_REG_GEN321144 || cpu. param1.base.reg_gen32 != USE_REG_ESP1143 || cpu.Param1.fUse != DISUSE_REG_GEN32 1144 || cpu.Param1.base.reg_gen32 != USE_REG_ESP 1145 1145 ) 1146 1146 { … … 1328 1328 // For our first attempt, we'll handle only simple relative jumps and calls (immediate offset coded in instruction) 1329 1329 if ( ((cpu.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->fParam1) == OP_PARM_J)) 1330 || (cpu.pCurInstr->uOpcode == OP_CALL && cpu. param1.fUse == DISUSE_DISPLACEMENT32)) /* simple indirect call (call dword ptr [address]) */1330 || (cpu.pCurInstr->uOpcode == OP_CALL && cpu.Param1.fUse == DISUSE_DISPLACEMENT32)) /* simple indirect call (call dword ptr [address]) */ 1331 1331 { 1332 1332 /* We need to parse 'call dword ptr [address]' type of calls to catch cpuid instructions in some recent Linux distributions (e.g. OpenSuse 10.3) */ 1333 1333 if ( cpu.pCurInstr->uOpcode == OP_CALL 1334 && cpu. param1.fUse == DISUSE_DISPLACEMENT32)1334 && cpu.Param1.fUse == DISUSE_DISPLACEMENT32) 1335 1335 { 1336 1336 addr = 0; 1337 PGMPhysSimpleReadGCPtr(pVCpu, &addr, (RTRCUINTPTR)cpu. param1.uDisp.i32, sizeof(addr));1337 PGMPhysSimpleReadGCPtr(pVCpu, &addr, (RTRCUINTPTR)cpu.Param1.uDisp.i32, sizeof(addr)); 1338 1338 } 1339 1339 else … … 1342 1342 if (addr == 0) 1343 1343 { 1344 Log(("We don't support far jumps here!! (%08X)\n", cpu. param1.fUse));1344 Log(("We don't support far jumps here!! (%08X)\n", cpu.Param1.fUse)); 1345 1345 rc = VINF_SUCCESS; 1346 1346 break; … … 1399 1399 else 1400 1400 if ( cpu.pCurInstr->uOpcode == OP_JMP 1401 && (cpu. param1.fUse & (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)) == (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)1401 && (cpu.Param1.fUse & (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)) == (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE) 1402 1402 ) 1403 1403 { 1404 RTRCPTR pJumpTableGC = (RTRCPTR)cpu. param1.disp32;1404 RTRCPTR pJumpTableGC = (RTRCPTR)cpu.Param1.disp32; 1405 1405 uint8_t *pJumpTableHC; 1406 1406 int rc2; … … 1415 1415 uint64_t fFlags; 1416 1416 1417 addr = pJumpTableGC + cpu. param1.scale * i;1417 addr = pJumpTableGC + cpu.Param1.scale * i; 1418 1418 /* Same page? */ 1419 1419 if (PAGE_ADDRESS(addr) != PAGE_ADDRESS(pJumpTableGC)) 1420 1420 break; 1421 1421 1422 addr = *(RTRCPTR *)(pJumpTableHC + cpu. param1.scale * i);1422 addr = *(RTRCPTR *)(pJumpTableHC + cpu.Param1.scale * i); 1423 1423 1424 1424 rc2 = PGMGstGetPage(pVCpu, addr, &fFlags, NULL); -
trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
r41738 r41739 990 990 991 991 case OP_MOV_CR: 992 if (Cpu. param1.fUse & DISUSE_REG_GEN32)992 if (Cpu.Param1.fUse & DISUSE_REG_GEN32) 993 993 { 994 994 //read 995 Assert(Cpu. param2.fUse & DISUSE_REG_CR);996 Assert(Cpu. param2.base.reg_ctrl <= DISCREG_CR4);997 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu. param2.base.reg_ctrl]);995 Assert(Cpu.Param2.fUse & DISUSE_REG_CR); 996 Assert(Cpu.Param2.base.reg_ctrl <= DISCREG_CR4); 997 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.base.reg_ctrl]); 998 998 } 999 999 else 1000 1000 { 1001 1001 //write 1002 Assert(Cpu. param1.fUse & DISUSE_REG_CR);1003 Assert(Cpu. param1.base.reg_ctrl <= DISCREG_CR4);1004 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu. param1.base.reg_ctrl]);1002 Assert(Cpu.Param1.fUse & DISUSE_REG_CR); 1003 Assert(Cpu.Param1.base.reg_ctrl <= DISCREG_CR4); 1004 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.base.reg_ctrl]); 1005 1005 } 1006 1006 break; … … 1100 1100 1101 1101 if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR 1102 && Cpu. param1.fUse == DISUSE_REG_CR /* write */1102 && Cpu.Param1.fUse == DISUSE_REG_CR /* write */ 1103 1103 ) 1104 1104 { -
trunk/src/VBox/VMM/VMMR3/HWACCM.cpp
r41737 r41739 1833 1833 pPatch->cbOp = cbOp; 1834 1834 1835 if (pDis-> param1.fUse == DISUSE_DISPLACEMENT32)1835 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32) 1836 1836 { 1837 1837 /* write. */ 1838 if (pDis-> param2.fUse == DISUSE_REG_GEN32)1838 if (pDis->Param2.fUse == DISUSE_REG_GEN32) 1839 1839 { 1840 1840 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG; 1841 pPatch->uSrcOperand = pDis-> param2.base.reg_gen;1841 pPatch->uSrcOperand = pDis->Param2.base.reg_gen; 1842 1842 } 1843 1843 else 1844 1844 { 1845 Assert(pDis-> param2.fUse == DISUSE_IMMEDIATE32);1845 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32); 1846 1846 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM; 1847 pPatch->uSrcOperand = pDis-> param2.parval;1847 pPatch->uSrcOperand = pDis->Param2.parval; 1848 1848 } 1849 1849 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall)); … … 1857 1857 RTGCPTR oldrip = pCtx->rip; 1858 1858 uint32_t oldcbOp = cbOp; 1859 uint32_t uMmioReg = pDis-> param1.base.reg_gen;1859 uint32_t uMmioReg = pDis->Param1.base.reg_gen; 1860 1860 1861 1861 /* read */ 1862 Assert(pDis-> param1.fUse == DISUSE_REG_GEN32);1862 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32); 1863 1863 1864 1864 /* Found: … … 1872 1872 if ( rc == VINF_SUCCESS 1873 1873 && pDis->pCurInstr->uOpcode == OP_SHR 1874 && pDis-> param1.fUse == DISUSE_REG_GEN321875 && pDis-> param1.base.reg_gen == uMmioReg1876 && pDis-> param2.fUse == DISUSE_IMMEDIATE81877 && pDis-> param2.parval == 41874 && pDis->Param1.fUse == DISUSE_REG_GEN32 1875 && pDis->Param1.base.reg_gen == uMmioReg 1876 && pDis->Param2.fUse == DISUSE_IMMEDIATE8 1877 && pDis->Param2.parval == 4 1878 1878 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode)) 1879 1879 { … … 1890 1890 szInstr[1] = 0x0F; 1891 1891 szInstr[2] = 0x20; 1892 szInstr[3] = 0xC0 | pDis-> param1.base.reg_gen;1892 szInstr[3] = 0xC0 | pDis->Param1.base.reg_gen; 1893 1893 for (unsigned i = 4; i < pPatch->cbOp; i++) 1894 1894 szInstr[i] = 0x90; /* nop */ … … 1906 1906 { 1907 1907 pPatch->enmType = HWACCMTPRINSTR_READ; 1908 pPatch->uDstOperand = pDis-> param1.base.reg_gen;1908 pPatch->uDstOperand = pDis->Param1.base.reg_gen; 1909 1909 1910 1910 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall)); … … 2008 2008 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT; 2009 2009 2010 if (pDis-> param1.fUse == DISUSE_DISPLACEMENT32)2010 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32) 2011 2011 { 2012 2012 /* … … 2028 2028 * 2029 2029 */ 2030 bool fUsesEax = (pDis-> param2.fUse == DISUSE_REG_GEN32 && pDis->param2.base.reg_gen == DISGREG_EAX);2030 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.base.reg_gen == DISGREG_EAX); 2031 2031 2032 2032 aPatch[off++] = 0x51; /* push ecx */ … … 2036 2036 aPatch[off++] = 0x31; /* xor edx, edx */ 2037 2037 aPatch[off++] = 0xD2; 2038 if (pDis-> param2.fUse == DISUSE_REG_GEN32)2038 if (pDis->Param2.fUse == DISUSE_REG_GEN32) 2039 2039 { 2040 2040 if (!fUsesEax) 2041 2041 { 2042 2042 aPatch[off++] = 0x89; /* mov eax, src_reg */ 2043 aPatch[off++] = MAKE_MODRM(3, pDis-> param2.base.reg_gen, DISGREG_EAX);2043 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.base.reg_gen, DISGREG_EAX); 2044 2044 } 2045 2045 } 2046 2046 else 2047 2047 { 2048 Assert(pDis-> param2.fUse == DISUSE_IMMEDIATE32);2048 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32); 2049 2049 aPatch[off++] = 0xB8; /* mov eax, immediate */ 2050 *(uint32_t *)&aPatch[off] = pDis-> param2.parval;2050 *(uint32_t *)&aPatch[off] = pDis->Param2.parval; 2051 2051 off += sizeof(uint32_t); 2052 2052 } … … 2079 2079 * 2080 2080 */ 2081 Assert(pDis-> param1.fUse == DISUSE_REG_GEN32);2082 2083 if (pDis-> param1.base.reg_gen != DISGREG_ECX)2081 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32); 2082 2083 if (pDis->Param1.base.reg_gen != DISGREG_ECX) 2084 2084 aPatch[off++] = 0x51; /* push ecx */ 2085 if (pDis-> param1.base.reg_gen != DISGREG_EDX )2085 if (pDis->Param1.base.reg_gen != DISGREG_EDX ) 2086 2086 aPatch[off++] = 0x52; /* push edx */ 2087 if (pDis-> param1.base.reg_gen != DISGREG_EAX)2087 if (pDis->Param1.base.reg_gen != DISGREG_EAX) 2088 2088 aPatch[off++] = 0x50; /* push eax */ 2089 2089 … … 2098 2098 aPatch[off++] = 0x32; 2099 2099 2100 if (pDis-> param1.base.reg_gen != DISGREG_EAX)2100 if (pDis->Param1.base.reg_gen != DISGREG_EAX) 2101 2101 { 2102 2102 aPatch[off++] = 0x89; /* mov dst_reg, eax */ 2103 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis-> param1.base.reg_gen);2103 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.base.reg_gen); 2104 2104 } 2105 2105 2106 if (pDis-> param1.base.reg_gen != DISGREG_EAX)2106 if (pDis->Param1.base.reg_gen != DISGREG_EAX) 2107 2107 aPatch[off++] = 0x58; /* pop eax */ 2108 if (pDis-> param1.base.reg_gen != DISGREG_EDX )2108 if (pDis->Param1.base.reg_gen != DISGREG_EDX ) 2109 2109 aPatch[off++] = 0x5A; /* pop edx */ 2110 if (pDis-> param1.base.reg_gen != DISGREG_ECX)2110 if (pDis->Param1.base.reg_gen != DISGREG_ECX) 2111 2111 aPatch[off++] = 0x59; /* pop ecx */ 2112 2112 } -
trunk/src/VBox/VMM/VMMR3/PATM.cpp
r41738 r41739 1399 1399 ) 1400 1400 { 1401 Assert(pCpu-> param1.cb <= 4 || pCpu->param1.cb == 6);1402 if ( pCpu-> param1.cb == 6 /* far call/jmp */1401 Assert(pCpu->Param1.cb <= 4 || pCpu->Param1.cb == 6); 1402 if ( pCpu->Param1.cb == 6 /* far call/jmp */ 1403 1403 || (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS)) 1404 1404 || (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS)) … … 1558 1558 ) 1559 1559 { 1560 Assert(pCpu-> param1.cb <= 4 || pCpu->param1.cb == 6);1561 if ( pCpu-> param1.cb == 6 /* far call/jmp */1560 Assert(pCpu->Param1.cb <= 4 || pCpu->Param1.cb == 6); 1561 if ( pCpu->Param1.cb == 6 /* far call/jmp */ 1562 1562 || (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS)) 1563 1563 || (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS)) … … 1701 1701 if (pTargetGC == 0) 1702 1702 { 1703 Log(("We don't support far jumps here!! (%08X)\n", pCpu-> param1.fUse));1703 Log(("We don't support far jumps here!! (%08X)\n", pCpu->Param1.fUse)); 1704 1704 return VERR_PATCHING_REFUSED; 1705 1705 } … … 1748 1748 { 1749 1749 /* mov ss, src? */ 1750 if ( (pCpu-> param1.fUse & DISUSE_REG_SEG)1751 && (pCpu-> param1.base.reg_seg == DISSELREG_SS))1750 if ( (pCpu->Param1.fUse & DISUSE_REG_SEG) 1751 && (pCpu->Param1.base.reg_seg == DISSELREG_SS)) 1752 1752 { 1753 1753 Log(("Force recompilation of next instruction for OP_MOV at %RRv\n", pCurInstrGC)); … … 1757 1757 #if 0 /* necessary for Haiku */ 1758 1758 else 1759 if ( (pCpu-> param2.fUse & DISUSE_REG_SEG)1760 && (pCpu-> param2.base.reg_seg == USE_REG_SS)1761 && (pCpu-> param1.fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN16))) /** @todo memory operand must in theory be handled too */1759 if ( (pCpu->Param2.fUse & DISUSE_REG_SEG) 1760 && (pCpu->Param2.base.reg_seg == USE_REG_SS) 1761 && (pCpu->Param1.fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN16))) /** @todo memory operand must in theory be handled too */ 1762 1762 { 1763 1763 /* mov GPR, ss */ … … 1945 1945 * In that case we'll jump to the original instruction and continue from there. Otherwise an int 3 is executed. 1946 1946 */ 1947 Assert(pCpu-> param1.cb == 4 || pCpu->param1.cb == 6);1948 if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu-> param1.cb == 4 /* no far calls! */)1947 Assert(pCpu->Param1.cb == 4 || pCpu->Param1.cb == 6); 1948 if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu->Param1.cb == 4 /* no far calls! */) 1949 1949 { 1950 1950 rc = patmPatchGenCall(pVM, pPatch, pCpu, pCurInstrGC, (RTRCPTR)0xDEADBEEF, true); … … 1962 1962 * In that case we'll jump to the original instruction and continue from there. Otherwise an int 3 is executed. 1963 1963 */ 1964 Assert(pCpu-> param1.cb == 4 || pCpu->param1.cb == 6);1965 if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu-> param1.cb == 4 /* no far jumps! */)1964 Assert(pCpu->Param1.cb == 4 || pCpu->Param1.cb == 6); 1965 if (pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS && pCpu->Param1.cb == 4 /* no far jumps! */) 1966 1966 { 1967 1967 rc = patmPatchGenJump(pVM, pPatch, pCpu, pCurInstrGC); … … 2133 2133 2134 2134 bool disret = patmR3DisInstr(pVM, pPatch, pOrgJumpGC, pOrgJumpHC, PATMREAD_ORGCODE, &cpu, NULL); 2135 if (!disret || cpu.pCurInstr->uOpcode != OP_CALL || cpu. param1.cb != 4 /* only near calls */)2135 if (!disret || cpu.pCurInstr->uOpcode != OP_CALL || cpu.Param1.cb != 4 /* only near calls */) 2136 2136 return VINF_SUCCESS; 2137 2137 } … … 2242 2242 if (pTargetGC == 0) 2243 2243 { 2244 Log(("We don't support far jumps here!! (%08X)\n", cpu. param1.fUse));2244 Log(("We don't support far jumps here!! (%08X)\n", cpu.Param1.fUse)); 2245 2245 rc = VERR_PATCHING_REFUSED; 2246 2246 break; … … 2461 2461 if (addr == 0) 2462 2462 { 2463 Log(("We don't support far jumps here!! (%08X)\n", cpu. param1.fUse));2463 Log(("We don't support far jumps here!! (%08X)\n", cpu.Param1.fUse)); 2464 2464 rc = VERR_PATCHING_REFUSED; 2465 2465 break; … … 3581 3581 if (pTargetGC == 0) 3582 3582 { 3583 Log(("We don't support far jumps here!! (%08X)\n", pCpu-> param1.fUse));3583 Log(("We don't support far jumps here!! (%08X)\n", pCpu->Param1.fUse)); 3584 3584 rc = VERR_PATCHING_REFUSED; 3585 3585 goto failure; … … 3673 3673 goto failure; 3674 3674 3675 if (pCpu-> param2.fUse != DISUSE_DISPLACEMENT32)3675 if (pCpu->Param2.fUse != DISUSE_DISPLACEMENT32) 3676 3676 goto failure; 3677 3677 … … 3752 3752 if (cbInstr > MAX_INSTR_SIZE) 3753 3753 return VERR_PATCHING_REFUSED; 3754 if (cpu. param2.fUse != DISUSE_DISPLACEMENT32)3754 if (cpu.Param2.fUse != DISUSE_DISPLACEMENT32) 3755 3755 return VERR_PATCHING_REFUSED; 3756 3756 … … 3914 3914 case OP_JMP: 3915 3915 Assert(pPatch->flags & PATMFL_JUMP_CONFLICT); 3916 Assert(pCpu-> param1.fUse & DISUSE_IMMEDIATE32_REL);3917 if (!(pCpu-> param1.fUse & DISUSE_IMMEDIATE32_REL))3916 Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL); 3917 if (!(pCpu->Param1.fUse & DISUSE_IMMEDIATE32_REL)) 3918 3918 goto failure; 3919 3919 … … 3949 3949 * references the target instruction in the conflict patch. 3950 3950 */ 3951 RTRCPTR pJmpDest = PATMR3GuestGCPtrToPatchGCPtr(pVM, pInstrGC + pCpu->cbInstr + (int32_t)pCpu-> param1.parval);3952 3953 AssertMsg(pJmpDest, ("PATMR3GuestGCPtrToPatchGCPtr failed for %RRv\n", pInstrGC + pCpu->cbInstr + (int32_t)pCpu-> param1.parval));3951 RTRCPTR pJmpDest = PATMR3GuestGCPtrToPatchGCPtr(pVM, pInstrGC + pCpu->cbInstr + (int32_t)pCpu->Param1.parval); 3952 3953 AssertMsg(pJmpDest, ("PATMR3GuestGCPtrToPatchGCPtr failed for %RRv\n", pInstrGC + pCpu->cbInstr + (int32_t)pCpu->Param1.parval)); 3954 3954 pPatch->pPatchJumpDestGC = pJmpDest; 3955 3955 … … 5199 5199 && (pConflictPatch->flags & PATMFL_CODE32) 5200 5200 && (cpu.pCurInstr->uOpcode == OP_JMP || (cpu.pCurInstr->fOpType & DISOPTYPE_COND_CONTROLFLOW)) 5201 && (cpu. param1.fUse & DISUSE_IMMEDIATE32_REL))5201 && (cpu.Param1.fUse & DISUSE_IMMEDIATE32_REL)) 5202 5202 { 5203 5203 /* Hint patches must be enabled first. */ -
trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
r41738 r41739 694 694 { 695 695 Log(("patmPatchGenIndirectCall\n")); 696 Assert(pCpu-> param1.cb == 4);696 Assert(pCpu->Param1.cb == 4); 697 697 Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J); 698 698 … … 790 790 791 791 Log(("patmPatchGenIndirectJump\n")); 792 Assert(pCpu-> param1.cb == 4);792 Assert(pCpu->Param1.cb == 4); 793 793 Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J); 794 794 … … 857 857 /** @note optimization: multiple identical ret instruction in a single patch can share a single patched ret. */ 858 858 if ( pPatch->pTempInfo->pPatchRetInstrGC 859 && pPatch->pTempInfo->uPatchRetParam1 == (uint32_t)pCpu-> param1.parval) /* nr of bytes popped off the stack should be identical of course! */859 && pPatch->pTempInfo->uPatchRetParam1 == (uint32_t)pCpu->Param1.parval) /* nr of bytes popped off the stack should be identical of course! */ 860 860 { 861 861 Assert(pCpu->pCurInstr->uOpcode == OP_RETN); … … 891 891 { 892 892 pPatch->pTempInfo->pPatchRetInstrGC = pPatchRetInstrGC; 893 pPatch->pTempInfo->uPatchRetParam1 = pCpu-> param1.parval;893 pPatch->pTempInfo->uPatchRetParam1 = pCpu->Param1.parval; 894 894 } 895 895 return rc; … … 1164 1164 // mov DRx, GPR 1165 1165 pPB[0] = 0x89; //mov disp32, GPR 1166 Assert(pCpu-> param1.fUse & DISUSE_REG_DBG);1167 Assert(pCpu-> param2.fUse & DISUSE_REG_GEN32);1168 1169 dbgreg = pCpu-> param1.base.reg_dbg;1170 reg = pCpu-> param2.base.reg_gen;1166 Assert(pCpu->Param1.fUse & DISUSE_REG_DBG); 1167 Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32); 1168 1169 dbgreg = pCpu->Param1.base.reg_dbg; 1170 reg = pCpu->Param2.base.reg_gen; 1171 1171 } 1172 1172 else 1173 1173 { 1174 1174 // mov GPR, DRx 1175 Assert(pCpu-> param1.fUse & DISUSE_REG_GEN32);1176 Assert(pCpu-> param2.fUse & DISUSE_REG_DBG);1175 Assert(pCpu->Param1.fUse & DISUSE_REG_GEN32); 1176 Assert(pCpu->Param2.fUse & DISUSE_REG_DBG); 1177 1177 1178 1178 pPB[0] = 0x8B; // mov GPR, disp32 1179 reg = pCpu-> param1.base.reg_gen;1180 dbgreg = pCpu-> param2.base.reg_dbg;1179 reg = pCpu->Param1.base.reg_gen; 1180 dbgreg = pCpu->Param2.base.reg_dbg; 1181 1181 } 1182 1182 … … 1214 1214 // mov CRx, GPR 1215 1215 pPB[0] = 0x89; //mov disp32, GPR 1216 ctrlreg = pCpu-> param1.base.reg_ctrl;1217 reg = pCpu-> param2.base.reg_gen;1218 Assert(pCpu-> param1.fUse & DISUSE_REG_CR);1219 Assert(pCpu-> param2.fUse & DISUSE_REG_GEN32);1216 ctrlreg = pCpu->Param1.base.reg_ctrl; 1217 reg = pCpu->Param2.base.reg_gen; 1218 Assert(pCpu->Param1.fUse & DISUSE_REG_CR); 1219 Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32); 1220 1220 } 1221 1221 else 1222 1222 { 1223 1223 // mov GPR, DRx 1224 Assert(pCpu-> param1.fUse & DISUSE_REG_GEN32);1225 Assert(pCpu-> param2.fUse & DISUSE_REG_CR);1224 Assert(pCpu->Param1.fUse & DISUSE_REG_GEN32); 1225 Assert(pCpu->Param2.fUse & DISUSE_REG_CR); 1226 1226 1227 1227 pPB[0] = 0x8B; // mov GPR, disp32 1228 reg = pCpu-> param1.base.reg_gen;1229 ctrlreg = pCpu-> param2.base.reg_ctrl;1228 reg = pCpu->Param1.base.reg_gen; 1229 ctrlreg = pCpu->Param2.base.reg_ctrl; 1230 1230 } 1231 1231 … … 1292 1292 if (pCpu->fPrefix & DISPREFIX_OPSIZE) 1293 1293 pPB[offset++] = 0x66; /* size override -> 16 bits pop */ 1294 pPB[offset++] = 0x58 + pCpu-> param1.base.reg_gen;1294 pPB[offset++] = 0x58 + pCpu->Param1.base.reg_gen; 1295 1295 PATCHGEN_EPILOG(pPatch, offset); 1296 1296 … … 1325 1325 PATCHGEN_PROLOG(pVM, pPatch); 1326 1326 1327 if (pCpu-> param1.fUse == DISUSE_REG_GEN32 || pCpu->param1.fUse == DISUSE_REG_GEN16)1327 if (pCpu->Param1.fUse == DISUSE_REG_GEN32 || pCpu->Param1.fUse == DISUSE_REG_GEN16) 1328 1328 { 1329 1329 /* Register operand */ … … 1335 1335 pPB[offset++] = 0x8B; // mov destreg, CPUMCTX.tr/ldtr 1336 1336 /* Modify REG part according to destination of original instruction */ 1337 pPB[offset++] = MAKE_MODRM(0, pCpu-> param1.base.reg_gen, 5);1337 pPB[offset++] = MAKE_MODRM(0, pCpu->Param1.base.reg_gen, 5); 1338 1338 if (pCpu->pCurInstr->uOpcode == OP_STR) 1339 1339 {
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