Changeset 41743 in vbox

Timestamp:

Jun 15, 2012 2:00:58 AM (13 years ago)

Author:

vboxsync

Message:

DISOPPARAM: s/index.reg_gen/Index.idxGenReg/ + doc

Location:

trunk

Files:

• include/VBox/dis.h (modified) (5 diffs)
• src/VBox/Disassembler/DisasmCore.cpp (modified) (2 diffs)
• src/VBox/Disassembler/DisasmFormatYasm.cpp (modified) (3 diffs)
• src/VBox/Disassembler/DisasmReg.cpp (modified) (3 diffs)

trunk/include/VBox/dis.h

@@ -194 +194 @@
 /** @name 64-bit general register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
+ * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
  * @note  Safe to assume same values as the 16-bit and 32-bit general registers.
  * @{
@@ -218 +218 @@
 /** @name 32-bit general register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
+ * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
  * @note  Safe to assume same values as the 16-bit and 64-bit general registers.
  * @{
@@ -242 +242 @@
 /** @name 16-bit general register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
+ * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
  * @note  Safe to assume same values as the 32-bit and 64-bit general registers.
  * @{
@@ -266 +266 @@
 /** @name 8-bit general register indexes.
  * This mostly (?) matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
+ * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
  * @{
  */
@@ -426 +426 @@
         uint8_t     reg_dbg;
     } base;
+    /** The SIB index register meaning, applicable if DISUSE_INDEX is
+     * set in fUse. */
     union
     {
-        /** DISGREG_XXX. */
-        uint8_t     reg_gen;
-    } index;
-
+        /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
+         * DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
+        uint8_t     idxGenReg;
+    } Index;
     /** 2, 4 or 8, if DISUSE_SCALE is set in fUse. */
     uint8_t         uScale;

trunk/src/VBox/Disassembler/DisasmCore.cpp

@@ -617 +617 @@
     {
          pParam->fUse |= DISUSE_INDEX | regtype;
-         pParam->index.reg_gen = index;
+         pParam->Index.idxGenReg = index;
 
          if (scale != 0)
@@ -2379 +2379 @@
     {
         pParam->fUse |= DISUSE_INDEX;
-        pParam->index.reg_gen = IndexModRMReg16[idx];
+        pParam->Index.idxGenReg = IndexModRMReg16[idx];
     }
 }

trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp

@@ -208 +208 @@
         case DISCPUMODE_16BIT:
         {
-            Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
-            const char *psz = g_aszYasmRegGen16[pParam->index.reg_gen];
+            Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
+            const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;
@@ -216 +216 @@
         case DISCPUMODE_32BIT:
         {
-            Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
-            const char *psz = g_aszYasmRegGen32[pParam->index.reg_gen];
+            Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
+            const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;
@@ -224 +224 @@
         case DISCPUMODE_64BIT:
         {
-            Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
-            const char *psz = g_aszYasmRegGen64[pParam->index.reg_gen];
+            Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
+            const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;

trunk/src/VBox/Disassembler/DisasmReg.cpp

@@ -549 +549 @@
 
                 pParamVal->flags |= DISQPV_FLAG_16;
-                if (RT_FAILURE(DISFetchReg16(pCtx, pParam->index.reg_gen, &val16))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Index.idxGenReg, &val16))) return VERR_INVALID_PARAMETER;
 
                 Assert(!(pParam->fUse & DISUSE_SCALE));   /* shouldn't be possible in 16 bits mode */
@@ -561 +561 @@
 
                 pParamVal->flags |= DISQPV_FLAG_32;
-                if (RT_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Index.idxGenReg, &val32))) return VERR_INVALID_PARAMETER;
 
                 if (pParam->fUse & DISUSE_SCALE)
@@ -574 +574 @@
 
                 pParamVal->flags |= DISQPV_FLAG_64;
-                if (RT_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Index.idxGenReg, &val64))) return VERR_INVALID_PARAMETER;
 
                 if (pParam->fUse & DISUSE_SCALE)