Index: trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41744)
@@ -879,8 +879,8 @@
                 {
                 case 1: //special case for AH etc
-                        rc = DISWriteReg8(pRegFrame, pDis->Param1.base.reg_gen,  (uint8_t )valpar2); break;
-                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, (uint16_t)valpar2); break;
-                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.base.reg_gen, (uint32_t)valpar2); break;
-                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.base.reg_gen, valpar2); break;
+                        rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg,  (uint8_t )valpar2); break;
+                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
+                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
+                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
                 default: AssertFailedReturn(VERR_EM_INTERPRETER);
                 }
@@ -905,8 +905,8 @@
                 {
                 case 1: //special case for AH etc
-                        rc = DISWriteReg8(pRegFrame, pDis->Param2.base.reg_gen,  (uint8_t )valpar1);    break;
-                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.base.reg_gen, (uint16_t)valpar1);    break;
-                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.base.reg_gen, (uint32_t)valpar1);    break;
-                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.base.reg_gen, valpar1);              break;
+                        rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg,  (uint8_t )valpar1);    break;
+                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1);    break;
+                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1);    break;
+                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1);              break;
                 default: AssertFailedReturn(VERR_EM_INTERPRETER);
                 }
@@ -1051,5 +1051,5 @@
                 if (    (pDis->Param1.fUse & DISUSE_BASE)
                     &&  (pDis->Param1.fUse & (DISUSE_REG_GEN16|DISUSE_REG_GEN32))
-                    &&  pDis->Param1.base.reg_gen == DISGREG_ESP
+                    &&  pDis->Param1.Base.idxGenReg == DISGREG_ESP
                    )
                    pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
@@ -1609,8 +1609,8 @@
                 switch(param1.size)
                 {
-                case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.base.reg_gen,  (uint8_t) val64); break;
-                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, (uint16_t)val64); break;
-                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.base.reg_gen, (uint32_t)val64); break;
-                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.base.reg_gen, val64); break;
+                case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg,  (uint8_t) val64); break;
+                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
+                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
+                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
                 default:
                     return VERR_EM_INTERPRETER;
@@ -2428,6 +2428,6 @@
         if(param1.size != sizeof(uint16_t))
             return VERR_EM_INTERPRETER;
-        LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.base.reg_gen, cr0));
-        rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, cr0);
+        LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
+        rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
         break;
 
@@ -2469,8 +2469,8 @@
     NOREF(pvFault); NOREF(pcbSize);
     if ((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
-        return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_gen, pDis->Param2.base.reg_ctrl);
+        return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
 
     if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
-        return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_ctrl, pDis->Param2.base.reg_gen);
+        return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
 
     AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
@@ -2560,10 +2560,10 @@
     if((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
     {
-        rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_gen, pDis->Param2.base.reg_dbg);
+        rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
     }
     else
     if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
     {
-        rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_dbg, pDis->Param2.base.reg_gen);
+        rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
     }
     else
Index: trunk/src/VBox/VMM/VMMAll/IOMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IOMAll.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMAll/IOMAll.cpp	(revision 41744)
@@ -81,5 +81,5 @@
         {
             *pcbSize  = 4;
-            DISFetchReg32(pRegFrame, pParam->base.reg_gen, (uint32_t *)pu64Data);
+            DISFetchReg32(pRegFrame, pParam->Base.idxGenReg, (uint32_t *)pu64Data);
             return true;
         }
@@ -88,5 +88,5 @@
         {
             *pcbSize  = 2;
-            DISFetchReg16(pRegFrame, pParam->base.reg_gen, (uint16_t *)pu64Data);
+            DISFetchReg16(pRegFrame, pParam->Base.idxGenReg, (uint16_t *)pu64Data);
             return true;
         }
@@ -95,5 +95,5 @@
         {
             *pcbSize  = 1;
-            DISFetchReg8(pRegFrame, pParam->base.reg_gen, (uint8_t *)pu64Data);
+            DISFetchReg8(pRegFrame, pParam->Base.idxGenReg, (uint8_t *)pu64Data);
             return true;
         }
@@ -101,5 +101,5 @@
         Assert(pParam->fUse & DISUSE_REG_GEN64);
         *pcbSize  = 8;
-        DISFetchReg64(pRegFrame, pParam->base.reg_gen, pu64Data);
+        DISFetchReg64(pRegFrame, pParam->Base.idxGenReg, pu64Data);
         return true;
     }
@@ -137,5 +137,5 @@
         {
             *pcbSize  = 2;
-            DISFetchRegSeg(pRegFrame, (DISSELREG)pParam->base.reg_seg, (RTSEL *)pu64Data);
+            DISFetchRegSeg(pRegFrame, (DISSELREG)pParam->Base.idxSegReg, (RTSEL *)pu64Data);
             return true;
         } /* Else - error. */
@@ -169,5 +169,5 @@
     if (pParam->fUse & DISUSE_REG_GEN32)
     {
-        DISWriteReg32(pRegFrame, pParam->base.reg_gen, (uint32_t)u64Data);
+        DISWriteReg32(pRegFrame, pParam->Base.idxGenReg, (uint32_t)u64Data);
         return true;
     }
@@ -175,5 +175,5 @@
     if (pParam->fUse & DISUSE_REG_GEN64)
     {
-        DISWriteReg64(pRegFrame, pParam->base.reg_gen, u64Data);
+        DISWriteReg64(pRegFrame, pParam->Base.idxGenReg, u64Data);
         return true;
     }
@@ -181,5 +181,5 @@
     if (pParam->fUse & DISUSE_REG_GEN16)
     {
-        DISWriteReg16(pRegFrame, pParam->base.reg_gen, (uint16_t)u64Data);
+        DISWriteReg16(pRegFrame, pParam->Base.idxGenReg, (uint16_t)u64Data);
         return true;
     }
@@ -187,5 +187,5 @@
     if (pParam->fUse & DISUSE_REG_GEN8)
     {
-        DISWriteReg8(pRegFrame, pParam->base.reg_gen, (uint8_t)u64Data);
+        DISWriteReg8(pRegFrame, pParam->Base.idxGenReg, (uint8_t)u64Data);
         return true;
     }
@@ -193,5 +193,5 @@
     if (pParam->fUse & DISUSE_REG_SEG)
     {
-        DISWriteRegSeg(pRegFrame, (DISSELREG)pParam->base.reg_seg, (RTSEL)u64Data);
+        DISWriteRegSeg(pRegFrame, (DISSELREG)pParam->Base.idxSegReg, (RTSEL)u64Data);
         return true;
     }
Index: trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41744)
@@ -761,5 +761,5 @@
 #endif
 
-    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse,  pDis->Param1.base.reg_gen));
+    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse,  pDis->Param1.Base.idxGenReg));
 
     /* Non-supervisor mode write means it's used for something else. */
@@ -806,5 +806,5 @@
     if (    (    (pDis->Param1.fUse & DISUSE_REG_GEN32)
              ||  (pDis->Param1.fUse & DISUSE_REG_GEN64))
-        &&  (pDis->Param1.base.reg_gen == DISGREG_ESP))
+        &&  (pDis->Param1.Base.idxGenReg == DISGREG_ESP))
     {
         Log4(("pgmPoolMonitorIsReused: ESP\n"));
Index: trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41744)
@@ -994,6 +994,6 @@
                     //read
                     Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
-                    Assert(Cpu.Param2.base.reg_ctrl <= DISCREG_CR4);
-                    STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.base.reg_ctrl]);
+                    Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
+                    STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
                 }
                 else
@@ -1001,6 +1001,6 @@
                     //write
                     Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
-                    Assert(Cpu.Param1.base.reg_ctrl <= DISCREG_CR4);
-                    STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.base.reg_ctrl]);
+                    Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
+                    STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
                 }
                 break;
Index: trunk/src/VBox/VMM/VMMR3/HWACCM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41744)
@@ -1839,5 +1839,5 @@
             {
                 pPatch->enmType     = HWACCMTPRINSTR_WRITE_REG;
-                pPatch->uSrcOperand = pDis->Param2.base.reg_gen;
+                pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
             }
             else
@@ -1857,5 +1857,5 @@
             RTGCPTR  oldrip   = pCtx->rip;
             uint32_t oldcbOp  = cbOp;
-            uint32_t uMmioReg = pDis->Param1.base.reg_gen;
+            uint32_t uMmioReg = pDis->Param1.Base.idxGenReg;
 
             /* read */
@@ -1873,5 +1873,5 @@
                 &&  pDis->pCurInstr->uOpcode == OP_SHR
                 &&  pDis->Param1.fUse == DISUSE_REG_GEN32
-                &&  pDis->Param1.base.reg_gen == uMmioReg
+                &&  pDis->Param1.Base.idxGenReg == uMmioReg
                 &&  pDis->Param2.fUse == DISUSE_IMMEDIATE8
                 &&  pDis->Param2.uValue == 4
@@ -1890,5 +1890,5 @@
                 szInstr[1] = 0x0F;
                 szInstr[2] = 0x20;
-                szInstr[3] = 0xC0 | pDis->Param1.base.reg_gen;
+                szInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
                 for (unsigned i = 4; i < pPatch->cbOp; i++)
                     szInstr[i] = 0x90;  /* nop */
@@ -1906,5 +1906,5 @@
             {
                 pPatch->enmType     = HWACCMTPRINSTR_READ;
-                pPatch->uDstOperand = pDis->Param1.base.reg_gen;
+                pPatch->uDstOperand = pDis->Param1.Base.idxGenReg;
 
                 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
@@ -2028,5 +2028,5 @@
                 *
                 */
-            bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.base.reg_gen == DISGREG_EAX);
+            bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
 
             aPatch[off++] = 0x51;    /* push ecx */
@@ -2041,5 +2041,5 @@
                 {
                     aPatch[off++] = 0x89;    /* mov eax, src_reg */
-                    aPatch[off++] = MAKE_MODRM(3, pDis->Param2.base.reg_gen, DISGREG_EAX);
+                    aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
                 }
             }
@@ -2081,9 +2081,9 @@
             Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
 
-            if (pDis->Param1.base.reg_gen != DISGREG_ECX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
                 aPatch[off++] = 0x51;    /* push ecx */
-            if (pDis->Param1.base.reg_gen != DISGREG_EDX )
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
                 aPatch[off++] = 0x52;    /* push edx */
-            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
                 aPatch[off++] = 0x50;    /* push eax */
 
@@ -2098,15 +2098,15 @@
             aPatch[off++] = 0x32;
 
-            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
             {
                 aPatch[off++] = 0x89;    /* mov dst_reg, eax */
-                aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.base.reg_gen);
+                aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
             }
 
-            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
                 aPatch[off++] = 0x58;    /* pop eax */
-            if (pDis->Param1.base.reg_gen != DISGREG_EDX )
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
                 aPatch[off++] = 0x5A;    /* pop edx */
-            if (pDis->Param1.base.reg_gen != DISGREG_ECX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
                 aPatch[off++] = 0x59;    /* pop ecx */
         }
Index: trunk/src/VBox/VMM/VMMR3/PATM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41744)
@@ -1749,5 +1749,5 @@
             /* mov ss, src? */
             if (    (pCpu->Param1.fUse & DISUSE_REG_SEG)
-                &&  (pCpu->Param1.base.reg_seg == DISSELREG_SS))
+                &&  (pCpu->Param1.Base.idxSegReg == DISSELREG_SS))
             {
                 Log(("Force recompilation of next instruction for OP_MOV at %RRv\n", pCurInstrGC));
@@ -1758,5 +1758,5 @@
             else
             if (    (pCpu->Param2.fUse & DISUSE_REG_SEG)
-                &&  (pCpu->Param2.base.reg_seg == USE_REG_SS)
+                &&  (pCpu->Param2.Base.idxSegReg == USE_REG_SS)
                 &&  (pCpu->Param1.fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN16)))     /** @todo memory operand must in theory be handled too */
             {
Index: trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41741)
+++ trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41744)
@@ -1167,6 +1167,6 @@
         Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32);
 
-        dbgreg = pCpu->Param1.base.reg_dbg;
-        reg    = pCpu->Param2.base.reg_gen;
+        dbgreg = pCpu->Param1.Base.idxDbgReg;
+        reg    = pCpu->Param2.Base.idxGenReg;
     }
     else
@@ -1177,6 +1177,6 @@
 
         pPB[0] = 0x8B;      // mov GPR, disp32
-        reg    = pCpu->Param1.base.reg_gen;
-        dbgreg = pCpu->Param2.base.reg_dbg;
+        reg    = pCpu->Param1.Base.idxGenReg;
+        dbgreg = pCpu->Param2.Base.idxDbgReg;
     }
 
@@ -1214,6 +1214,6 @@
         // mov CRx, GPR
         pPB[0] = 0x89;      //mov disp32, GPR
-        ctrlreg = pCpu->Param1.base.reg_ctrl;
-        reg     = pCpu->Param2.base.reg_gen;
+        ctrlreg = pCpu->Param1.Base.idxCtrlReg;
+        reg     = pCpu->Param2.Base.idxGenReg;
         Assert(pCpu->Param1.fUse & DISUSE_REG_CR);
         Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32);
@@ -1226,6 +1226,6 @@
 
         pPB[0]  = 0x8B;      // mov GPR, disp32
-        reg     = pCpu->Param1.base.reg_gen;
-        ctrlreg = pCpu->Param2.base.reg_ctrl;
+        reg     = pCpu->Param1.Base.idxGenReg;
+        ctrlreg = pCpu->Param2.Base.idxCtrlReg;
     }
 
@@ -1292,5 +1292,5 @@
     if (pCpu->fPrefix & DISPREFIX_OPSIZE)
         pPB[offset++] = 0x66; /* size override -> 16 bits pop */
-    pPB[offset++] = 0x58 + pCpu->Param1.base.reg_gen;
+    pPB[offset++] = 0x58 + pCpu->Param1.Base.idxGenReg;
     PATCHGEN_EPILOG(pPatch, offset);
 
@@ -1335,5 +1335,5 @@
         pPB[offset++] = 0x8B;              // mov       destreg, CPUMCTX.tr/ldtr
         /* Modify REG part according to destination of original instruction */
-        pPB[offset++] = MAKE_MODRM(0, pCpu->Param1.base.reg_gen, 5);
+        pPB[offset++] = MAKE_MODRM(0, pCpu->Param1.Base.idxGenReg, 5);
         if (pCpu->pCurInstr->uOpcode == OP_STR)
         {
