Changeset 41899 in vbox
- Timestamp:
- Jun 23, 2012 7:07:03 PM (13 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
- 1 copied
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include/VBox/types.h (modified) (1 diff)
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include/VBox/vmm/cpumctx-v1_6.h (copied) (copied from trunk/include/VBox/vmm/cpumctx.h ) (3 diffs, 1 prop)
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include/VBox/vmm/cpumctx.h (modified) (1 diff)
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src/VBox/VMM/VMMR3/CPUM.cpp (modified) (11 diffs)
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src/VBox/VMM/VMMR3/PATMSSM.cpp (modified) (2 diffs)
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src/VBox/VMM/testcase/tstVMStruct.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/types.h
r41790 r41899 729 729 uint64_t pIdt; 730 730 } VBOXIDTR, *PVBOXIDTR; 731 #pragma pack()732 733 #pragma pack(1)734 /** IDTR from version 1.6 */735 typedef struct VBOXIDTR_VER1_6736 {737 /** Size of the IDT. */738 uint16_t cbIdt;739 /** Address of the IDT. */740 uint32_t pIdt;741 } VBOXIDTR_VER1_6, *PVBOXIDTR_VER1_6;742 731 #pragma pack() 743 732 -
trunk/include/VBox/vmm/cpumctx-v1_6.h
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Property svn:mergeinfo
set to (toggle deleted branches)
/branches/VBox-3.0/include/VBox/vmm/cpumctx.h 58652,70973 /branches/VBox-3.2/include/VBox/vmm/cpumctx.h 66309,66318 /branches/VBox-4.0/include/VBox/vmm/cpumctx.h 70873 /branches/VBox-4.1/include/VBox/vmm/cpumctx.h 74233
r41892 r41899 1 1 /** @file 2 * CPUM - CPU Monitor(/ Manager), Context Structures .2 * CPUM - CPU Monitor(/ Manager), Context Structures from v1.6 (saved state). 3 3 */ 4 4 … … 24 24 */ 25 25 26 #ifndef ___VBox_vmm_cpumctx_h 27 #define ___VBox_vmm_cpumctx_h 28 29 #ifndef VBOX_FOR_DTRACE_LIB 30 # include <iprt/x86.h> 31 #else 32 # pragma D depends_on library x86.d 33 #endif 26 #ifndef ___VBox_vmm_cpumctx_v1_6_h 27 #define ___VBox_vmm_cpumctx_v1_6_h 28 29 #include <iprt/x86.h> 34 30 35 31 36 32 RT_C_DECLS_BEGIN 37 33 38 /** @addgroup grp_cpum_ctx The CPUM Context Structures34 /** @addgroup grp_cpum_ctx_v1_6 The CPUM Context Structures from v1.6 39 35 * @ingroup grp_cpum 40 36 * @{ 41 37 */ 42 38 43 /** 44 * Selector hidden registers. 45 */ 46 typedef struct CPUMSELREGHID 39 #pragma pack(1) 40 /** IDTR from version 1.6 */ 41 typedef struct VBOXIDTR_VER1_6 47 42 { 48 /** Base register. 49 * 50 * Long mode remarks: 51 * - Unused in long mode for CS, DS, ES, SS 52 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address 53 * - 64 bits for TR & LDTR 54 */ 55 uint64_t u64Base; 56 /** Limit (expanded). */ 57 uint32_t u32Limit; 58 /** Flags. 59 * This is the high 32-bit word of the descriptor entry. 60 * Only the flags, dpl and type are used. */ 61 X86DESCATTR Attr; 62 } CPUMSELREGHID; 63 64 65 /** 66 * The sysenter register set. 67 */ 68 typedef struct CPUMSYSENTER 69 { 70 /** Ring 0 cs. 71 * This value + 8 is the Ring 0 ss. 72 * This value + 16 is the Ring 3 cs. 73 * This value + 24 is the Ring 3 ss. 74 */ 75 uint64_t cs; 76 /** Ring 0 eip. */ 77 uint64_t eip; 78 /** Ring 0 esp. */ 79 uint64_t esp; 80 } CPUMSYSENTER; 81 82 /** 83 * For compilers (like DTrace) that does not grok nameless unions, we have a 84 * little hack to make them palatable. 85 */ 86 #ifdef VBOX_FOR_DTRACE_LIB 87 # define CPUM_UNION_NAME(a_Nm) a_Nm 88 #elif defined(VBOX_WITHOUT_UNNAMED_UNIONS) 89 # define CPUM_UNION_NAME(a_Nm) a_Nm 90 #else 91 # define CPUM_UNION_NAME(a_Nm) 92 #endif 93 94 95 /** 96 * CPU context core. 97 */ 98 #pragma pack(1) 99 typedef struct CPUMCTXCORE 100 { 101 union 102 { 103 uint16_t di; 104 uint32_t edi; 105 uint64_t rdi; 106 } CPUM_UNION_NAME(rdi); 107 union 108 { 109 uint16_t si; 110 uint32_t esi; 111 uint64_t rsi; 112 } CPUM_UNION_NAME(rsi); 113 union 114 { 115 uint16_t bp; 116 uint32_t ebp; 117 uint64_t rbp; 118 } CPUM_UNION_NAME(rbp); 119 union 120 { 121 uint16_t ax; 122 uint32_t eax; 123 uint64_t rax; 124 } CPUM_UNION_NAME(rax); 125 union 126 { 127 uint16_t bx; 128 uint32_t ebx; 129 uint64_t rbx; 130 } CPUM_UNION_NAME(rbx); 131 union 132 { 133 uint16_t dx; 134 uint32_t edx; 135 uint64_t rdx; 136 } CPUM_UNION_NAME(rdx); 137 union 138 { 139 uint16_t cx; 140 uint32_t ecx; 141 uint64_t rcx; 142 } CPUM_UNION_NAME(rcx); 143 union 144 { 145 uint16_t sp; 146 uint32_t esp; 147 uint64_t rsp; 148 } CPUM_UNION_NAME(rsp); 149 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */ 150 uint32_t lss_esp; 151 RTSEL ss; 152 RTSEL ssPadding; 153 154 RTSEL gs; 155 RTSEL gsPadding; 156 RTSEL fs; 157 RTSEL fsPadding; 158 RTSEL es; 159 RTSEL esPadding; 160 RTSEL ds; 161 RTSEL dsPadding; 162 RTSEL cs; 163 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */ 164 165 union 166 { 167 X86EFLAGS eflags; 168 X86RFLAGS rflags; 169 } CPUM_UNION_NAME(rflags); 170 union 171 { 172 uint16_t ip; 173 uint32_t eip; 174 uint64_t rip; 175 } CPUM_UNION_NAME(rip); 176 177 uint64_t r8; 178 uint64_t r9; 179 uint64_t r10; 180 uint64_t r11; 181 uint64_t r12; 182 uint64_t r13; 183 uint64_t r14; 184 uint64_t r15; 185 186 /** Hidden selector registers. 187 * @{ */ 188 CPUMSELREGHID esHid; 189 CPUMSELREGHID csHid; 190 CPUMSELREGHID ssHid; 191 CPUMSELREGHID dsHid; 192 CPUMSELREGHID fsHid; 193 CPUMSELREGHID gsHid; 194 /** @} */ 195 196 } CPUMCTXCORE; 43 /** Size of the IDT. */ 44 uint16_t cbIdt; 45 /** Address of the IDT. */ 46 uint32_t pIdt; 47 } VBOXIDTR_VER1_6; 197 48 #pragma pack() 198 199 200 /**201 * CPU context.202 */203 #pragma pack(1)204 typedef struct CPUMCTX205 {206 /** FPU state. (16-byte alignment)207 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the208 * actual format or convert it (waste of time). */209 X86FXSTATE fpu;210 211 /** CPUMCTXCORE Part.212 * @{ */213 union214 {215 uint8_t dil;216 uint16_t di;217 uint32_t edi;218 uint64_t rdi;219 } CPUM_UNION_NAME(rdi);220 union221 {222 uint8_t sil;223 uint16_t si;224 uint32_t esi;225 uint64_t rsi;226 } CPUM_UNION_NAME(rsi);227 union228 {229 uint16_t bp;230 uint32_t ebp;231 uint64_t rbp;232 } CPUM_UNION_NAME(rbp);233 union234 {235 uint8_t al;236 uint16_t ax;237 uint32_t eax;238 uint64_t rax;239 } CPUM_UNION_NAME(rax);240 union241 {242 uint8_t bl;243 uint16_t bx;244 uint32_t ebx;245 uint64_t rbx;246 } CPUM_UNION_NAME(rbx);247 union248 {249 uint8_t dl;250 uint16_t dx;251 uint32_t edx;252 uint64_t rdx;253 } CPUM_UNION_NAME(rdx);254 union255 {256 uint8_t cl;257 uint16_t cx;258 uint32_t ecx;259 uint64_t rcx;260 } CPUM_UNION_NAME(rcx);261 union262 {263 uint16_t sp;264 uint32_t esp;265 uint64_t rsp;266 } CPUM_UNION_NAME(rsp);267 /** @note lss esp, [] in the switcher needs some space, so we reserve it here268 * instead of relying on the exact esp & ss layout as before (prevented269 * us from using a union with rsp). */270 uint32_t lss_esp;271 RTSEL ss;272 RTSEL ssPadding;273 274 RTSEL gs;275 RTSEL gsPadding;276 RTSEL fs;277 RTSEL fsPadding;278 RTSEL es;279 RTSEL esPadding;280 RTSEL ds;281 RTSEL dsPadding;282 RTSEL cs;283 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */284 285 union286 {287 X86EFLAGS eflags;288 X86RFLAGS rflags;289 } CPUM_UNION_NAME(rflags);290 union291 {292 uint16_t ip;293 uint32_t eip;294 uint64_t rip;295 } CPUM_UNION_NAME(rip);296 297 uint64_t r8;298 uint64_t r9;299 uint64_t r10;300 uint64_t r11;301 uint64_t r12;302 uint64_t r13;303 uint64_t r14;304 uint64_t r15;305 306 /** Hidden selector registers.307 * @{ */308 CPUMSELREGHID esHid;309 CPUMSELREGHID csHid;310 CPUMSELREGHID ssHid;311 CPUMSELREGHID dsHid;312 CPUMSELREGHID fsHid;313 CPUMSELREGHID gsHid;314 /** @} */315 316 /** @} */317 318 /** Control registers.319 * @{ */320 uint64_t cr0;321 uint64_t cr2;322 uint64_t cr3;323 uint64_t cr4;324 /** @} */325 326 /** Debug registers.327 * @remarks DR4 and DR5 should not be used since they are aliases for328 * DR6 and DR7 respectively on both AMD and Intel CPUs.329 * @remarks DR8-15 are currently not supported by AMD or Intel, so330 * neither do we.331 * @{ */332 uint64_t dr[8];333 /** @} */334 335 /** Global Descriptor Table register. */336 VBOXGDTR gdtr;337 uint16_t gdtrPadding;338 /** Interrupt Descriptor Table register. */339 VBOXIDTR idtr;340 uint16_t idtrPadding;341 /** The task register.342 * Only the guest context uses all the members. */343 RTSEL ldtr;344 RTSEL ldtrPadding;345 /** The task register.346 * Only the guest context uses all the members. */347 RTSEL tr;348 RTSEL trPadding;349 350 /** The sysenter msr registers.351 * This member is not used by the hypervisor context. */352 CPUMSYSENTER SysEnter;353 354 /** System MSRs.355 * @{ */356 uint64_t msrEFER;357 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */358 uint64_t msrPAT;359 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */360 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */361 uint64_t msrSFMASK; /**< syscall flag mask. */362 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */363 /** @} */364 365 /** Hidden selector registers.366 * @{ */367 CPUMSELREGHID ldtrHid;368 CPUMSELREGHID trHid;369 /** @} */370 371 #if 0372 /** Padding to align the size on a 64 byte boundary. */373 uint32_t padding[6];374 #endif375 } CPUMCTX;376 #pragma pack()377 378 #ifndef VBOX_FOR_DTRACE_LIB379 380 /**381 * Gets the CPUMCTXCORE part of a CPUMCTX.382 */383 # define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)384 49 385 50 … … 566 231 # pragma pack() 567 232 568 #endif /* VBOX_FOR_DTRACE_LIB */569 570 /**571 * Additional guest MSRs (i.e. not part of the CPU context structure).572 *573 * @remarks Never change the order here because of the saved stated! The size574 * can in theory be changed, but keep older VBox versions in mind.575 */576 typedef union CPUMCTXMSRS577 {578 struct579 {580 uint64_t TscAux; /**< MSR_K8_TSC_AUX */581 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */582 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */583 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */584 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */585 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */586 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */587 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */588 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */589 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */590 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */591 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */592 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */593 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */594 } msr;595 uint64_t au64[64];596 } CPUMCTXMSRS;597 /** Pointer to the guest MSR state. */598 typedef CPUMCTXMSRS *PCPUMCTXMSRS;599 /** Pointer to the const guest MSR state. */600 typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;601 602 /**603 * The register set returned by a CPUID operation.604 */605 typedef struct CPUMCPUID606 {607 uint32_t eax;608 uint32_t ebx;609 uint32_t ecx;610 uint32_t edx;611 } CPUMCPUID;612 /** Pointer to a CPUID leaf. */613 typedef CPUMCPUID *PCPUMCPUID;614 /** Pointer to a const CPUID leaf. */615 typedef const CPUMCPUID *PCCPUMCPUID;616 617 233 /** @} */ 618 234 -
Property svn:mergeinfo
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trunk/include/VBox/vmm/cpumctx.h
r41270 r41899 382 382 */ 383 383 # define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi) 384 385 386 /**387 * Selector hidden registers, for version 1.6 saved state.388 */389 typedef struct CPUMSELREGHID_VER1_6390 {391 /** Base register. */392 uint32_t u32Base;393 /** Limit (expanded). */394 uint32_t u32Limit;395 /** Flags.396 * This is the high 32-bit word of the descriptor entry.397 * Only the flags, dpl and type are used. */398 X86DESCATTR Attr;399 } CPUMSELREGHID_VER1_6;400 401 /**402 * CPU context, for version 1.6 saved state.403 * @remarks PATM uses this, which is why it has to be here.404 */405 # pragma pack(1)406 typedef struct CPUMCTX_VER1_6407 {408 /** FPU state. (16-byte alignment)409 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the410 * actual format or convert it (waste of time). */411 X86FXSTATE fpu;412 413 /** CPUMCTXCORE Part.414 * @{ */415 union416 {417 uint32_t edi;418 uint64_t rdi;419 } CPUM_UNION_NAME(rdi);420 union421 {422 uint32_t esi;423 uint64_t rsi;424 } CPUM_UNION_NAME(rsi);425 union426 {427 uint32_t ebp;428 uint64_t rbp;429 } CPUM_UNION_NAME(rbp);430 union431 {432 uint32_t eax;433 uint64_t rax;434 } CPUM_UNION_NAME(rax);435 union436 {437 uint32_t ebx;438 uint64_t rbx;439 } CPUM_UNION_NAME(rbx);440 union441 {442 uint32_t edx;443 uint64_t rdx;444 } CPUM_UNION_NAME(rdx);445 union446 {447 uint32_t ecx;448 uint64_t rcx;449 } CPUM_UNION_NAME(rcx);450 /** @note We rely on the exact layout, because we use lss esp, [] in the451 * switcher. */452 uint32_t esp;453 RTSEL ss;454 RTSEL ssPadding;455 /* Note: no overlap with esp here. */456 uint64_t rsp_notused;457 458 RTSEL gs;459 RTSEL gsPadding;460 RTSEL fs;461 RTSEL fsPadding;462 RTSEL es;463 RTSEL esPadding;464 RTSEL ds;465 RTSEL dsPadding;466 RTSEL cs;467 RTSEL csPadding[3]; /**< 3 words to force 8 byte alignment for the remainder. */468 469 union470 {471 X86EFLAGS eflags;472 X86RFLAGS rflags;473 } CPUM_UNION_NAME(rflags);474 union475 {476 uint32_t eip;477 uint64_t rip;478 } CPUM_UNION_NAME(rip);479 480 uint64_t r8;481 uint64_t r9;482 uint64_t r10;483 uint64_t r11;484 uint64_t r12;485 uint64_t r13;486 uint64_t r14;487 uint64_t r15;488 489 /** Hidden selector registers.490 * @{ */491 CPUMSELREGHID_VER1_6 esHid;492 CPUMSELREGHID_VER1_6 csHid;493 CPUMSELREGHID_VER1_6 ssHid;494 CPUMSELREGHID_VER1_6 dsHid;495 CPUMSELREGHID_VER1_6 fsHid;496 CPUMSELREGHID_VER1_6 gsHid;497 /** @} */498 499 /** @} */500 501 /** Control registers.502 * @{ */503 uint64_t cr0;504 uint64_t cr2;505 uint64_t cr3;506 uint64_t cr4;507 uint64_t cr8;508 /** @} */509 510 /** Debug registers.511 * @{ */512 uint64_t dr0;513 uint64_t dr1;514 uint64_t dr2;515 uint64_t dr3;516 uint64_t dr4; /**< @todo remove dr4 and dr5. */517 uint64_t dr5;518 uint64_t dr6;519 uint64_t dr7;520 /* DR8-15 are currently not supported */521 /** @} */522 523 /** Global Descriptor Table register. */524 VBOXGDTR_VER1_6 gdtr;525 uint16_t gdtrPadding;526 uint32_t gdtrPadding64;/** @todo fix this hack */527 /** Interrupt Descriptor Table register. */528 VBOXIDTR_VER1_6 idtr;529 uint16_t idtrPadding;530 uint32_t idtrPadding64;/** @todo fix this hack */531 /** The task register.532 * Only the guest context uses all the members. */533 RTSEL ldtr;534 RTSEL ldtrPadding;535 /** The task register.536 * Only the guest context uses all the members. */537 RTSEL tr;538 RTSEL trPadding;539 540 /** The sysenter msr registers.541 * This member is not used by the hypervisor context. */542 CPUMSYSENTER SysEnter;543 544 /** System MSRs.545 * @{ */546 uint64_t msrEFER;547 uint64_t msrSTAR;548 uint64_t msrPAT;549 uint64_t msrLSTAR;550 uint64_t msrCSTAR;551 uint64_t msrSFMASK;552 uint64_t msrFSBASE;553 uint64_t msrGSBASE;554 uint64_t msrKERNELGSBASE;555 /** @} */556 557 /** Hidden selector registers.558 * @{ */559 CPUMSELREGHID_VER1_6 ldtrHid;560 CPUMSELREGHID_VER1_6 trHid;561 /** @} */562 563 /** padding to get 32byte aligned size. */564 uint32_t padding[2];565 } CPUMCTX_VER1_6;566 # pragma pack()567 384 568 385 #endif /* VBOX_FOR_DTRACE_LIB */ -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r41803 r41899 38 38 #include <VBox/vmm/cpum.h> 39 39 #include <VBox/vmm/cpumdis.h> 40 #include <VBox/vmm/cpumctx-v1_6.h> 40 41 #include <VBox/vmm/pgm.h> 41 42 #include <VBox/vmm/mm.h> … … 63 64 * Defined Constants And Macros * 64 65 *******************************************************************************/ 66 #if 0 /* later when actual changes have been made */ 65 67 /** The current saved state version. */ 66 #define CPUM_SAVED_STATE_VERSION 13 68 #define CPUM_SAVED_STATE_VERSION 14 69 #else 70 # define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_MEM 71 #endif 72 /** The current saved state version before using SSMR3PutStruct. */ 73 #define CPUM_SAVED_STATE_VERSION_MEM 13 67 74 /** The saved state version before introducing the MSR size field. */ 68 75 #define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12 … … 114 121 static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs); 115 122 static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs); 123 124 125 /******************************************************************************* 126 * Global Variables * 127 *******************************************************************************/ 128 /** Saved state field descriptors for CPUMCTX. */ 129 static const SSMFIELD g_aCpumCtxFields[] = 130 { 131 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW), 132 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW), 133 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW), 134 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP), 135 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP), 136 SSMFIELD_ENTRY( CPUMCTX, fpu.CS), 137 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1), 138 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP), 139 SSMFIELD_ENTRY( CPUMCTX, fpu.DS), 140 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2), 141 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR), 142 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK), 143 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]), 144 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]), 145 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]), 146 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]), 147 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]), 148 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]), 149 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]), 150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]), 151 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]), 152 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]), 153 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]), 154 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]), 155 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]), 156 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]), 157 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]), 158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]), 159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]), 160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]), 161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]), 162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]), 163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]), 164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]), 165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]), 166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]), 167 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest), 168 SSMFIELD_ENTRY( CPUMCTX, rdi), 169 SSMFIELD_ENTRY( CPUMCTX, rsi), 170 SSMFIELD_ENTRY( CPUMCTX, rbp), 171 SSMFIELD_ENTRY( CPUMCTX, rax), 172 SSMFIELD_ENTRY( CPUMCTX, rbx), 173 SSMFIELD_ENTRY( CPUMCTX, rdx), 174 SSMFIELD_ENTRY( CPUMCTX, rcx), 175 SSMFIELD_ENTRY( CPUMCTX, rsp), 176 SSMFIELD_ENTRY_IGNORE( CPUMCTX, lss_esp), 177 SSMFIELD_ENTRY( CPUMCTX, ss), 178 SSMFIELD_ENTRY_IGNORE( CPUMCTX, ssPadding), 179 SSMFIELD_ENTRY( CPUMCTX, gs), 180 SSMFIELD_ENTRY_IGNORE( CPUMCTX, gsPadding), 181 SSMFIELD_ENTRY( CPUMCTX, fs), 182 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fsPadding), 183 SSMFIELD_ENTRY( CPUMCTX, es), 184 SSMFIELD_ENTRY_IGNORE( CPUMCTX, esPadding), 185 SSMFIELD_ENTRY( CPUMCTX, ds), 186 SSMFIELD_ENTRY_IGNORE( CPUMCTX, dsPadding), 187 SSMFIELD_ENTRY( CPUMCTX, cs), 188 SSMFIELD_ENTRY_IGNORE( CPUMCTX, csPadding), 189 SSMFIELD_ENTRY( CPUMCTX, rflags), 190 SSMFIELD_ENTRY( CPUMCTX, rip), 191 SSMFIELD_ENTRY( CPUMCTX, r8), 192 SSMFIELD_ENTRY( CPUMCTX, r9), 193 SSMFIELD_ENTRY( CPUMCTX, r10), 194 SSMFIELD_ENTRY( CPUMCTX, r11), 195 SSMFIELD_ENTRY( CPUMCTX, r12), 196 SSMFIELD_ENTRY( CPUMCTX, r13), 197 SSMFIELD_ENTRY( CPUMCTX, r14), 198 SSMFIELD_ENTRY( CPUMCTX, r15), 199 SSMFIELD_ENTRY( CPUMCTX, esHid.u64Base), 200 SSMFIELD_ENTRY( CPUMCTX, esHid.u32Limit), 201 SSMFIELD_ENTRY( CPUMCTX, esHid.Attr), 202 SSMFIELD_ENTRY( CPUMCTX, csHid.u64Base), 203 SSMFIELD_ENTRY( CPUMCTX, csHid.u32Limit), 204 SSMFIELD_ENTRY( CPUMCTX, csHid.Attr), 205 SSMFIELD_ENTRY( CPUMCTX, ssHid.u64Base), 206 SSMFIELD_ENTRY( CPUMCTX, ssHid.u32Limit), 207 SSMFIELD_ENTRY( CPUMCTX, ssHid.Attr), 208 SSMFIELD_ENTRY( CPUMCTX, dsHid.u64Base), 209 SSMFIELD_ENTRY( CPUMCTX, dsHid.u32Limit), 210 SSMFIELD_ENTRY( CPUMCTX, dsHid.Attr), 211 SSMFIELD_ENTRY( CPUMCTX, fsHid.u64Base), 212 SSMFIELD_ENTRY( CPUMCTX, fsHid.u32Limit), 213 SSMFIELD_ENTRY( CPUMCTX, fsHid.Attr), 214 SSMFIELD_ENTRY( CPUMCTX, gsHid.u64Base), 215 SSMFIELD_ENTRY( CPUMCTX, gsHid.u32Limit), 216 SSMFIELD_ENTRY( CPUMCTX, gsHid.Attr), 217 SSMFIELD_ENTRY( CPUMCTX, cr0), 218 SSMFIELD_ENTRY( CPUMCTX, cr2), 219 SSMFIELD_ENTRY( CPUMCTX, cr3), 220 SSMFIELD_ENTRY( CPUMCTX, cr4), 221 SSMFIELD_ENTRY( CPUMCTX, dr[0]), 222 SSMFIELD_ENTRY( CPUMCTX, dr[1]), 223 SSMFIELD_ENTRY( CPUMCTX, dr[2]), 224 SSMFIELD_ENTRY( CPUMCTX, dr[3]), 225 SSMFIELD_ENTRY( CPUMCTX, dr[4]), 226 SSMFIELD_ENTRY_IGNORE( CPUMCTX, dr[5]), 227 SSMFIELD_ENTRY_IGNORE( CPUMCTX, dr[6]), 228 SSMFIELD_ENTRY( CPUMCTX, dr[7]), 229 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt), 230 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt), 231 SSMFIELD_ENTRY_IGNORE( CPUMCTX, gdtrPadding), 232 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt), 233 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt), 234 SSMFIELD_ENTRY_IGNORE( CPUMCTX, idtrPadding), 235 SSMFIELD_ENTRY( CPUMCTX, ldtr), 236 SSMFIELD_ENTRY_IGNORE( CPUMCTX, ldtrPadding), 237 SSMFIELD_ENTRY( CPUMCTX, tr), 238 SSMFIELD_ENTRY_IGNORE( CPUMCTX, trPadding), 239 SSMFIELD_ENTRY_IGNORE( CPUMCTX, SysEnter.cs), 240 SSMFIELD_ENTRY_IGNORE( CPUMCTX, SysEnter.eip), 241 SSMFIELD_ENTRY_IGNORE( CPUMCTX, SysEnter.esp), 242 SSMFIELD_ENTRY( CPUMCTX, msrEFER), 243 SSMFIELD_ENTRY( CPUMCTX, msrSTAR), 244 SSMFIELD_ENTRY( CPUMCTX, msrPAT), 245 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR), 246 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR), 247 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK), 248 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE), 249 SSMFIELD_ENTRY( CPUMCTX, ldtrHid.u64Base), 250 SSMFIELD_ENTRY( CPUMCTX, ldtrHid.u32Limit), 251 SSMFIELD_ENTRY( CPUMCTX, ldtrHid.Attr), 252 SSMFIELD_ENTRY( CPUMCTX, trHid.u64Base), 253 SSMFIELD_ENTRY( CPUMCTX, trHid.u32Limit), 254 SSMFIELD_ENTRY( CPUMCTX, trHid.Attr), 255 SSMFIELD_ENTRY_TERM() 256 }; 257 258 /** Saved state field descriptors for CPUMCTX_VER1_6. */ 259 static const SSMFIELD g_aCpumCtxFieldsV16[] = 260 { 261 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.FCW), 262 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.FSW), 263 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.FTW), 264 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.FOP), 265 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.FPUIP), 266 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.CS), 267 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.Rsrvd1), 268 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.FPUDP), 269 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.DS), 270 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.Rsrvd2), 271 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.MXCSR), 272 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.MXCSR_MASK), 273 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[0]), 274 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[1]), 275 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[2]), 276 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[3]), 277 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[4]), 278 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[5]), 279 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[6]), 280 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aRegs[7]), 281 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[0]), 282 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[1]), 283 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[2]), 284 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[3]), 285 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[4]), 286 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[5]), 287 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[6]), 288 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[7]), 289 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[8]), 290 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[9]), 291 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[10]), 292 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[11]), 293 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[12]), 294 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[13]), 295 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[14]), 296 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fpu.aXMM[15]), 297 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, fpu.au32RsrvdRest), 298 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rdi), 299 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rsi), 300 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rbp), 301 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rax), 302 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rbx), 303 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rdx), 304 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rcx), 305 SSMFIELD_ENTRY( CPUMCTX_VER1_6, esp), 306 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ss), 307 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, ssPadding), 308 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, rsp_notused), 309 SSMFIELD_ENTRY( CPUMCTX_VER1_6, gs), 310 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, gsPadding), 311 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fs), 312 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, fsPadding), 313 SSMFIELD_ENTRY( CPUMCTX_VER1_6, es), 314 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, esPadding), 315 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ds), 316 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, dsPadding), 317 SSMFIELD_ENTRY( CPUMCTX_VER1_6, cs), 318 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, csPadding), 319 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rflags), 320 SSMFIELD_ENTRY( CPUMCTX_VER1_6, rip), 321 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r8), 322 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r9), 323 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r10), 324 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r11), 325 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r12), 326 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r13), 327 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r14), 328 SSMFIELD_ENTRY( CPUMCTX_VER1_6, r15), 329 SSMFIELD_ENTRY( CPUMCTX_VER1_6, esHid.u32Base), 330 SSMFIELD_ENTRY( CPUMCTX_VER1_6, esHid.u32Limit), 331 SSMFIELD_ENTRY( CPUMCTX_VER1_6, esHid.Attr), 332 SSMFIELD_ENTRY( CPUMCTX_VER1_6, csHid.u32Base), 333 SSMFIELD_ENTRY( CPUMCTX_VER1_6, csHid.u32Limit), 334 SSMFIELD_ENTRY( CPUMCTX_VER1_6, csHid.Attr), 335 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ssHid.u32Base), 336 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ssHid.u32Limit), 337 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ssHid.Attr), 338 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dsHid.u32Base), 339 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dsHid.u32Limit), 340 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dsHid.Attr), 341 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fsHid.u32Base), 342 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fsHid.u32Limit), 343 SSMFIELD_ENTRY( CPUMCTX_VER1_6, fsHid.Attr), 344 SSMFIELD_ENTRY( CPUMCTX_VER1_6, gsHid.u32Base), 345 SSMFIELD_ENTRY( CPUMCTX_VER1_6, gsHid.u32Limit), 346 SSMFIELD_ENTRY( CPUMCTX_VER1_6, gsHid.Attr), 347 SSMFIELD_ENTRY( CPUMCTX_VER1_6, cr0), 348 SSMFIELD_ENTRY( CPUMCTX_VER1_6, cr2), 349 SSMFIELD_ENTRY( CPUMCTX_VER1_6, cr3), 350 SSMFIELD_ENTRY( CPUMCTX_VER1_6, cr4), 351 SSMFIELD_ENTRY( CPUMCTX_VER1_6, cr8), 352 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dr0), 353 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dr1), 354 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dr2), 355 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dr3), 356 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dr4), 357 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, dr5), 358 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, dr6), 359 SSMFIELD_ENTRY( CPUMCTX_VER1_6, dr7), 360 SSMFIELD_ENTRY( CPUMCTX_VER1_6, gdtr.cbGdt), 361 SSMFIELD_ENTRY( CPUMCTX_VER1_6, gdtr.pGdt), 362 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, gdtrPadding), 363 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, gdtrPadding64), 364 SSMFIELD_ENTRY( CPUMCTX_VER1_6, idtr.cbIdt), 365 SSMFIELD_ENTRY( CPUMCTX_VER1_6, idtr.pIdt), 366 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, idtrPadding), 367 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, idtrPadding64), 368 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ldtr), 369 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, ldtrPadding), 370 SSMFIELD_ENTRY( CPUMCTX_VER1_6, tr), 371 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, trPadding), 372 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, SysEnter.cs), 373 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, SysEnter.eip), 374 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, SysEnter.esp), 375 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrEFER), 376 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrSTAR), 377 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrPAT), 378 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrLSTAR), 379 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrCSTAR), 380 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrSFMASK), 381 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrFSBASE), 382 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrGSBASE), 383 SSMFIELD_ENTRY( CPUMCTX_VER1_6, msrKERNELGSBASE), 384 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ldtrHid.u32Base), 385 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ldtrHid.u32Limit), 386 SSMFIELD_ENTRY( CPUMCTX_VER1_6, ldtrHid.Attr), 387 SSMFIELD_ENTRY( CPUMCTX_VER1_6, trHid.u32Base), 388 SSMFIELD_ENTRY( CPUMCTX_VER1_6, trHid.u32Limit), 389 SSMFIELD_ENTRY( CPUMCTX_VER1_6, trHid.Attr), 390 SSMFIELD_ENTRY_IGNORE( CPUMCTX_VER1_6, padding), 391 SSMFIELD_ENTRY_TERM() 392 }; 116 393 117 394 … … 1948 2225 { 1949 2226 PVMCPU pVCpu = &pVM->aCpus[i]; 1950 1951 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));2227 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), SSMSTRUCT_FLAGS_MEM_BAND_AID, 2228 g_aCpumCtxFields, NULL); 1952 2229 } 1953 2230 … … 1958 2235 PVMCPU pVCpu = &pVM->aCpus[i]; 1959 2236 1960 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest)); 2237 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), SSMSTRUCT_FLAGS_MEM_BAND_AID, 2238 g_aCpumCtxFields, NULL); 1961 2239 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags); 1962 2240 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged); … … 2085 2363 */ 2086 2364 if ( uVersion != CPUM_SAVED_STATE_VERSION 2365 && uVersion != CPUM_SAVED_STATE_VERSION_MEM 2087 2366 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 2088 2367 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2 … … 2107 2386 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR)); 2108 2387 2388 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields; 2389 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6) 2390 paCpumCtxFields = g_aCpumCtxFieldsV16; 2391 uint32_t fLoad = 0; 2392 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM) 2393 fLoad = SSMSTRUCT_FLAGS_MEM_BAND_AID; 2394 2109 2395 /* 2110 2396 * Restore. … … 2113 2399 { 2114 2400 PVMCPU pVCpu = &pVM->aCpus[i]; 2115 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3; 2116 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */ 2117 2118 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper)); 2401 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3; 2402 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */ 2403 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL); 2119 2404 pVCpu->cpum.s.Hyper.cr3 = uCR3; 2120 pVCpu->cpum.s.Hyper. esp = uESP;2405 pVCpu->cpum.s.Hyper.rsp = uRSP; 2121 2406 } 2122 2407 … … 2125 2410 CPUMCTX_VER1_6 cpumctx16; 2126 2411 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest)); 2127 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16)); 2412 SSMR3GetStructEx(pSSM, &cpumctx16, sizeof(cpumctx16), fLoad, 2413 paCpumCtxFields, NULL); 2128 2414 2129 2415 /* Save the old cpumctx state into the new one. */ … … 2142 2428 VERR_SSM_UNEXPECTED_DATA); 2143 2429 } 2144 AssertLogRelMsgReturn( uVersion !=CPUM_SAVED_STATE_VERSION_VER2_02430 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0 2145 2431 || pVM->cCpus == 1, 2146 2432 ("cCpus=%u\n", pVM->cCpus), … … 2159 2445 for (VMCPUID i = 0; i < pVM->cCpus; i++) 2160 2446 { 2161 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest)); 2447 SSMR3GetStructEx(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest), fLoad, 2448 paCpumCtxFields, NULL); 2162 2449 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags); 2163 2450 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged); -
trunk/src/VBox/VMM/VMMR3/PATMSSM.cpp
r41800 r41899 24 24 #include <VBox/vmm/patm.h> 25 25 #include <VBox/vmm/cpum.h> 26 #include <VBox/vmm/cpumctx-v1_6.h> 26 27 #include <VBox/vmm/mm.h> 27 28 #include <VBox/vmm/ssm.h> … … 49 50 * to avoid changing the saved state version for now (will come later). 50 51 */ 51 typedef struct _PATCHINFOSSM52 typedef struct PATCHINFOSSM 52 53 { 53 54 uint32_t uState; -
trunk/src/VBox/VMM/testcase/tstVMStruct.h
r41739 r41899 1298 1298 GEN_CHECK_OFF(PATMPATCHPAGE, cCount); 1299 1299 GEN_CHECK_OFF(PATMPATCHPAGE, cMaxPatches); 1300 GEN_CHECK_OFF(PATMPATCHPAGE, aPatch);1300 GEN_CHECK_OFF(PATMPATCHPAGE, papPatch); 1301 1301 #endif 1302 1302
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