Changeset 41906 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Jun 24, 2012 3:44:03 PM (12 years ago)
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 5 edited
-
HWACCMR0.cpp (modified) (1 diff)
-
HWSVMR0.cpp (modified) (8 diffs)
-
HWSVMR0.h (modified) (2 diffs)
-
HWVMXR0.cpp (modified) (19 diffs)
-
HWVMXR0.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
r41836 r41906 1931 1931 { 1932 1932 Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n" 1933 "rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"1934 "r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"1935 "r14=%016RX64 r15=%016RX64\n"1936 "rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"1937 "cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"1938 "ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"1939 "es={%04x base=%016RX64 limit=%08x flags=%08x}\n"1940 "fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"1941 "gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"1942 "ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"1943 "cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"1944 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"1945 "dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"1946 "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"1947 "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"1948 "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"1949 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"1950 ,1951 pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,1952 pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,1953 pCtx->r14, pCtx->r15,1954 pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,1955 (RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,1956 (RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,1957 (RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,1958 (RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,1959 (RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,1960 (RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,1961 pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,1962 pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],1963 pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],1964 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,1965 (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,1966 (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,1967 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));1933 "rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n" 1934 "r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n" 1935 "r14=%016RX64 r15=%016RX64\n" 1936 "rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n" 1937 "cs={%04x base=%016RX64 limit=%08x flags=%08x}\n" 1938 "ds={%04x base=%016RX64 limit=%08x flags=%08x}\n" 1939 "es={%04x base=%016RX64 limit=%08x flags=%08x}\n" 1940 "fs={%04x base=%016RX64 limit=%08x flags=%08x}\n" 1941 "gs={%04x base=%016RX64 limit=%08x flags=%08x}\n" 1942 "ss={%04x base=%016RX64 limit=%08x flags=%08x}\n" 1943 "cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n" 1944 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n" 1945 "dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n" 1946 "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n" 1947 "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n" 1948 "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n" 1949 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n" 1950 , 1951 pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi, 1952 pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13, 1953 pCtx->r14, pCtx->r15, 1954 pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags, 1955 pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, 1956 pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, 1957 pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, 1958 pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, 1959 pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, 1960 pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, 1961 pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4, 1962 pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3], 1963 pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7], 1964 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl, 1965 pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u, 1966 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u, 1967 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp)); 1968 1968 } 1969 1969 else 1970 1970 Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n" 1971 "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"1972 "cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"1973 "ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"1974 "es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"1975 "fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"1976 "gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"1977 "ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"1978 "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"1979 "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"1980 "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"1981 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"1982 ,1983 pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,1984 pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,1985 (RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],1986 (RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],1987 (RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],1988 (RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],1989 (RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,1990 (RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,1991 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,1992 (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,1993 (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,1994 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));1971 "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n" 1972 "cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n" 1973 "ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n" 1974 "es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n" 1975 "fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n" 1976 "gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n" 1977 "ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n" 1978 "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n" 1979 "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n" 1980 "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n" 1981 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n" 1982 , 1983 pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi, 1984 pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags, 1985 pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1], 1986 pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3], 1987 pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5], 1988 pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7], 1989 pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2, 1990 pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4, 1991 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl, 1992 pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u, 1993 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u, 1994 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp)); 1995 1995 1996 1996 Log(("FPU:\n" -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r41823 r41906 923 923 924 924 /* Set CPL */ 925 pVMCB->guest.u8CPL = pCtx->ss Hid.Attr.n.u2Dpl;925 pVMCB->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl; 926 926 927 927 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */ … … 946 946 #endif 947 947 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */ 948 pVMCB->guest.FS.u64Base = pCtx->fs Hid.u64Base;949 pVMCB->guest.GS.u64Base = pCtx->gs Hid.u64Base;948 pVMCB->guest.FS.u64Base = pCtx->fs.u64Base; 949 pVMCB->guest.GS.u64Base = pCtx->gs.u64Base; 950 950 } 951 951 else … … 1644 1644 * register (yet). 1645 1645 */ 1646 if ( !pCtx->cs Hid.Attr.n.u1Granularity1647 && pCtx->cs Hid.Attr.n.u1Present1648 && pCtx->cs Hid.u32Limit > UINT32_C(0xfffff))1649 { 1650 Assert((pCtx->cs Hid.u32Limit & 0xfff) == 0xfff);1651 pCtx->cs Hid.Attr.n.u1Granularity = 1;1646 if ( !pCtx->cs.Attr.n.u1Granularity 1647 && pCtx->cs.Attr.n.u1Present 1648 && pCtx->cs.u32Limit > UINT32_C(0xfffff)) 1649 { 1650 Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff); 1651 pCtx->cs.Attr.n.u1Granularity = 1; 1652 1652 } 1653 1653 #define SVM_ASSERT_SEL_GRANULARITY(reg) \ 1654 AssertMsg( !pCtx->reg ##Hid.Attr.n.u1Present \1655 || ( pCtx->reg ##Hid.Attr.n.u1Granularity \1656 ? (pCtx->reg ##Hid.u32Limit & 0xfff) == 0xfff \1657 : pCtx->reg ##Hid.u32Limit <= 0xfffff), \1658 ("%#x %#x %#llx\n", pCtx->reg ##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))1654 AssertMsg( !pCtx->reg.Attr.n.u1Present \ 1655 || ( pCtx->reg.Attr.n.u1Granularity \ 1656 ? (pCtx->reg.u32Limit & 0xfff) == 0xfff \ 1657 : pCtx->reg.u32Limit <= 0xfffff), \ 1658 ("%#x %#x %#llx\n", pCtx->reg.u32Limit, pCtx->reg.Attr.u, pCtx->reg.u64Base)) 1659 1659 SVM_ASSERT_SEL_GRANULARITY(ss); 1660 1660 SVM_ASSERT_SEL_GRANULARITY(cs); … … 1672 1672 */ 1673 1673 Assert(!(pVMCB->guest.u8CPL & ~0x3)); 1674 pCtx->ss Hid.Attr.n.u2Dpl = pVMCB->guest.u8CPL & 0x3;1674 pCtx->ss.Attr.n.u2Dpl = pVMCB->guest.u8CPL & 0x3; 1675 1675 1676 1676 /* … … 1775 1775 #ifdef DBGFTRACE_ENABLED /** @todo DTrace */ 1776 1776 RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x at %04:%08RX64 %RX64 %RX64 %RX64", 1777 exitCode, pCtx->cs , pCtx->rip,1777 exitCode, pCtx->cs.Sel, pCtx->rip, 1778 1778 pVMCB->ctrl.u64ExitInfo1, pVMCB->ctrl.u64ExitInfo2, pVMCB->ctrl.ExitIntInfo.au64[0]); 1779 1779 #endif … … 1825 1825 } 1826 1826 /* Return to ring 3 to deal with the debug exit code. */ 1827 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs , pCtx->rip, VBOXSTRICTRC_VAL(rc)));1827 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc))); 1828 1828 break; 1829 1829 } … … 2031 2031 break; 2032 2032 } 2033 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs , (RTGCPTR)pCtx->rip, pCtx->esi));2033 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->esi)); 2034 2034 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event); 2035 2035 goto ResumeExecution; … … 2971 2971 * Only allow 32 & 64 bit code. 2972 2972 */ 2973 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs , &pRegFrame->csHid);2973 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs.Sel, &pRegFrame->cs); 2974 2974 if (enmMode != DISCPUMODE_16BIT) 2975 2975 { -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.h
r41335 r41906 200 200 #define SVM_HIDSEGATTR_SVM2VMX(a) (a & 0xFF) | ((a & 0x0F00) << 4) 201 201 202 #define SVM_WRITE_SELREG(REG, reg) \ 203 { \ 204 pVMCB->guest.REG.u16Sel = pCtx->reg; \ 205 pVMCB->guest.REG.u32Limit = pCtx->reg##Hid.u32Limit; \ 206 pVMCB->guest.REG.u64Base = pCtx->reg##Hid.u64Base; \ 207 pVMCB->guest.REG.u16Attr = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg##Hid.Attr.u); \ 208 } 209 210 #define SVM_READ_SELREG(REG, reg) \ 211 { \ 212 pCtx->reg = pVMCB->guest.REG.u16Sel; \ 213 pCtx->reg##Hid.u32Limit = pVMCB->guest.REG.u32Limit; \ 214 pCtx->reg##Hid.u64Base = pVMCB->guest.REG.u64Base; \ 215 pCtx->reg##Hid.Attr.u = SVM_HIDSEGATTR_SVM2VMX(pVMCB->guest.REG.u16Attr); \ 216 } 202 #define SVM_WRITE_SELREG(REG, reg) \ 203 do \ 204 { \ 205 Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \ 206 Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \ 207 pVMCB->guest.REG.u16Sel = pCtx->reg.Sel; \ 208 pVMCB->guest.REG.u32Limit = pCtx->reg.u32Limit; \ 209 pVMCB->guest.REG.u64Base = pCtx->reg.u64Base; \ 210 pVMCB->guest.REG.u16Attr = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg.Attr.u); \ 211 } while (0) 212 213 #define SVM_READ_SELREG(REG, reg) \ 214 do \ 215 { \ 216 pCtx->reg.Sel = pVMCB->guest.REG.u16Sel; \ 217 pCtx->reg.ValidSel = pVMCB->guest.REG.u16Sel; \ 218 pCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \ 219 pCtx->reg.u32Limit = pVMCB->guest.REG.u32Limit; \ 220 pCtx->reg.u64Base = pVMCB->guest.REG.u64Base; \ 221 pCtx->reg.Attr.u = SVM_HIDSEGATTR_SVM2VMX(pVMCB->guest.REG.u16Attr); \ 222 } while (0) 217 223 218 224 #endif /* IN_RING0 */ … … 222 228 RT_C_DECLS_END 223 229 224 #endif /* ___VMMR0_HWSVMR0_h */225 230 #endif /* !___VMMR0_HWSVMR0_h */ 231 -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r41834 r41906 904 904 /** @todo Check stack limit. */ 905 905 pCtx->sp -= 2; 906 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss , pCtx->sp, pCtx->eflags.u));907 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss Hid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);906 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss.Sel, pCtx->sp, pCtx->eflags.u)); 907 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc); 908 908 pCtx->sp -= 2; 909 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss , pCtx->sp, pCtx->cs));910 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss Hid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);909 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss.Sel, pCtx->sp, pCtx->cs.Sel)); 910 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc); 911 911 pCtx->sp -= 2; 912 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss , pCtx->sp, ip));913 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss Hid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);912 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss.Sel, pCtx->sp, ip)); 913 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc); 914 914 915 915 /* … … 917 917 */ 918 918 pCtx->rip = offset; 919 pCtx->cs 920 pCtx->cs Hid.u64Base= sel << 4;919 pCtx->cs.Sel = sel; 920 pCtx->cs.u64Base = sel << 4; 921 921 pCtx->eflags.u &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC); 922 922 … … 1009 1009 rc = PDMGetInterrupt(pVCpu, &u8Interrupt); 1010 1010 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, 1011 u8Interrupt, u8Interrupt, rc, pCtx->cs , (RTGCPTR)pCtx->rip));1011 u8Interrupt, u8Interrupt, rc, pCtx->cs.Sel, (RTGCPTR)pCtx->rip)); 1012 1012 if (RT_SUCCESS(rc)) 1013 1013 { … … 1642 1642 * DPL of all hidden selector registers must match the current CPL (0). 1643 1643 */ 1644 pCtx->cs Hid.Attr.n.u2Dpl = 0;1645 pCtx->cs Hid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;1646 1647 pCtx->ds Hid.Attr.n.u2Dpl = 0;1648 pCtx->es Hid.Attr.n.u2Dpl = 0;1649 pCtx->fs Hid.Attr.n.u2Dpl = 0;1650 pCtx->gs Hid.Attr.n.u2Dpl = 0;1651 pCtx->ss Hid.Attr.n.u2Dpl = 0;1644 pCtx->cs.Attr.n.u2Dpl = 0; 1645 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC; 1646 1647 pCtx->ds.Attr.n.u2Dpl = 0; 1648 pCtx->es.Attr.n.u2Dpl = 0; 1649 pCtx->fs.Attr.n.u2Dpl = 0; 1650 pCtx->gs.Attr.n.u2Dpl = 0; 1651 pCtx->ss.Attr.n.u2Dpl = 0; 1652 1652 } 1653 1653 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode; 1654 1654 } 1655 1655 else if ( CPUMIsGuestInRealModeEx(pCtx) 1656 && pCtx->cs Hid.u64Base == 0xffff0000)1656 && pCtx->cs.u64Base == 0xffff0000) 1657 1657 { 1658 1658 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */ 1659 pCtx->cs Hid.u64Base = 0xf0000;1660 pCtx->cs =0xf000;1659 pCtx->cs.u64Base = 0xf0000; 1660 pCtx->cs.Sel = 0xf000; 1661 1661 } 1662 1662 } … … 1686 1686 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR) 1687 1687 { 1688 if (pCtx->ldtr == 0)1688 if (pCtx->ldtr.Sel == 0) 1689 1689 { 1690 1690 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0); … … 1696 1696 else 1697 1697 { 1698 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr );1699 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr Hid.u32Limit);1700 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtr Hid.u64Base);1701 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr Hid.Attr.u);1698 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr.Sel); 1699 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit); 1700 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); 1701 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr.Attr.u); 1702 1702 } 1703 1703 AssertRC(rc); … … 1735 1735 else 1736 1736 { 1737 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr );1738 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->tr Hid.u32Limit);1739 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->tr Hid.u64Base);1740 1741 val = pCtx->tr Hid.Attr.u;1737 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr.Sel); 1738 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->tr.u32Limit); 1739 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->tr.u64Base); 1740 1741 val = pCtx->tr.Attr.u; 1742 1742 1743 1743 /* The TSS selector must be busy (REM bugs? see defect #XXXX). */ … … 2076 2076 { 2077 2077 /* Update these as wrmsr might have changed them. */ 2078 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fs Hid.u64Base);2078 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fs.u64Base); 2079 2079 AssertRC(rc); 2080 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gs Hid.u64Base);2080 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gs.u64Base); 2081 2081 AssertRC(rc); 2082 2082 } … … 3215 3215 #endif 3216 3216 3217 Log2(("E%d: New EIP=%x:%RGv\n", (uint32_t)exitReason, pCtx->cs , (RTGCPTR)pCtx->rip));3217 Log2(("E%d: New EIP=%x:%RGv\n", (uint32_t)exitReason, pCtx->cs.Sel, (RTGCPTR)pCtx->rip)); 3218 3218 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification)); 3219 3219 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr)); … … 3233 3233 #ifdef DBGFTRACE_ENABLED /** @todo DTrace later. */ 3234 3234 RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x %016RX64 at %04:%08RX64 %RX64", 3235 exitReason, (uint64_t)exitQualification, pCtx->cs , pCtx->rip, (uint64_t)intInfo);3235 exitReason, (uint64_t)exitQualification, pCtx->cs.Sel, pCtx->rip, (uint64_t)intInfo); 3236 3236 #endif 3237 3237 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x); … … 3445 3445 break; 3446 3446 } 3447 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs , (RTGCPTR)pCtx->rip));3447 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip)); 3448 3448 rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 3449 3449 cbInstr, errCode); … … 3506 3506 } 3507 3507 /* Return to ring 3 to deal with the debug exit code. */ 3508 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs , pCtx->rip, VBOXSTRICTRC_VAL(rc)));3508 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc))); 3509 3509 break; 3510 3510 } … … 3516 3516 if (rc == VINF_EM_RAW_GUEST_TRAP) 3517 3517 { 3518 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs , pCtx->rip));3518 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs.Sel, pCtx->rip)); 3519 3519 rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 3520 3520 cbInstr, errCode); … … 3528 3528 goto ResumeExecution; 3529 3529 } 3530 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs , pCtx->rip, VBOXSTRICTRC_VAL(rc)));3530 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc))); 3531 3531 break; 3532 3532 } … … 3542 3542 || !pVM->hwaccm.s.vmx.pRealModeTSS) 3543 3543 { 3544 Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs , (RTGCPTR)pCtx->rip, errCode));3544 Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, errCode)); 3545 3545 rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 3546 3546 cbInstr, errCode); … … 3552 3552 Assert(CPUMIsGuestInRealModeEx(pCtx)); 3553 3553 3554 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs , (RTGCPTR)pCtx->rip));3554 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip)); 3555 3555 3556 3556 rc2 = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); … … 3695 3695 } 3696 3696 pCtx->ip = aIretFrame[0]; 3697 pCtx->cs = aIretFrame[1]; 3698 pCtx->csHid.u64Base = pCtx->cs << 4; 3697 pCtx->cs.Sel = aIretFrame[1]; 3698 pCtx->cs.ValidSel = aIretFrame[1]; 3699 pCtx->cs.u64Base = (uint32_t)pCtx->cs.Sel << 4; 3699 3700 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) 3700 3701 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask); 3701 3702 pCtx->sp += sizeof(aIretFrame); 3702 3703 3703 LogFlow(("iret to %04x:%x\n", pCtx->cs , pCtx->ip));3704 LogFlow(("iret to %04x:%x\n", pCtx->cs.Sel, pCtx->ip)); 3704 3705 fUpdateRIP = false; 3705 3706 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret); … … 3813 3814 } 3814 3815 3815 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs , (RTGCPTR)pCtx->rip));3816 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip)); 3816 3817 rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 3817 3818 cbInstr, errCode); … … 3827 3828 && pVM->hwaccm.s.vmx.pRealModeTSS) 3828 3829 { 3829 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs , pCtx->eip, errCode));3830 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs.Sel, pCtx->eip, errCode)); 3830 3831 rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 3831 3832 cbInstr, errCode); -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.h
r41330 r41906 217 217 218 218 # define VMX_WRITE_SELREG(REG, reg) \ 219 { \ 220 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG, pCtx->reg); \ 221 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, pCtx->reg##Hid.u32Limit); \ 222 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_##REG##_BASE, pCtx->reg##Hid.u64Base); \ 219 do \ 220 { \ 221 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG, pCtx->reg.Sel); \ 222 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, pCtx->reg.u32Limit); \ 223 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_##REG##_BASE, pCtx->reg.u64Base); \ 223 224 if ((pCtx->eflags.u32 & X86_EFL_VM)) \ 224 225 { \ 225 226 /* Must override this or else VT-x will fail with invalid guest state errors. */ \ 226 227 /* DPL=3, present, code/data, r/w/accessed. */ \ 227 val = (pCtx->reg ##Hid.Attr.u & ~0xFF) | 0xF3;\228 val = (pCtx->reg.Attr.u & ~0xFF) | 0xF3; \ 228 229 } \ 229 230 else \ … … 236 237 } \ 237 238 else \ 238 if ( ( pCtx->reg 239 if ( ( pCtx->reg.Sel \ 239 240 || !CPUMIsGuestInPagedProtectedModeEx(pCtx) \ 240 || (!pCtx->cs Hid.Attr.n.u1DefBig && !CPUMIsGuestIn64BitCodeEx(pCtx))\241 || (!pCtx->cs.Attr.n.u1DefBig && !CPUMIsGuestIn64BitCodeEx(pCtx)) \ 241 242 ) \ 242 && pCtx->reg ##Hid.Attr.n.u1Present == 1)\243 && pCtx->reg.Attr.n.u1Present == 1) \ 243 244 { \ 244 val = pCtx->reg ##Hid.Attr.u | X86_SEL_TYPE_ACCESSED;\245 val = pCtx->reg.Attr.u | X86_SEL_TYPE_ACCESSED; \ 245 246 } \ 246 247 else \ … … 248 249 \ 249 250 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, val); \ 250 } 251 } while (0) 251 252 252 253 # define VMX_READ_SELREG(REG, reg) \ 253 { \ 254 VMXReadCachedVMCS(VMX_VMCS16_GUEST_FIELD_##REG, &val); \ 255 pCtx->reg = val; \ 256 VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &val); \ 257 pCtx->reg##Hid.u32Limit = val; \ 258 VMXReadCachedVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &val); \ 259 pCtx->reg##Hid.u64Base = val; \ 260 VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \ 261 pCtx->reg##Hid.Attr.u = val; \ 262 } 254 do \ 255 { \ 256 VMXReadCachedVMCS(VMX_VMCS16_GUEST_FIELD_##REG, &val); \ 257 pCtx->reg.Sel = val; \ 258 pCtx->reg.ValidSel = val; \ 259 pCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \ 260 VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &val); \ 261 pCtx->reg.u32Limit = val; \ 262 VMXReadCachedVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &val); \ 263 pCtx->reg.u64Base = val; \ 264 VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \ 265 pCtx->reg.Attr.u = val; \ 266 } while (0) 263 267 264 268 /* Don't read from the cache in this macro; used only in case of failure where the cache is out of sync. */ 265 269 # define VMX_LOG_SELREG(REG, szSelReg, val) \ 266 { \ 267 VMXReadVMCS(VMX_VMCS16_GUEST_FIELD_##REG, &(val)); \ 268 Log(("%s Selector %x\n", szSelReg, (val))); \ 269 VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &(val)); \ 270 Log(("%s Limit %x\n", szSelReg, (val))); \ 271 VMXReadVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &(val)); \ 272 Log(("%s Base %RX64\n", szSelReg, (uint64_t)(val))); \ 273 VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val)); \ 274 Log(("%s Attributes %x\n", szSelReg, (val))); \ 275 } 270 do \ 271 { \ 272 VMXReadVMCS(VMX_VMCS16_GUEST_FIELD_##REG, &(val)); \ 273 Log(("%s Selector %x\n", szSelReg, (val))); \ 274 VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &(val)); \ 275 Log(("%s Limit %x\n", szSelReg, (val))); \ 276 VMXReadVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &(val)); \ 277 Log(("%s Base %RX64\n", szSelReg, (uint64_t)(val))); \ 278 VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val)); \ 279 Log(("%s Attributes %x\n", szSelReg, (val))); \ 280 } while (0) 276 281 277 282 /**
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