VirtualBox

Changeset 41906 in vbox for trunk/src/VBox/VMM/VMMRZ


Ignore:
Timestamp:
Jun 24, 2012 3:44:03 PM (13 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
78759
Message:

CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMRZ/DBGFRZ.cpp

    r41823 r41906  
    4646{
    4747#ifdef IN_RC
    48     const bool fInHyper = !(pRegFrame->ss & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
     48    const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
    4949#else
    5050    const bool fInHyper = false;
     
    6666                pVCpu->dbgf.s.fSingleSteppingRaw = false;
    6767                LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
    68                          pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs, pRegFrame->rip));
     68                         pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
    6969
    7070                return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
     
    8181    {
    8282        pVCpu->dbgf.s.fSingleSteppingRaw = false;
    83         LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs, pRegFrame->rip));
     83        LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
    8484        return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
    8585    }
     
    9191     */
    9292    AssertMsg(uDr6 & X86_DR6_BS, ("hey! we're not doing guest BPs yet! dr6=%RTreg %04x:%RGv\n",
    93                                   uDr6, pRegFrame->cs, pRegFrame->rip));
     93                                  uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
    9494#endif
    9595
    96     LogFlow(("DBGFRZTrap01Handler: guest debug event %RTreg at %04x:%RGv!\n", uDr6, pRegFrame->cs, pRegFrame->rip));
     96    LogFlow(("DBGFRZTrap01Handler: guest debug event %RTreg at %04x:%RGv!\n", uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
    9797    return fInHyper ? VERR_DBGF_HYPER_DB_XCPT : VINF_EM_RAW_GUEST_TRAP;
    9898}
     
    113113{
    114114#ifdef IN_RC
    115     const bool fInHyper = !(pRegFrame->ss & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
     115    const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
    116116#else
    117117    const bool fInHyper = false;
     
    125125    {
    126126        RTGCPTR pPc;
    127         int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
     127        int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
    128128#ifdef IN_RC
    129129                                              pRegFrame->eip - 1,
     
    143143
    144144                LogFlow(("DBGFRZTrap03Handler: hit breakpoint %d at %RGv (%04x:%RGv) cHits=0x%RX64\n",
    145                          pVM->dbgf.s.aBreakpoints[iBp].iBp, pPc, pRegFrame->cs, pRegFrame->rip,
     145                         pVM->dbgf.s.aBreakpoints[iBp].iBp, pPc, pRegFrame->cs.Sel, pRegFrame->rip,
    146146                         pVM->dbgf.s.aBreakpoints[iBp].cHits));
    147147                return fInHyper
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