Index: trunk/src/VBox/Disassembler/DisasmReg.cpp
===================================================================
--- trunk/src/VBox/Disassembler/DisasmReg.cpp	(revision 41905)
+++ trunk/src/VBox/Disassembler/DisasmReg.cpp	(revision 41906)
@@ -185,10 +185,10 @@
 static const unsigned g_aRegHidSegIndex[] =
 {
-    RT_OFFSETOF(CPUMCTXCORE, esHid),         /* DISSELREG_ES */
-    RT_OFFSETOF(CPUMCTXCORE, csHid),         /* DISSELREG_CS */
-    RT_OFFSETOF(CPUMCTXCORE, ssHid),         /* DISSELREG_SS */
-    RT_OFFSETOF(CPUMCTXCORE, dsHid),         /* DISSELREG_DS */
-    RT_OFFSETOF(CPUMCTXCORE, fsHid),         /* DISSELREG_FS */
-    RT_OFFSETOF(CPUMCTXCORE, gsHid)          /* DISSELREG_GS */
+    RT_OFFSETOF(CPUMCTXCORE, es),         /* DISSELREG_ES */
+    RT_OFFSETOF(CPUMCTXCORE, cs),         /* DISSELREG_CS */
+    RT_OFFSETOF(CPUMCTXCORE, ss),         /* DISSELREG_SS */
+    RT_OFFSETOF(CPUMCTXCORE, ds),         /* DISSELREG_DS */
+    RT_OFFSETOF(CPUMCTXCORE, fs),         /* DISSELREG_FS */
+    RT_OFFSETOF(CPUMCTXCORE, gs)          /* DISSELREG_GS */
 };
 
Index: trunk/src/VBox/VMM/Makefile.kmk
===================================================================
--- trunk/src/VBox/VMM/Makefile.kmk	(revision 41905)
+++ trunk/src/VBox/VMM/Makefile.kmk	(revision 41906)
@@ -683,2 +683,6 @@
 IEMAllCImplStrInstr.cpp.o IEMAllCImplStrInstr.cpp.obj: IEMAll.o
 
+# Alias the switcher templates.
+PAEand32Bit.o PAEand32Bit.obj:                 PAETo32Bit.o   PAEToPAE.o   32BitTo32Bit.o PAETo32Bit.o
+LegacyandAMD64.o LegacyandAMD64.obj:           32BitToAMD64.o PAEToAMD64.o
+AMD64andLegacy.o AMD64andLegacy.obj:           AMD64To32Bit.o AMD64ToPAE.o
Index: trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 41906)
@@ -142,5 +142,5 @@
 VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
 {
-    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
+    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs.Sel = SelCS;
 }
 
@@ -148,5 +148,5 @@
 VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
 {
-    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
+    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds.Sel = SelDS;
 }
 
@@ -154,5 +154,5 @@
 VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
 {
-    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
+    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es.Sel = SelES;
 }
 
@@ -160,5 +160,5 @@
 VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
 {
-    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
+    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs.Sel = SelFS;
 }
 
@@ -166,5 +166,5 @@
 VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
 {
-    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
+    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs.Sel = SelGS;
 }
 
@@ -172,5 +172,5 @@
 VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
 {
-    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
+    pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss.Sel = SelSS;
 }
 
@@ -197,5 +197,5 @@
 VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
 {
-    pVCpu->cpum.s.Hyper.tr = SelTR;
+    pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
 }
 
@@ -203,5 +203,5 @@
 VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
 {
-    pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
+    pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
 }
 
@@ -251,5 +251,5 @@
 VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
+    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs.Sel;
 }
 
@@ -257,5 +257,5 @@
 VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
+    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds.Sel;
 }
 
@@ -263,5 +263,5 @@
 VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
+    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es.Sel;
 }
 
@@ -269,5 +269,5 @@
 VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
+    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs.Sel;
 }
 
@@ -275,5 +275,5 @@
 VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
+    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs.Sel;
 }
 
@@ -281,5 +281,5 @@
 VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
+    return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss.Sel;
 }
 
@@ -369,5 +369,5 @@
 VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Hyper.ldtr;
+    return pVCpu->cpum.s.Hyper.ldtr.Sel;
 }
 
@@ -491,5 +491,5 @@
 VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
 {
-    pVCpu->cpum.s.Guest.tr  = tr;
+    pVCpu->cpum.s.Guest.tr.Sel  = tr;
     pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
     return VINF_SUCCESS;
@@ -498,5 +498,5 @@
 VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
 {
-    pVCpu->cpum.s.Guest.ldtr = ldtr;
+    pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
     pVCpu->cpum.s.fChanged  |= CPUM_CHANGED_LDTR;
     return VINF_SUCCESS;
@@ -682,5 +682,5 @@
 VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
 {
-    pVCpu->cpum.s.Guest.ss = ss;
+    pVCpu->cpum.s.Guest.ss.Sel = ss;
     return VINF_SUCCESS;
 }
@@ -689,5 +689,5 @@
 VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
 {
-    pVCpu->cpum.s.Guest.cs = cs;
+    pVCpu->cpum.s.Guest.cs.Sel = cs;
     return VINF_SUCCESS;
 }
@@ -696,5 +696,5 @@
 VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
 {
-    pVCpu->cpum.s.Guest.ds = ds;
+    pVCpu->cpum.s.Guest.ds.Sel = ds;
     return VINF_SUCCESS;
 }
@@ -703,5 +703,5 @@
 VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
 {
-    pVCpu->cpum.s.Guest.es = es;
+    pVCpu->cpum.s.Guest.es.Sel = es;
     return VINF_SUCCESS;
 }
@@ -710,5 +710,5 @@
 VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
 {
-    pVCpu->cpum.s.Guest.fs = fs;
+    pVCpu->cpum.s.Guest.fs.Sel = fs;
     return VINF_SUCCESS;
 }
@@ -717,5 +717,5 @@
 VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
 {
-    pVCpu->cpum.s.Guest.gs = gs;
+    pVCpu->cpum.s.Guest.gs.Sel = gs;
     return VINF_SUCCESS;
 }
@@ -864,9 +864,9 @@
 
         case MSR_K8_FS_BASE:
-            *puValue = pVCpu->cpum.s.Guest.fsHid.u64Base;
+            *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
             break;
 
         case MSR_K8_GS_BASE:
-            *puValue = pVCpu->cpum.s.Guest.gsHid.u64Base;
+            *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
             break;
 
@@ -1142,9 +1142,9 @@
 
         case MSR_K8_FS_BASE:
-            pVCpu->cpum.s.Guest.fsHid.u64Base   = uValue;
+            pVCpu->cpum.s.Guest.fs.u64Base      = uValue;
             break;
 
         case MSR_K8_GS_BASE:
-            pVCpu->cpum.s.Guest.gsHid.u64Base   = uValue;
+            pVCpu->cpum.s.Guest.gs.u64Base      = uValue;
             break;
 
@@ -1189,6 +1189,6 @@
 {
     if (pHidden)
-        *pHidden = pVCpu->cpum.s.Guest.trHid;
-    return pVCpu->cpum.s.Guest.tr;
+        *pHidden = pVCpu->cpum.s.Guest.tr;
+    return pVCpu->cpum.s.Guest.tr.Sel;
 }
 
@@ -1196,5 +1196,5 @@
 VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.cs;
+    return pVCpu->cpum.s.Guest.cs.Sel;
 }
 
@@ -1202,5 +1202,5 @@
 VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.ds;
+    return pVCpu->cpum.s.Guest.ds.Sel;
 }
 
@@ -1208,5 +1208,5 @@
 VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.es;
+    return pVCpu->cpum.s.Guest.es.Sel;
 }
 
@@ -1214,5 +1214,5 @@
 VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.fs;
+    return pVCpu->cpum.s.Guest.fs.Sel;
 }
 
@@ -1220,5 +1220,5 @@
 VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.gs;
+    return pVCpu->cpum.s.Guest.gs.Sel;
 }
 
@@ -1226,5 +1226,5 @@
 VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.ss;
+    return pVCpu->cpum.s.Guest.ss.Sel;
 }
 
@@ -1232,5 +1232,5 @@
 VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
 {
-    return pVCpu->cpum.s.Guest.ldtr;
+    return pVCpu->cpum.s.Guest.ldtr.Sel;
 }
 
@@ -2454,5 +2454,5 @@
         {
             if (!pCtxCore->eflags.Bits.u1VM)
-                cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
+                cpl = pCtxCore->ss.Attr.n.u2Dpl;
             else
                 cpl = 3; /* REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
@@ -2470,5 +2470,5 @@
              * See section 4.11.1 in the AMD manual.
              */
-            cpl = (pCtxCore->ss & X86_SEL_RPL);
+            cpl = (pCtxCore->ss.Sel & X86_SEL_RPL);
 #ifndef IN_RING0
             if (cpl == 1)
Index: trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41906)
@@ -384,11 +384,11 @@
 #else
 /** @todo Get the CPU mode as well while we're at it! */
-    int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss, pCtxCore->cs,
-                                          &pCtxCore->csHid, pCtxCore->rip, &GCPtrInstr);
+    int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel,
+                                          &pCtxCore->cs, pCtxCore->rip, &GCPtrInstr);
 #endif
     if (RT_FAILURE(rc))
     {
         Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
-             pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
+             pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
         return rc;
     }
@@ -415,5 +415,5 @@
                                    PDISCPUSTATE pDis, unsigned *pcbInstr)
 {
-    DISCPUMODE enmCpuMode = SELMGetCpuModeFromSelector(pVCpu, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid);
+    DISCPUMODE enmCpuMode = SELMGetCpuModeFromSelector(pVCpu, pCtxCore->eflags, pCtxCore->cs.Sel, (PCPUMSELREGHID)&pCtxCore->cs);
     /** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
      *        \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
@@ -461,5 +461,5 @@
         uint32_t     cbOp;
         PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
-        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
+        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs.Sel, &pRegFrame->cs);
         rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
         if (RT_SUCCESS(rc))
@@ -515,5 +515,5 @@
         uint32_t     cbOp;
         PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
-        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
+        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs.Sel, &pRegFrame->cs);
         rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
         if (RT_SUCCESS(rc))
@@ -625,6 +625,6 @@
     AssertRCReturn(rc, VERR_EM_INTERPRETER);
 
-    pRegFrame->eip = eip & 0xffff;
-    pRegFrame->cs  = cs;
+    pRegFrame->eip    = eip & 0xffff;
+    pRegFrame->cs.Sel = cs;
 
     /* Mask away all reserved bits */
@@ -635,10 +635,10 @@
     Assert((pRegFrame->eflags.u32 & (X86_EFL_IF|X86_EFL_IOPL)) == X86_EFL_IF);
 
-    pRegFrame->esp = esp;
-    pRegFrame->ss  = ss;
-    pRegFrame->ds  = ds;
-    pRegFrame->es  = es;
-    pRegFrame->fs  = fs;
-    pRegFrame->gs  = gs;
+    pRegFrame->esp      = esp;
+    pRegFrame->ss.Sel   = ss;
+    pRegFrame->ds.Sel   = ds;
+    pRegFrame->es.Sel   = es;
+    pRegFrame->fs.Sel   = fs;
+    pRegFrame->gs.Sel   = gs;
 
     return VINF_SUCCESS;
@@ -926,5 +926,5 @@
             {
                 /* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
-                if (pRegFrame->csHid.Attr.n.u1Long)
+                if (pRegFrame->cs.Attr.n.u1Long)
                 {
                     AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
@@ -1535,5 +1535,5 @@
 
             /* Read stack value first */
-            if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == DISCPUMODE_16BIT)
+            if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, &pRegFrame->ss) == DISCPUMODE_16BIT)
                 return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
 
@@ -2202,5 +2202,5 @@
     if (!(pDis->fPrefix & DISPREFIX_REP))
     {
-        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
+        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
 
         rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
@@ -2247,5 +2247,5 @@
         }
 
-        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
+        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
         /* Access verification first; we currently can't recover properly from traps inside this instruction */
         rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
Index: trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 41906)
@@ -632,5 +632,5 @@
     IEMMODE enmMode = CPUMIsGuestIn64BitCodeEx(pCtx)
                     ? IEMMODE_64BIT
-                    : pCtx->csHid.Attr.n.u1DefBig /** @todo check if this is correct... */
+                    : pCtx->cs.Attr.n.u1DefBig /** @todo check if this is correct... */
                     ? IEMMODE_32BIT
                     : IEMMODE_16BIT;
@@ -684,9 +684,9 @@
     {
         uint32_t GCPtrPC32 = pCtx->eip;
-        AssertMsg(!(GCPtrPC32 & ~(uint32_t)UINT16_MAX) || pIemCpu->enmCpuMode == IEMMODE_32BIT, ("%04x:%RX64\n", pCtx->cs, pCtx->rip));
-        if (GCPtrPC32 > pCtx->csHid.u32Limit)
+        AssertMsg(!(GCPtrPC32 & ~(uint32_t)UINT16_MAX) || pIemCpu->enmCpuMode == IEMMODE_32BIT, ("%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip));
+        if (GCPtrPC32 > pCtx->cs.u32Limit)
             return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
-        cbToTryRead = pCtx->csHid.u32Limit - GCPtrPC32 + 1;
-        GCPtrPC = pCtx->csHid.u64Base + GCPtrPC32;
+        cbToTryRead = pCtx->cs.u32Limit - GCPtrPC32 + 1;
+        GCPtrPC = pCtx->cs.u64Base + GCPtrPC32;
     }
 
@@ -789,10 +789,10 @@
         Assert(!(GCPtrNext32 & ~(uint32_t)UINT16_MAX) || pIemCpu->enmCpuMode == IEMMODE_32BIT);
         GCPtrNext32 += pIemCpu->cbOpcode;
-        if (GCPtrNext32 > pCtx->csHid.u32Limit)
+        if (GCPtrNext32 > pCtx->cs.u32Limit)
             return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
-        cbToTryRead = pCtx->csHid.u32Limit - GCPtrNext32 + 1;
+        cbToTryRead = pCtx->cs.u32Limit - GCPtrNext32 + 1;
         if (cbToTryRead < cbMin - cbLeft)
             return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
-        GCPtrNext = pCtx->csHid.u64Base + GCPtrNext32;
+        GCPtrNext = pCtx->cs.u64Base + GCPtrNext32;
     }
 
@@ -1590,5 +1590,5 @@
     *pSelSS = 0; /* make gcc happy */
 
-    switch (pCtx->trHid.Attr.n.u4Type)
+    switch (pCtx->tr.Attr.n.u4Type)
     {
         /*
@@ -1599,12 +1599,12 @@
         {
             uint32_t off = uCpl * 4 + 2;
-            if (off + 4 > pCtx->trHid.u32Limit)
+            if (off + 4 > pCtx->tr.u32Limit)
             {
-                Log(("LoadStackFromTss32Or16: out of bounds! uCpl=%d, u32Limit=%#x TSS16\n", uCpl, pCtx->trHid.u32Limit));
+                Log(("LoadStackFromTss32Or16: out of bounds! uCpl=%d, u32Limit=%#x TSS16\n", uCpl, pCtx->tr.u32Limit));
                 return iemRaiseTaskSwitchFaultCurrentTSS(pIemCpu);
             }
 
             uint32_t u32Tmp = 0; /* gcc maybe... */
-            rcStrict = iemMemFetchSysU32(pIemCpu, &u32Tmp, UINT8_MAX, pCtx->trHid.u64Base + off);
+            rcStrict = iemMemFetchSysU32(pIemCpu, &u32Tmp, UINT8_MAX, pCtx->tr.u64Base + off);
             if (rcStrict == VINF_SUCCESS)
             {
@@ -1623,12 +1623,12 @@
         {
             uint32_t off = uCpl * 8 + 4;
-            if (off + 7 > pCtx->trHid.u32Limit)
+            if (off + 7 > pCtx->tr.u32Limit)
             {
-                Log(("LoadStackFromTss32Or16: out of bounds! uCpl=%d, u32Limit=%#x TSS16\n", uCpl, pCtx->trHid.u32Limit));
+                Log(("LoadStackFromTss32Or16: out of bounds! uCpl=%d, u32Limit=%#x TSS16\n", uCpl, pCtx->tr.u32Limit));
                 return iemRaiseTaskSwitchFaultCurrentTSS(pIemCpu);
             }
 
             uint64_t u64Tmp;
-            rcStrict = iemMemFetchSysU64(pIemCpu, &u64Tmp, UINT8_MAX, pCtx->trHid.u64Base + off);
+            rcStrict = iemMemFetchSysU64(pIemCpu, &u64Tmp, UINT8_MAX, pCtx->tr.u64Base + off);
             if (rcStrict == VINF_SUCCESS)
             {
@@ -1714,5 +1714,5 @@
 
     pu16Frame[2] = (uint16_t)pCtx->eflags.u;
-    pu16Frame[1] = (uint16_t)pCtx->cs;
+    pu16Frame[1] = (uint16_t)pCtx->cs.Sel;
     pu16Frame[0] = pCtx->ip + cbInstr;
     rcStrict = iemMemStackPushCommitSpecial(pIemCpu, pu16Frame, uNewRsp);
@@ -1724,6 +1724,8 @@
      * adjustments.
      */
-    pCtx->cs               = Idte.sel;
-    pCtx->csHid.u64Base    = (uint32_t)Idte.sel << 4;
+    pCtx->cs.Sel           = Idte.sel;
+    pCtx->cs.ValidSel      = Idte.sel;
+    pCtx->cs.fFlags        = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.u64Base       = (uint32_t)Idte.sel << 4;
     /** @todo do we load attribs and limit as well? Should we check against limit like far jump? */
     pCtx->rip              = Idte.off;
@@ -1956,8 +1958,8 @@
         uStackFrame.pu32[0] = (fFlags & (IEM_XCPT_FLAGS_T_SOFT_INT | IEM_XCPT_FLAGS_BP_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
                             ? pCtx->eip + cbInstr : pCtx->eip;
-        uStackFrame.pu32[1] = (pCtx->cs & ~X86_SEL_RPL) | pIemCpu->uCpl;
+        uStackFrame.pu32[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) | pIemCpu->uCpl;
         uStackFrame.pu32[2] = pCtx->eflags.u;
         uStackFrame.pu32[3] = pCtx->esp;
-        uStackFrame.pu32[4] = pCtx->ss;
+        uStackFrame.pu32[4] = pCtx->ss.Sel;
         rcStrict = iemMemCommitAndUnmap(pIemCpu, pvStackFrame, IEM_ACCESS_STACK_W | IEM_ACCESS_WHAT_SYS);
         if (rcStrict != VINF_SUCCESS)
@@ -1985,10 +1987,12 @@
 
         /*
-         * Start commint the register changes (joins with the DPL=CPL branch).
+         * Start comitting the register changes (joins with the DPL=CPL branch).
          */
-        pCtx->ss                = NewSS;
-        pCtx->ssHid.u32Limit    = cbLimitSS;
-        pCtx->ssHid.u64Base     = X86DESC_BASE(DescSS.Legacy);
-        pCtx->ssHid.Attr.u      = X86DESC_GET_HID_ATTR(DescSS.Legacy);
+        pCtx->ss.Sel            = NewSS;
+        pCtx->ss.ValidSel       = NewSS;
+        pCtx->ss.fFlags         = CPUMSELREG_FLAGS_VALID;
+        pCtx->ss.u32Limit       = cbLimitSS;
+        pCtx->ss.u64Base        = X86DESC_BASE(DescSS.Legacy);
+        pCtx->ss.Attr.u         = X86DESC_GET_HID_ATTR(DescSS.Legacy);
         pCtx->rsp               = uNewEsp - cbStackFrame; /** @todo Is the high word cleared for 16-bit stacks and/or interrupt handlers? */
         pIemCpu->uCpl           = uNewCpl;
@@ -2011,5 +2015,5 @@
         uStackFrame.pu32[0] = (fFlags & (IEM_XCPT_FLAGS_T_SOFT_INT | IEM_XCPT_FLAGS_BP_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
                             ? pCtx->eip + cbInstr : pCtx->eip;
-        uStackFrame.pu32[1] = (pCtx->cs & ~X86_SEL_RPL) | pIemCpu->uCpl;
+        uStackFrame.pu32[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) | pIemCpu->uCpl;
         uStackFrame.pu32[2] = pCtx->eflags.u;
         rcStrict = iemMemCommitAndUnmap(pIemCpu, pvStackFrame, IEM_ACCESS_STACK_W); /* don't use the commit here */
@@ -2033,8 +2037,10 @@
 
     /* ... register committing continues. */
-    pCtx->cs                = (NewCS & ~X86_SEL_RPL) | uNewCpl;
-    pCtx->csHid.u32Limit    = cbLimitCS;
-    pCtx->csHid.u64Base     = X86DESC_BASE(DescCS.Legacy);
-    pCtx->csHid.Attr.u      = X86DESC_GET_HID_ATTR(DescCS.Legacy);
+    pCtx->cs.Sel            = (NewCS & ~X86_SEL_RPL) | uNewCpl;
+    pCtx->cs.ValidSel       = (NewCS & ~X86_SEL_RPL) | uNewCpl;
+    pCtx->cs.fFlags         = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.u32Limit       = cbLimitCS;
+    pCtx->cs.u64Base        = X86DESC_BASE(DescCS.Legacy);
+    pCtx->cs.Attr.u         = X86DESC_GET_HID_ATTR(DescCS.Legacy);
 
     pCtx->rip               = uNewEip;
@@ -2138,9 +2144,9 @@
     if (pIemCpu->cXcptRecursions == 0)
         Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx\n",
-             u8Vector, pCtx->cs, pCtx->rip, cbInstr, fFlags, uErr, uCr2));
+             u8Vector, pCtx->cs.Sel, pCtx->rip, cbInstr, fFlags, uErr, uCr2));
     else
     {
         Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx; prev=%#x depth=%d flags=%#x\n",
-             u8Vector, pCtx->cs, pCtx->rip, cbInstr, fFlags, uErr, uCr2, pIemCpu->uCurXcpt, pIemCpu->cXcptRecursions + 1, fPrevXcpt));
+             u8Vector, pCtx->cs.Sel, pCtx->rip, cbInstr, fFlags, uErr, uCr2, pIemCpu->uCurXcpt, pIemCpu->cXcptRecursions + 1, fPrevXcpt));
 
         /** @todo double and tripple faults. */
@@ -2221,5 +2227,5 @@
     pIemCpu->fCurXcpt = fPrevXcpt;
     LogFlow(("iemRaiseXcptOrInt: returns %Rrc (vec=%#x); cs:rip=%04x:%RGv ss:rsp=%04x:%RGv\n",
-             VBOXSTRICTRC_VAL(rcStrict), u8Vector, pCtx->cs, pCtx->rip, pCtx->ss, pCtx->esp));
+             VBOXSTRICTRC_VAL(rcStrict), u8Vector, pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->esp));
     return rcStrict;
 }
@@ -2268,5 +2274,5 @@
 {
     return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR,
-                             pIemCpu->CTX_SUFF(pCtx)->tr, 0);
+                             pIemCpu->CTX_SUFF(pCtx)->tr.Sel, 0);
 }
 
@@ -2642,28 +2648,4 @@
     switch (iSegReg)
     {
-        case X86_SREG_ES: return &pCtx->esHid;
-        case X86_SREG_CS: return &pCtx->csHid;
-        case X86_SREG_SS: return &pCtx->ssHid;
-        case X86_SREG_DS: return &pCtx->dsHid;
-        case X86_SREG_FS: return &pCtx->fsHid;
-        case X86_SREG_GS: return &pCtx->gsHid;
-    }
-    AssertFailedReturn(NULL);
-}
-
-
-/**
- * Gets a reference (pointer) to the specified segment register (the selector
- * value).
- *
- * @returns Pointer to the selector variable.
- * @param   pIemCpu             The per CPU data.
- * @param   iSegReg             The segment register.
- */
-static uint16_t *iemSRegRef(PIEMCPU pIemCpu, uint8_t iSegReg)
-{
-    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
-    switch (iSegReg)
-    {
         case X86_SREG_ES: return &pCtx->es;
         case X86_SREG_CS: return &pCtx->cs;
@@ -2678,4 +2660,28 @@
 
 /**
+ * Gets a reference (pointer) to the specified segment register (the selector
+ * value).
+ *
+ * @returns Pointer to the selector variable.
+ * @param   pIemCpu             The per CPU data.
+ * @param   iSegReg             The segment register.
+ */
+static uint16_t *iemSRegRef(PIEMCPU pIemCpu, uint8_t iSegReg)
+{
+    PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
+    switch (iSegReg)
+    {
+        case X86_SREG_ES: return &pCtx->es.Sel;
+        case X86_SREG_CS: return &pCtx->cs.Sel;
+        case X86_SREG_SS: return &pCtx->ss.Sel;
+        case X86_SREG_DS: return &pCtx->ds.Sel;
+        case X86_SREG_FS: return &pCtx->fs.Sel;
+        case X86_SREG_GS: return &pCtx->gs.Sel;
+    }
+    AssertFailedReturn(NULL);
+}
+
+
+/**
  * Fetches the selector value of a segment register.
  *
@@ -2689,10 +2695,10 @@
     switch (iSegReg)
     {
-        case X86_SREG_ES: return pCtx->es;
-        case X86_SREG_CS: return pCtx->cs;
-        case X86_SREG_SS: return pCtx->ss;
-        case X86_SREG_DS: return pCtx->ds;
-        case X86_SREG_FS: return pCtx->fs;
-        case X86_SREG_GS: return pCtx->gs;
+        case X86_SREG_ES: return pCtx->es.Sel;
+        case X86_SREG_CS: return pCtx->cs.Sel;
+        case X86_SREG_SS: return pCtx->ss.Sel;
+        case X86_SREG_DS: return pCtx->ds.Sel;
+        case X86_SREG_FS: return pCtx->fs.Sel;
+        case X86_SREG_GS: return pCtx->gs.Sel;
     }
     AssertFailedReturn(0xffff);
@@ -2842,5 +2848,5 @@
         {
             uint16_t uNewIp = pCtx->ip + offNextInstr + pIemCpu->offOpcode;
-            if (   uNewIp > pCtx->csHid.u32Limit
+            if (   uNewIp > pCtx->cs.u32Limit
                 && pIemCpu->enmCpuMode != IEMMODE_64BIT) /* no need to check for non-canonical. */
                 return iemRaiseGeneralProtectionFault0(pIemCpu);
@@ -2855,5 +2861,5 @@
 
             uint32_t uNewEip = pCtx->eip + offNextInstr + pIemCpu->offOpcode;
-            if (uNewEip > pCtx->csHid.u32Limit)
+            if (uNewEip > pCtx->cs.u32Limit)
                 return iemRaiseGeneralProtectionFault0(pIemCpu);
             pCtx->rip = uNewEip;
@@ -2895,5 +2901,5 @@
 
     uint16_t uNewIp = pCtx->ip + offNextInstr + pIemCpu->offOpcode;
-    if (   uNewIp > pCtx->csHid.u32Limit
+    if (   uNewIp > pCtx->cs.u32Limit
         && pIemCpu->enmCpuMode != IEMMODE_64BIT) /* no need to check for non-canonical. */
         return iemRaiseGeneralProtectionFault0(pIemCpu);
@@ -2925,5 +2931,5 @@
 
         uint32_t uNewEip = pCtx->eip + offNextInstr + pIemCpu->offOpcode;
-        if (uNewEip > pCtx->csHid.u32Limit)
+        if (uNewEip > pCtx->cs.u32Limit)
             return iemRaiseGeneralProtectionFault0(pIemCpu);
         pCtx->rip = uNewEip;
@@ -2959,5 +2965,5 @@
         {
             Assert(uNewRip <= UINT16_MAX);
-            if (   uNewRip > pCtx->csHid.u32Limit
+            if (   uNewRip > pCtx->cs.u32Limit
                 && pIemCpu->enmCpuMode != IEMMODE_64BIT) /* no need to check for non-canonical. */
                 return iemRaiseGeneralProtectionFault0(pIemCpu);
@@ -2973,5 +2979,5 @@
             Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT);
 
-            if (uNewRip > pCtx->csHid.u32Limit)
+            if (uNewRip > pCtx->cs.u32Limit)
                 return iemRaiseGeneralProtectionFault0(pIemCpu);
             pCtx->rip = uNewRip;
@@ -3004,7 +3010,7 @@
 DECLINLINE(RTGCPTR) iemRegGetEffRsp(PCCPUMCTX pCtx)
 {
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         return pCtx->rsp;
-    if (pCtx->ssHid.Attr.n.u1DefBig)
+    if (pCtx->ss.Attr.n.u1DefBig)
         return pCtx->esp;
     return pCtx->sp;
@@ -3062,7 +3068,7 @@
 DECLINLINE(void) iemRegAddToRsp(PCPUMCTX pCtx, uint8_t cbToAdd)
 {
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         pCtx->rsp += cbToAdd;
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         pCtx->esp += cbToAdd;
     else
@@ -3080,7 +3086,7 @@
 DECLINLINE(void) iemRegSubFromRsp(PCPUMCTX pCtx, uint8_t cbToSub)
 {
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         pCtx->rsp -= cbToSub;
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         pCtx->esp -= cbToSub;
     else
@@ -3098,7 +3104,7 @@
 DECLINLINE(void) iemRegAddToRspEx(PRTUINT64U pTmpRsp, uint8_t cbToAdd, PCCPUMCTX pCtx)
 {
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         pTmpRsp->u           += cbToAdd;
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         pTmpRsp->DWords.dw0  += cbToAdd;
     else
@@ -3116,7 +3122,7 @@
 DECLINLINE(void) iemRegSubFromRspEx(PRTUINT64U pTmpRsp, uint8_t cbToSub, PCCPUMCTX pCtx)
 {
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         pTmpRsp->u          -= cbToSub;
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         pTmpRsp->DWords.dw0 -= cbToSub;
     else
@@ -3140,7 +3146,7 @@
     uTmpRsp.u = pCtx->rsp;
 
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         GCPtrTop = uTmpRsp.u            -= cbItem;
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         GCPtrTop = uTmpRsp.DWords.dw0   -= cbItem;
     else
@@ -3166,10 +3172,10 @@
     uTmpRsp.u = pCtx->rsp;
 
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
     {
         GCPtrTop = uTmpRsp.u;
         uTmpRsp.u += cbItem;
     }
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
     {
         GCPtrTop = uTmpRsp.DWords.dw0;
@@ -3199,7 +3205,7 @@
     RTGCPTR GCPtrTop;
 
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
         GCPtrTop = pTmpRsp->u          -= cbItem;
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         GCPtrTop = pTmpRsp->DWords.dw0 -= cbItem;
     else
@@ -3221,10 +3227,10 @@
 {
     RTGCPTR GCPtrTop;
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
     {
         GCPtrTop = pTmpRsp->u;
         pTmpRsp->u          += cbItem;
     }
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
     {
         GCPtrTop = pTmpRsp->DWords.dw0;
@@ -3335,9 +3341,9 @@
          *        happens in real mode here based on the fnsave and fnstenv images. */
         pCtx->fpu.CS    = 0;
-        pCtx->fpu.FPUIP = pCtx->eip | ((uint32_t)pCtx->cs << 4);
+        pCtx->fpu.FPUIP = pCtx->eip | ((uint32_t)pCtx->cs.Sel << 4);
     }
     else
     {
-        pCtx->fpu.CS    = pCtx->cs;
+        pCtx->fpu.CS    = pCtx->cs.Sel;
         pCtx->fpu.FPUIP = pCtx->rip;
     }
@@ -3358,13 +3364,13 @@
     switch (iEffSeg)
     {
-        case X86_SREG_DS: sel = pCtx->ds; break;
-        case X86_SREG_SS: sel = pCtx->ss; break;
-        case X86_SREG_CS: sel = pCtx->cs; break;
-        case X86_SREG_ES: sel = pCtx->es; break;
-        case X86_SREG_FS: sel = pCtx->fs; break;
-        case X86_SREG_GS: sel = pCtx->gs; break;
+        case X86_SREG_DS: sel = pCtx->ds.Sel; break;
+        case X86_SREG_SS: sel = pCtx->ss.Sel; break;
+        case X86_SREG_CS: sel = pCtx->cs.Sel; break;
+        case X86_SREG_ES: sel = pCtx->es.Sel; break;
+        case X86_SREG_FS: sel = pCtx->fs.Sel; break;
+        case X86_SREG_GS: sel = pCtx->gs.Sel; break;
         default:
             AssertMsgFailed(("%d\n", iEffSeg));
-            sel = pCtx->ds;
+            sel = pCtx->ds.Sel;
     }
     /** @todo FPU.DS and FPUDP needs to be kept seperately. */
@@ -5777,15 +5783,15 @@
     if (uSel & X86_SEL_LDT)
     {
-        if (   !pCtx->ldtrHid.Attr.n.u1Present
-            || (uSel | 0x7U) > pCtx->ldtrHid.u32Limit )
+        if (   !pCtx->ldtr.Attr.n.u1Present
+            || (uSel | 0x7U) > pCtx->ldtr.u32Limit )
         {
             Log(("iemMemFetchSelDesc: LDT selector %#x is out of bounds (%3x) or ldtr is NP (%#x)\n",
-                 uSel, pCtx->ldtrHid.u32Limit, pCtx->ldtr));
+                 uSel, pCtx->ldtr.u32Limit, pCtx->ldtr.Sel));
             /** @todo is this the right exception? */
             return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
         }
 
-        Assert(pCtx->ldtrHid.Attr.n.u1Present);
-        GCPtrBase = pCtx->ldtrHid.u64Base;
+        Assert(pCtx->ldtr.Attr.n.u1Present);
+        GCPtrBase = pCtx->ldtr.u64Base;
     }
     else
@@ -5810,5 +5816,5 @@
             || pDesc->Legacy.Gen.u1DescType)
             pDesc->Long.au64[1] = 0;
-        else if ((uint32_t)(uSel & X86_SEL_MASK) + 15 < (uSel & X86_SEL_LDT ? pCtx->ldtrHid.u32Limit : pCtx->gdtr.cbGdt))
+        else if ((uint32_t)(uSel & X86_SEL_MASK) + 15 < (uSel & X86_SEL_LDT ? pCtx->ldtr.u32Limit : pCtx->gdtr.cbGdt))
             rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
         else
@@ -5859,5 +5865,5 @@
      */
     RTGCPTR GCPtr = uSel & X86_SEL_LDT
-                  ? pCtx->ldtrHid.u64Base
+                  ? pCtx->ldtr.u64Base
                   : pCtx->gdtr.pGdt;
     GCPtr += uSel & X86_SEL_MASK;
@@ -6605,8 +6611,8 @@
 #ifdef DEBUG
 # define IEMOP_MNEMONIC(a_szMnemonic) \
-    Log4(("decode - %04x:%RGv %s%s [#%u]\n", pIemCpu->CTX_SUFF(pCtx)->cs, pIemCpu->CTX_SUFF(pCtx)->rip, \
+    Log4(("decode - %04x:%RGv %s%s [#%u]\n", pIemCpu->CTX_SUFF(pCtx)->cs.Sel, pIemCpu->CTX_SUFF(pCtx)->rip, \
           pIemCpu->fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, pIemCpu->cInstructions))
 # define IEMOP_MNEMONIC2(a_szMnemonic, a_szOps) \
-    Log4(("decode - %04x:%RGv %s%s %s [#%u]\n", pIemCpu->CTX_SUFF(pCtx)->cs, pIemCpu->CTX_SUFF(pCtx)->rip, \
+    Log4(("decode - %04x:%RGv %s%s %s [#%u]\n", pIemCpu->CTX_SUFF(pCtx)->cs.Sel, pIemCpu->CTX_SUFF(pCtx)->rip, \
           pIemCpu->fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, a_szOps, pIemCpu->cInstructions))
 #else
@@ -7872,6 +7878,6 @@
               pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
               pCtx->eip, pCtx->esp, pCtx->ebp, pCtx->eflags.Bits.u2IOPL,
-              (RTSEL)pCtx->cs, (RTSEL)pCtx->ss, (RTSEL)pCtx->ds, (RTSEL)pCtx->es,
-              (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, pCtx->eflags.u,
+              pCtx->cs.Sel, pCtx->ss.Sel, pCtx->ds.Sel, pCtx->es.Sel,
+              pCtx->fs.Sel, pCtx->gs.Sel, pCtx->eflags.u,
               pCtx->fpu.FSW, pCtx->fpu.FCW, pCtx->fpu.FTW, pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK,
               szInstr));
@@ -7883,5 +7889,5 @@
 # endif
         LogFlow(("IEMExecOne: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x\n",
-                 pCtx->cs, pCtx->rip, pCtx->ss, pCtx->rsp, pCtx->eflags.u));
+                 pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->rsp, pCtx->eflags.u));
 #endif
 
@@ -7901,5 +7907,5 @@
     if (rcStrict != VINF_SUCCESS)
         LogFlow(("IEMExecOne: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x - rcStrict=%Rrc\n",
-                 pCtx->cs, pCtx->rip, pCtx->ss, pCtx->rsp, pCtx->eflags.u, VBOXSTRICTRC_VAL(rcStrict)));
+                 pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->rsp, pCtx->eflags.u, VBOXSTRICTRC_VAL(rcStrict)));
     return rcStrict;
 }
Index: trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h	(revision 41906)
@@ -103,15 +103,16 @@
  * visible parts, in protected mode.
  *
- * @param   puSel               The selector register.
- * @param   pHid                The hidden register part.
- */
-static void iemHlpLoadNullDataSelectorProt(PRTSEL puSel, PCPUMSELREGHID pHid)
+ * @param   pSReg               Pointer to the segment register.
+ */
+static void iemHlpLoadNullDataSelectorProt(PCPUMSELREG pSReg)
 {
     /** @todo Testcase: write a testcase checking what happends when loading a NULL
      *        data selector in protected mode. */
-    pHid->u64Base  = 0;
-    pHid->u32Limit = 0;
-    pHid->Attr.u   = 0;
-    *puSel = 0;
+    pSReg->Sel      = 0;
+    pSReg->ValidSel = 0;
+    pSReg->fFlags   = CPUMSELREG_FLAGS_VALID;
+    pSReg->u64Base  = 0;
+    pSReg->u32Limit = 0;
+    pSReg->Attr.u   = 0;
 }
 
@@ -121,14 +122,13 @@
  *
  * @param   uCpl                The new CPL.
- * @param   puSel               The selector register.
- * @param   pHid                The corresponding hidden register.
- */
-static void iemHlpAdjustSelectorForNewCpl(uint8_t uCpl, PRTSEL puSel, PCPUMSELREGHID pHid)
-{
-    if (   uCpl > pHid->Attr.n.u2Dpl
-        && pHid->Attr.n.u1DescType /* code or data, not system */
-        &&    (pHid->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
-           !=                        (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
-        iemHlpLoadNullDataSelectorProt(puSel, pHid);
+ * @param   pSReg               Pointer to the segment register.
+ */
+static void iemHlpAdjustSelectorForNewCpl(uint8_t uCpl, PCPUMSELREG pSReg)
+{
+    if (   uCpl > pSReg->Attr.n.u2Dpl
+        && pSReg->Attr.n.u1DescType /* code or data, not system */
+        &&    (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
+           !=                         (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
+        iemHlpLoadNullDataSelectorProt(pSReg);
 }
 
@@ -158,5 +158,5 @@
     /** @todo do popa boundary / wrap-around checks.  */
     if (RT_UNLIKELY(   IEM_IS_REAL_OR_V86_MODE(pIemCpu)
-                    && (pCtx->csHid.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
+                    && (pCtx->cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
     {
         /* word-by-word */
@@ -230,5 +230,5 @@
     /** @todo do popa boundary / wrap-around checks.  */
     if (RT_UNLIKELY(   IEM_IS_REAL_OR_V86_MODE(pIemCpu)
-                    && (pCtx->csHid.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
+                    && (pCtx->cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
     {
         /* word-by-word */
@@ -632,5 +632,5 @@
     PCPUMCTX pCtx   = pIemCpu->CTX_SUFF(pCtx);
     uint16_t uOldPC = pCtx->ip + cbInstr;
-    if (uNewPC > pCtx->csHid.u32Limit)
+    if (uNewPC > pCtx->cs.u32Limit)
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -655,5 +655,5 @@
     uint16_t uOldPC = pCtx->ip + cbInstr;
     uint16_t uNewPC = uOldPC + offDisp;
-    if (uNewPC > pCtx->csHid.u32Limit)
+    if (uNewPC > pCtx->cs.u32Limit)
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -678,5 +678,5 @@
     PCPUMCTX pCtx   = pIemCpu->CTX_SUFF(pCtx);
     uint32_t uOldPC = pCtx->eip + cbInstr;
-    if (uNewPC > pCtx->csHid.u32Limit)
+    if (uNewPC > pCtx->cs.u32Limit)
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -701,5 +701,5 @@
     uint32_t uOldPC = pCtx->eip + cbInstr;
     uint32_t uNewPC = uOldPC + offDisp;
-    if (uNewPC > pCtx->csHid.u32Limit)
+    if (uNewPC > pCtx->cs.u32Limit)
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -891,5 +891,5 @@
         && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
     {
-        if (offSeg > pCtx->csHid.u32Limit)
+        if (offSeg > pCtx->cs.u32Limit)
             return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -898,10 +898,12 @@
         else
             pCtx->rip       = offSeg & UINT16_MAX;
-        pCtx->cs            = uSel;
-        pCtx->csHid.u64Base = (uint32_t)uSel << 4;
+        pCtx->cs.Sel        = uSel;
+        pCtx->cs.ValidSel   = uSel;
+        pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+        pCtx->cs.u64Base    = (uint32_t)uSel << 4;
         /** @todo REM reset the accessed bit (see on jmp far16 after disabling
          *        PE.  Check with VT-x and AMD-V. */
 #ifdef IEM_VERIFICATION_MODE
-        pCtx->csHid.Attr.u  &= ~X86_SEL_TYPE_ACCESSED;
+        pCtx->cs.Attr.u    &= ~X86_SEL_TYPE_ACCESSED;
 #endif
         return VINF_SUCCESS;
@@ -1015,9 +1017,11 @@
     /* commit */
     pCtx->rip = offSeg;
-    pCtx->cs  = uSel & (X86_SEL_MASK | X86_SEL_LDT);
-    pCtx->cs |= pIemCpu->uCpl; /** @todo is this right for conforming segs? or in general? */
-    pCtx->csHid.Attr.u   = X86DESC_GET_HID_ATTR(Desc.Legacy);
-    pCtx->csHid.u32Limit = cbLimit;
-    pCtx->csHid.u64Base  = u64Base;
+    pCtx->cs.Sel         = uSel & (X86_SEL_MASK | X86_SEL_LDT);
+    pCtx->cs.Sel        |= pIemCpu->uCpl; /** @todo is this right for conforming segs? or in general? */
+    pCtx->cs.ValidSel    = pCtx->cs.Sel;
+    pCtx->cs.fFlags      = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.Attr.u      = X86DESC_GET_HID_ATTR(Desc.Legacy);
+    pCtx->cs.u32Limit    = cbLimit;
+    pCtx->cs.u64Base     = u64Base;
     /** @todo check if the hidden bits are loaded correctly for 64-bit
      *        mode.  */
@@ -1066,10 +1070,10 @@
         {
             uPtrRet.pu16[0] = pCtx->ip + cbInstr;
-            uPtrRet.pu16[1] = pCtx->cs;
+            uPtrRet.pu16[1] = pCtx->cs.Sel;
         }
         else
         {
             uPtrRet.pu32[0] = pCtx->eip + cbInstr;
-            uPtrRet.pu16[3] = pCtx->cs;
+            uPtrRet.pu16[3] = pCtx->cs.Sel;
         }
         rcStrict = iemMemStackPushCommitSpecial(pIemCpu, uPtrRet.pv, uNewRsp);
@@ -1079,10 +1083,12 @@
         /* Branch. */
         pCtx->rip           = offSeg;
-        pCtx->cs            = uSel;
-        pCtx->csHid.u64Base = (uint32_t)uSel << 4;
+        pCtx->cs.Sel        = uSel;
+        pCtx->cs.ValidSel   = uSel;
+        pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+        pCtx->cs.u64Base    = (uint32_t)uSel << 4;
         /** @todo Does REM reset the accessed bit here too? (See on jmp far16
          *        after disabling PE.) Check with VT-x and AMD-V. */
 #ifdef IEM_VERIFICATION_MODE
-        pCtx->csHid.Attr.u  &= ~X86_SEL_TYPE_ACCESSED;
+        pCtx->cs.Attr.u    &= ~X86_SEL_TYPE_ACCESSED;
 #endif
         return VINF_SUCCESS;
@@ -1217,15 +1223,15 @@
     {
         uPtrRet.pu16[0] = pCtx->ip + cbInstr;
-        uPtrRet.pu16[1] = pCtx->cs;
+        uPtrRet.pu16[1] = pCtx->cs.Sel;
     }
     else if (enmEffOpSize == IEMMODE_32BIT)
     {
         uPtrRet.pu32[0] = pCtx->eip + cbInstr;
-        uPtrRet.pu32[1] = pCtx->cs; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
+        uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
     }
     else
     {
         uPtrRet.pu64[0] = pCtx->rip + cbInstr;
-        uPtrRet.pu64[1] = pCtx->cs; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
+        uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
     }
     rcStrict = iemMemStackPushCommitSpecial(pIemCpu, uPtrRet.pv, uNewRsp);
@@ -1235,9 +1241,11 @@
     /* commit */
     pCtx->rip = offSeg;
-    pCtx->cs  = uSel & (X86_SEL_MASK | X86_SEL_LDT);
-    pCtx->cs |= pIemCpu->uCpl;
-    pCtx->csHid.Attr.u   = X86DESC_GET_HID_ATTR(Desc.Legacy);
-    pCtx->csHid.u32Limit = cbLimit;
-    pCtx->csHid.u64Base  = u64Base;
+    pCtx->cs.Sel         = uSel & (X86_SEL_MASK | X86_SEL_LDT);
+    pCtx->cs.Sel        |= pIemCpu->uCpl;
+    pCtx->cs.ValidSel    = pCtx->cs.Sel;
+    pCtx->cs.fFlags      = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.Attr.u      = X86DESC_GET_HID_ATTR(Desc.Legacy);
+    pCtx->cs.u32Limit    = cbLimit;
+    pCtx->cs.u64Base     = u64Base;
     /** @todo check if the hidden bits are loaded correctly for 64-bit
      *        mode.  */
@@ -1299,5 +1307,5 @@
         /** @todo Intel pseudo code only does the limit check for 16-bit
          *        operands, AMD does not make any distinction. What is right? */
-        if (uNewRip > pCtx->csHid.u32Limit)
+        if (uNewRip > pCtx->cs.u32Limit)
             return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
 
@@ -1307,6 +1315,8 @@
             return rcStrict;
         pCtx->rip           = uNewRip;
-        pCtx->cs            = uNewCs;
-        pCtx->csHid.u64Base = (uint32_t)uNewCs << 4;
+        pCtx->cs.Sel        = uNewCs;
+        pCtx->cs.ValidSel   = uNewCs;
+        pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+        pCtx->cs.u64Base    = (uint32_t)uNewCs << 4;
         /** @todo do we load attribs and limit as well? */
         if (cbPop)
@@ -1540,22 +1550,26 @@
         else
             pCtx->rip           = uNewRip;
-        pCtx->cs                = uNewCs;
-        pCtx->csHid.Attr.u      = X86DESC_GET_HID_ATTR(DescCs.Legacy);
-        pCtx->csHid.u32Limit    = cbLimitCs;
-        pCtx->csHid.u64Base     = u64Base;
+        pCtx->cs.Sel            = uNewCs;
+        pCtx->cs.ValidSel       = uNewCs;
+        pCtx->cs.fFlags         = CPUMSELREG_FLAGS_VALID;
+        pCtx->cs.Attr.u         = X86DESC_GET_HID_ATTR(DescCs.Legacy);
+        pCtx->cs.u32Limit       = cbLimitCs;
+        pCtx->cs.u64Base        = u64Base;
         pCtx->rsp               = uNewRsp;
-        pCtx->ss                = uNewCs;
-        pCtx->ssHid.Attr.u      = X86DESC_GET_HID_ATTR(DescSs.Legacy);
-        pCtx->ssHid.u32Limit    = cbLimitSs;
+        pCtx->ss.Sel            = uNewOuterSs;
+        pCtx->ss.ValidSel       = uNewOuterSs;
+        pCtx->ss.fFlags         = CPUMSELREG_FLAGS_VALID;
+        pCtx->ss.Attr.u         = X86DESC_GET_HID_ATTR(DescSs.Legacy);
+        pCtx->ss.u32Limit       = cbLimitSs;
         if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
-            pCtx->ssHid.u64Base = 0;
+            pCtx->ss.u64Base    = 0;
         else
-            pCtx->ssHid.u64Base = X86DESC_BASE(DescSs.Legacy);
+            pCtx->ss.u64Base    = X86DESC_BASE(DescSs.Legacy);
 
         pIemCpu->uCpl           = (uNewCs & X86_SEL_RPL);
-        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->ds, &pCtx->dsHid);
-        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->es, &pCtx->esHid);
-        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->fs, &pCtx->fsHid);
-        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->gs, &pCtx->gsHid);
+        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->ds);
+        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->es);
+        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->fs);
+        iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->gs);
 
         /** @todo check if the hidden bits are loaded correctly for 64-bit
@@ -1618,11 +1632,13 @@
             return rcStrict;
         if (enmEffOpSize == IEMMODE_16BIT)
-            pCtx->rip           = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
+            pCtx->rip       = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
         else
-            pCtx->rip           = uNewRip;
-        pCtx->cs                = uNewCs;
-        pCtx->csHid.Attr.u      = X86DESC_GET_HID_ATTR(DescCs.Legacy);
-        pCtx->csHid.u32Limit    = cbLimitCs;
-        pCtx->csHid.u64Base     = u64Base;
+            pCtx->rip       = uNewRip;
+        pCtx->cs.Sel        = uNewCs;
+        pCtx->cs.ValidSel   = uNewCs;
+        pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+        pCtx->cs.Attr.u     = X86DESC_GET_HID_ATTR(DescCs.Legacy);
+        pCtx->cs.u32Limit   = cbLimitCs;
+        pCtx->cs.u64Base    = u64Base;
         /** @todo check if the hidden bits are loaded correctly for 64-bit
          *        mode.  */
@@ -1677,7 +1693,7 @@
     if (enmEffOpSize != IEMMODE_64BIT)
     {
-        if (NewRip.DWords.dw0 > pCtx->csHid.u32Limit)
-        {
-            Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pCtx->csHid.u32Limit));
+        if (NewRip.DWords.dw0 > pCtx->cs.u32Limit)
+        {
+            Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pCtx->cs.u32Limit));
             return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
         }
@@ -1716,5 +1732,5 @@
     /* Calculate the intermediate RSP from RBP and the stack attributes. */
     RTUINT64U       NewRsp;
-    if (pCtx->ssHid.Attr.n.u1Long)
+    if (pCtx->ss.Attr.n.u1Long)
     {
         /** @todo Check that LEAVE actually preserve the high EBP bits. */
@@ -1722,5 +1738,5 @@
         NewRsp.Words.w0 = pCtx->bp;
     }
-    else if (pCtx->ssHid.Attr.n.u1DefBig)
+    else if (pCtx->ss.Attr.n.u1DefBig)
         NewRsp.u = pCtx->ebp;
     else
@@ -1839,5 +1855,5 @@
     /** @todo Only the AMD pseudo code check the limit here, what's
      *        right? */
-    if (uNewEip > pCtx->csHid.u32Limit)
+    if (uNewEip > pCtx->cs.u32Limit)
         return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
 
@@ -1875,6 +1891,8 @@
         return rcStrict;
     pCtx->rip           = uNewEip;
-    pCtx->cs            = uNewCs;
-    pCtx->csHid.u64Base = (uint32_t)uNewCs << 4;
+    pCtx->cs.Sel        = uNewCs;
+    pCtx->cs.ValidSel   = uNewCs;
+    pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.u64Base    = (uint32_t)uNewCs << 4;
     /** @todo do we load attribs and limit as well? */
     Assert(uNewFlags & X86_EFL_1);
@@ -2113,14 +2131,18 @@
                 }
 
-                pCtx->rip               = uNewEip;
-                pCtx->cs                = uNewCs;
-                pCtx->csHid.Attr.u      = X86DESC_GET_HID_ATTR(DescCS.Legacy);
-                pCtx->csHid.u32Limit    = cbLimitCS;
-                pCtx->csHid.u64Base     = X86DESC_BASE(DescCS.Legacy);
-                pCtx->rsp               = uNewESP;
-                pCtx->ss                = uNewSS;
-                pCtx->ssHid.Attr.u      = X86DESC_GET_HID_ATTR(DescSS.Legacy);
-                pCtx->ssHid.u32Limit    = cbLimitSs;
-                pCtx->ssHid.u64Base     = X86DESC_BASE(DescSS.Legacy);
+                pCtx->rip           = uNewEip;
+                pCtx->cs.Sel        = uNewCs;
+                pCtx->cs.ValidSel   = uNewCs;
+                pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+                pCtx->cs.Attr.u     = X86DESC_GET_HID_ATTR(DescCS.Legacy);
+                pCtx->cs.u32Limit   = cbLimitCS;
+                pCtx->cs.u64Base    = X86DESC_BASE(DescCS.Legacy);
+                pCtx->rsp           = uNewESP;
+                pCtx->ss.Sel        = uNewSS;
+                pCtx->ss.ValidSel   = uNewSS;
+                pCtx->ss.fFlags     = CPUMSELREG_FLAGS_VALID;
+                pCtx->ss.Attr.u     = X86DESC_GET_HID_ATTR(DescSS.Legacy);
+                pCtx->ss.u32Limit   = cbLimitSs;
+                pCtx->ss.u64Base    = X86DESC_BASE(DescSS.Legacy);
 
                 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF  | X86_EFL_SF
@@ -2132,12 +2154,12 @@
                 else if (pIemCpu->uCpl <= pCtx->eflags.Bits.u2IOPL)
                     fEFlagsMask |= X86_EFL_IF;
-                pCtx->eflags.u         &= ~fEFlagsMask;
-                pCtx->eflags.u         |= fEFlagsMask & uNewFlags;
-
-                pIemCpu->uCpl           = uNewCs & X86_SEL_RPL;
-                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->ds, &pCtx->dsHid);
-                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->es, &pCtx->esHid);
-                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->fs, &pCtx->fsHid);
-                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->gs, &pCtx->gsHid);
+                pCtx->eflags.u     &= ~fEFlagsMask;
+                pCtx->eflags.u     |= fEFlagsMask & uNewFlags;
+
+                pIemCpu->uCpl       = uNewCs & X86_SEL_RPL;
+                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->ds);
+                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->es);
+                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->fs);
+                iemHlpAdjustSelectorForNewCpl(uNewCs & X86_SEL_RPL, &pCtx->gs);
 
                 /* Done! */
@@ -2167,10 +2189,12 @@
                 }
 
-                pCtx->rip               = uNewEip;
-                pCtx->cs                = uNewCs;
-                pCtx->csHid.Attr.u      = X86DESC_GET_HID_ATTR(DescCS.Legacy);
-                pCtx->csHid.u32Limit    = cbLimitCS;
-                pCtx->csHid.u64Base     = X86DESC_BASE(DescCS.Legacy);
-                pCtx->rsp               = uNewRsp;
+                pCtx->rip           = uNewEip;
+                pCtx->cs.Sel        = uNewCs;
+                pCtx->cs.ValidSel   = uNewCs;
+                pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+                pCtx->cs.Attr.u     = X86DESC_GET_HID_ATTR(DescCS.Legacy);
+                pCtx->cs.u32Limit   = cbLimitCS;
+                pCtx->cs.u64Base    = X86DESC_BASE(DescCS.Legacy);
+                pCtx->rsp           = uNewRsp;
 
                 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF  | X86_EFL_SF
@@ -2667,8 +2691,10 @@
             CPUMSetGuestLDTR(IEMCPU_TO_VMCPU(pIemCpu), 0);
         else
-            pCtx->ldtr = 0;
-        pCtx->ldtrHid.Attr.u   = 0;
-        pCtx->ldtrHid.u64Base  = 0;
-        pCtx->ldtrHid.u32Limit = 0;
+            pCtx->ldtr.Sel = 0;
+        pCtx->ldtr.ValidSel = 0;
+        pCtx->ldtr.fFlags   = CPUMSELREG_FLAGS_VALID;
+        pCtx->ldtr.Attr.u   = 0;
+        pCtx->ldtr.u64Base  = 0;
+        pCtx->ldtr.u32Limit = 0;
 
         iemRegAddToRip(pIemCpu, cbInstr);
@@ -2728,8 +2754,10 @@
         CPUMSetGuestLDTR(IEMCPU_TO_VMCPU(pIemCpu), uNewLdt & X86_SEL_MASK);
     else
-        pCtx->ldtr = uNewLdt & X86_SEL_MASK;
-    pCtx->ldtrHid.Attr.u   = X86DESC_GET_HID_ATTR(Desc.Legacy);
-    pCtx->ldtrHid.u32Limit = X86DESC_LIMIT(Desc.Legacy);
-    pCtx->ldtrHid.u64Base  = u64Base;
+        pCtx->ldtr.Sel  = uNewLdt & X86_SEL_MASK;
+    pCtx->ldtr.ValidSel = uNewLdt & X86_SEL_MASK;
+    pCtx->ldtr.fFlags   = CPUMSELREG_FLAGS_VALID;
+    pCtx->ldtr.Attr.u   = X86DESC_GET_HID_ATTR(Desc.Legacy);
+    pCtx->ldtr.u32Limit = X86DESC_LIMIT(Desc.Legacy);
+    pCtx->ldtr.u64Base  = u64Base;
 
     iemRegAddToRip(pIemCpu, cbInstr);
@@ -2847,8 +2875,10 @@
         CPUMSetGuestTR(IEMCPU_TO_VMCPU(pIemCpu), uNewTr & X86_SEL_MASK);
     else
-        pCtx->tr = uNewTr & X86_SEL_MASK;
-    pCtx->trHid.Attr.u   = X86DESC_GET_HID_ATTR(Desc.Legacy);
-    pCtx->trHid.u32Limit = X86DESC_LIMIT(Desc.Legacy);
-    pCtx->trHid.u64Base  = u64Base;
+        pCtx->tr.Sel  = uNewTr & X86_SEL_MASK;
+    pCtx->tr.ValidSel = uNewTr & X86_SEL_MASK;
+    pCtx->tr.fFlags   = CPUMSELREG_FLAGS_VALID;
+    pCtx->tr.Attr.u   = X86DESC_GET_HID_ATTR(Desc.Legacy);
+    pCtx->tr.u32Limit = X86DESC_LIMIT(Desc.Legacy);
+    pCtx->tr.u64Base  = u64Base;
 
     iemRegAddToRip(pIemCpu, cbInstr);
@@ -2960,5 +2990,5 @@
                     return iemRaiseGeneralProtectionFault0(pIemCpu);
                 }
-                if (pCtx->csHid.Attr.n.u1Long)
+                if (pCtx->cs.Attr.n.u1Long)
                 {
                     Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
Index: trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h	(revision 41906)
@@ -76,5 +76,5 @@
         return rcStrict;
 
-    rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -94,6 +94,6 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtSrc1Addr = (uint32_t)pSrc1Hid->u64Base   + uSrc1AddrReg;
-        ADDR2_TYPE  uVirtSrc2Addr = (uint32_t)pCtx->esHid.u64Base + uSrc2AddrReg;
+        ADDR2_TYPE  uVirtSrc1Addr = (uint32_t)pSrc1Hid->u64Base + uSrc1AddrReg;
+        ADDR2_TYPE  uVirtSrc2Addr = (uint32_t)pCtx->es.u64Base  + uSrc2AddrReg;
 #else
         uint64_t    uVirtSrc1Addr = uSrc1AddrReg;
@@ -111,6 +111,6 @@
             && uSrc1AddrReg < pSrc1Hid->u32Limit
             && uSrc1AddrReg + (cLeftPage * (OP_SIZE / 8)) <= pSrc1Hid->u32Limit
-            && uSrc2AddrReg < pCtx->esHid.u32Limit
-            && uSrc2AddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uSrc2AddrReg < pCtx->es.u32Limit
+            && uSrc2AddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
@@ -233,5 +233,5 @@
         return rcStrict;
 
-    rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -251,6 +251,6 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtSrc1Addr = (uint32_t)pSrc1Hid->u64Base   + uSrc1AddrReg;
-        ADDR2_TYPE  uVirtSrc2Addr = (uint32_t)pCtx->esHid.u64Base + uSrc2AddrReg;
+        ADDR2_TYPE  uVirtSrc1Addr = (uint32_t)pSrc1Hid->u64Base + uSrc1AddrReg;
+        ADDR2_TYPE  uVirtSrc2Addr = (uint32_t)pCtx->es.u64Base  + uSrc2AddrReg;
 #else
         uint64_t    uVirtSrc1Addr = uSrc1AddrReg;
@@ -268,6 +268,6 @@
             && uSrc1AddrReg < pSrc1Hid->u32Limit
             && uSrc1AddrReg + (cLeftPage * (OP_SIZE / 8)) <= pSrc1Hid->u32Limit
-            && uSrc2AddrReg < pCtx->esHid.u32Limit
-            && uSrc2AddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uSrc2AddrReg < pCtx->es.u32Limit
+            && uSrc2AddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
@@ -385,5 +385,5 @@
     }
 
-    VBOXSTRICTRC rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    VBOXSTRICTRC rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -403,5 +403,5 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->esHid.u64Base + uAddrReg;
+        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->es.u64Base + uAddrReg;
 #else
         uint64_t    uVirtAddr = uAddrReg;
@@ -413,6 +413,6 @@
             && cbIncr > 0    /** @todo Implement reverse direction string ops. */
 #if ADDR_SIZE != 64
-            && uAddrReg < pCtx->esHid.u32Limit
-            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uAddrReg < pCtx->es.u32Limit
+            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
@@ -509,5 +509,5 @@
     }
 
-    VBOXSTRICTRC rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    VBOXSTRICTRC rcStrict = iemMemSegCheckReadAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -527,5 +527,5 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->esHid.u64Base + uAddrReg;
+        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->es.u64Base + uAddrReg;
 #else
         uint64_t    uVirtAddr = uAddrReg;
@@ -537,6 +537,6 @@
             && cbIncr > 0    /** @todo Implement reverse direction string ops. */
 #if ADDR_SIZE != 64
-            && uAddrReg < pCtx->esHid.u32Limit
-            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uAddrReg < pCtx->es.u32Limit
+            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
@@ -640,5 +640,5 @@
         return rcStrict;
 
-    rcStrict = iemMemSegCheckWriteAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    rcStrict = iemMemSegCheckWriteAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -657,6 +657,6 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtSrcAddr = (uint32_t)pSrcHid->u64Base    + uSrcAddrReg;
-        ADDR2_TYPE  uVirtDstAddr = (uint32_t)pCtx->esHid.u64Base + uDstAddrReg;
+        ADDR2_TYPE  uVirtSrcAddr = (uint32_t)pSrcHid->u64Base + uSrcAddrReg;
+        ADDR2_TYPE  uVirtDstAddr = (uint32_t)pCtx->es.u64Base + uDstAddrReg;
 #else
         uint64_t    uVirtSrcAddr = uSrcAddrReg;
@@ -674,6 +674,6 @@
             && uSrcAddrReg < pSrcHid->u32Limit
             && uSrcAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pSrcHid->u32Limit
-            && uDstAddrReg < pCtx->esHid.u32Limit
-            && uDstAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uDstAddrReg < pCtx->es.u32Limit
+            && uDstAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
@@ -764,5 +764,5 @@
     }
 
-    VBOXSTRICTRC rcStrict = iemMemSegCheckWriteAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    VBOXSTRICTRC rcStrict = iemMemSegCheckWriteAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -781,5 +781,5 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->esHid.u64Base + uAddrReg;
+        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->es.u64Base + uAddrReg;
 #else
         uint64_t    uVirtAddr = uAddrReg;
@@ -791,6 +791,6 @@
             && cbIncr > 0    /** @todo Implement reverse direction string ops. */
 #if ADDR_SIZE != 64
-            && uAddrReg < pCtx->esHid.u32Limit
-            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uAddrReg < pCtx->es.u32Limit
+            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
@@ -1048,5 +1048,5 @@
     }
 
-    rcStrict = iemMemSegCheckWriteAccessEx(pIemCpu, &pCtx->esHid, X86_SREG_ES);
+    rcStrict = iemMemSegCheckWriteAccessEx(pIemCpu, &pCtx->es, X86_SREG_ES);
     if (rcStrict != VINF_SUCCESS)
         return rcStrict;
@@ -1064,5 +1064,5 @@
          */
 #if ADDR_SIZE != 64
-        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->esHid.u64Base + uAddrReg;
+        ADDR2_TYPE  uVirtAddr = (uint32_t)pCtx->es.u64Base + uAddrReg;
 #else
         uint64_t    uVirtAddr = uAddrReg;
@@ -1074,6 +1074,6 @@
             && cbIncr > 0    /** @todo Implement reverse direction string ops. */
 #if ADDR_SIZE != 64
-            && uAddrReg < pCtx->esHid.u32Limit
-            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->esHid.u32Limit
+            && uAddrReg < pCtx->es.u32Limit
+            && uAddrReg + (cLeftPage * (OP_SIZE / 8)) <= pCtx->es.u32Limit
 #endif
            )
Index: trunk/src/VBox/VMM/VMMAll/PATMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PATMAll.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/PATMAll.cpp	(revision 41906)
@@ -385,5 +385,5 @@
         if (    pCtx->SysEnter.cs == 0
             ||  pRegFrame->eflags.Bits.u1VM
-            ||  (pRegFrame->cs & X86_SEL_RPL) != 3
+            ||  (pRegFrame->cs.Sel & X86_SEL_RPL) != 3
             ||  pVM->patm.s.pfnSysEnterPatchGC == 0
             ||  pVM->patm.s.pfnSysEnterGC != (RTRCPTR)(RTRCUINTPTR)pCtx->SysEnter.eip
@@ -394,9 +394,9 @@
         /** @todo the base and limit are forced to 0 & 4G-1 resp. We assume the selector is wide open here. */
         /** @note The Intel manual suggests that the OS is responsible for this. */
-        pRegFrame->cs          = (pCtx->SysEnter.cs & ~X86_SEL_RPL) | 1;
+        pRegFrame->cs.Sel      = (pCtx->SysEnter.cs & ~X86_SEL_RPL) | 1;
         pRegFrame->eip         = /** @todo ugly conversion! */(uint32_t)pVM->patm.s.pfnSysEnterPatchGC;
-        pRegFrame->ss          = pRegFrame->cs + 8;     /* SysEnter.cs + 8 */
+        pRegFrame->ss.Sel      = pRegFrame->cs.Sel + 8;     /* SysEnter.cs + 8 */
         pRegFrame->esp         = pCtx->SysEnter.esp;
-        pRegFrame->eflags.u32 &= ~(X86_EFL_VM|X86_EFL_RF);
+        pRegFrame->eflags.u32 &= ~(X86_EFL_VM | X86_EFL_RF);
         pRegFrame->eflags.u32 |= X86_EFL_IF;
 
@@ -408,9 +408,8 @@
         return VINF_SUCCESS;
     }
-    else
     if (pCpu->pCurInstr->uOpcode == OP_SYSEXIT)
     {
         if (    pCtx->SysEnter.cs == 0
-            ||  (pRegFrame->cs & X86_SEL_RPL) != 1
+            ||  (pRegFrame->cs.Sel & X86_SEL_RPL) != 1
             ||  pRegFrame->eflags.Bits.u1VM
             ||  !(PATMRawGetEFlags(pVM, pRegFrame) & X86_EFL_IF))
@@ -419,7 +418,7 @@
         Log2(("PATMSysCall: sysexit from %RRv to %RRv\n", pRegFrame->eip, pRegFrame->edx));
 
-        pRegFrame->cs          = ((pCtx->SysEnter.cs + 16) & ~X86_SEL_RPL) | 3;
+        pRegFrame->cs.Sel      = ((pCtx->SysEnter.cs + 16) & ~X86_SEL_RPL) | 3;
         pRegFrame->eip         = pRegFrame->edx;
-        pRegFrame->ss          = pRegFrame->cs + 8;  /* SysEnter.cs + 24 */
+        pRegFrame->ss.Sel      = pRegFrame->cs.Sel + 8;  /* SysEnter.cs + 24 */
         pRegFrame->esp         = pRegFrame->ecx;
 
@@ -428,5 +427,4 @@
         return VINF_SUCCESS;
     }
-    else
     if (pCpu->pCurInstr->uOpcode == OP_SYSCALL)
     {
Index: trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAll.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/PGMAll.cpp	(revision 41906)
@@ -407,5 +407,5 @@
     PVM pVM = pVCpu->CTX_SUFF(pVM);
 
-    Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
+    Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
     STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
     STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
Index: trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 41906)
@@ -1079,5 +1079,5 @@
      */
     LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
-            __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
+            __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
     return rc;
 
Index: trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41906)
@@ -853,5 +853,5 @@
         {
             LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
-                     pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
+                     pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->eip));
             rc = VINF_SUCCESS;
             STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
@@ -990,5 +990,5 @@
     {
         LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
-                  pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
+                  pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
         rc = VINF_EM_RAW_EMULATE_INSTR;
         STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
Index: trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/SELMAll.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/SELMAll.cpp	(revision 41906)
@@ -114,5 +114,5 @@
 
     /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
-    if (    pCtxCore->csHid.Attr.n.u1Long
+    if (    pCtxCore->cs.Attr.n.u1Long
         &&  CPUMIsGuestInLongMode(pVCpu))
     {
@@ -196,5 +196,5 @@
 
         /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
-        if (    pCtxCore->csHid.Attr.n.u1Long
+        if (    pCtxCore->cs.Attr.n.u1Long
             &&  CPUMIsGuestInLongMode(pVCpu))
         {
Index: trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp	(revision 41906)
@@ -370,7 +370,7 @@
 # if defined(VBOX_STRICT) || defined(LOG_ENABLED)
     if (pRegFrame->eflags.Bits.u1VM)
-        Log(("TRPMForwardTrap-VM: eip=%04X:%04X iGate=%d\n", pRegFrame->cs, pRegFrame->eip, iGate));
+        Log(("TRPMForwardTrap-VM: eip=%04X:%04X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
     else
-        Log(("TRPMForwardTrap: eip=%04X:%08X iGate=%d\n", pRegFrame->cs, pRegFrame->eip, iGate));
+        Log(("TRPMForwardTrap: eip=%04X:%08X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
 
     switch (iGate) {
@@ -564,5 +564,5 @@
                 if (fConforming || dpl == cpl)  /* to the same privilege level */
                 {
-                    ss_r0  = pRegFrame->ss;
+                    ss_r0  = pRegFrame->ss.Sel;
                     esp_r0 = pRegFrame->esp;
 
@@ -584,10 +584,10 @@
                 uint32_t *pTrapStack;
 #ifdef IN_RC
-                Assert(eflags.Bits.u1VM || (pRegFrame->ss & X86_SEL_RPL) != 0);
+                Assert(eflags.Bits.u1VM || (pRegFrame->ss.Sel & X86_SEL_RPL) != 0);
                 /* Check maximum amount we need (10 when executing in V86 mode) */
                 rc = PGMVerifyAccess(pVCpu, (RTGCUINTPTR)pTrapStackGC - 10*sizeof(uint32_t), 10 * sizeof(uint32_t), X86_PTE_RW);
                 pTrapStack = (uint32_t *)(uintptr_t)pTrapStackGC;
 #else
-                Assert(eflags.Bits.u1VM || (pRegFrame->ss & X86_SEL_RPL) == 0 || (pRegFrame->ss & X86_SEL_RPL) == 3);
+                Assert(eflags.Bits.u1VM || (pRegFrame->ss.Sel & X86_SEL_RPL) == 0 || (pRegFrame->ss.Sel & X86_SEL_RPL) == 3);
                 /* Check maximum amount we need (10 when executing in V86 mode) */
                 if ((pTrapStackGC >> PAGE_SHIFT) != ((pTrapStackGC - 10*sizeof(uint32_t)) >> PAGE_SHIFT)) /* fail if we cross a page boundary */
@@ -606,22 +606,22 @@
                     if (eflags.Bits.u1VM)
                     {
-                        Log(("TRAP%02X: (VM) Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
-                        pTrapStack[--idx] = pRegFrame->gs;
-                        pTrapStack[--idx] = pRegFrame->fs;
-                        pTrapStack[--idx] = pRegFrame->ds;
-                        pTrapStack[--idx] = pRegFrame->es;
+                        Log(("TRAP%02X: (VM) Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
+                        pTrapStack[--idx] = pRegFrame->gs.Sel;
+                        pTrapStack[--idx] = pRegFrame->fs.Sel;
+                        pTrapStack[--idx] = pRegFrame->ds.Sel;
+                        pTrapStack[--idx] = pRegFrame->es.Sel;
 
                         /* clear ds, es, fs & gs in current context */
-                        pRegFrame->ds = pRegFrame->es = pRegFrame->fs = pRegFrame->gs = 0;
+                        pRegFrame->ds.Sel = pRegFrame->es.Sel = pRegFrame->fs.Sel = pRegFrame->gs.Sel = 0;
                     }
                     else
-                        Log(("TRAP%02X: Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
+                        Log(("TRAP%02X: Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
 
                     if (!fConforming && dpl < cpl)
                     {
-                        if ((pRegFrame->ss & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
-                            pTrapStack[--idx] = pRegFrame->ss & ~1;    /* Mask away traces of raw ring execution (ring 1). */
+                        if ((pRegFrame->ss.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
+                            pTrapStack[--idx] = pRegFrame->ss.Sel & ~1;    /* Mask away traces of raw ring execution (ring 1). */
                         else
-                            pTrapStack[--idx] = pRegFrame->ss;
+                            pTrapStack[--idx] = pRegFrame->ss.Sel;
 
                         pTrapStack[--idx] = pRegFrame->esp;
@@ -632,8 +632,8 @@
                     pTrapStack[--idx] = eflags.u32;
 
-                    if ((pRegFrame->cs & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
-                        pTrapStack[--idx] = pRegFrame->cs & ~1;    /* Mask away traces of raw ring execution (ring 1). */
+                    if ((pRegFrame->cs.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
+                        pTrapStack[--idx] = pRegFrame->cs.Sel & ~1;    /* Mask away traces of raw ring execution (ring 1). */
                     else
-                        pTrapStack[--idx] = pRegFrame->cs;
+                        pTrapStack[--idx] = pRegFrame->cs.Sel;
 
                     if (enmType == TRPM_SOFTWARE_INT)
@@ -665,6 +665,6 @@
                           pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx, pRegFrame->esi, pRegFrame->edi,
                           pRegFrame->eip, pRegFrame->esp, pRegFrame->ebp, eflags.Bits.u2IOPL,
-                          (RTSEL)pRegFrame->cs, (RTSEL)pRegFrame->ds, (RTSEL)pRegFrame->es,
-                          (RTSEL)pRegFrame->fs, (RTSEL)pRegFrame->gs, eflags.u32));
+                          pRegFrame->cs.Sel, pRegFrame->ds.Sel, pRegFrame->es.Sel,
+                          pRegFrame->fs.Sel, pRegFrame->gs.Sel, eflags.u32));
 #endif
 
@@ -705,7 +705,7 @@
 
                     pRegFrame->eip        = pVM->trpm.s.aGuestTrapHandler[iGate];
-                    pRegFrame->cs         = GuestIdte.Gen.u16SegSel;
+                    pRegFrame->cs.Sel     = GuestIdte.Gen.u16SegSel;
                     pRegFrame->esp        = esp_r0;
-                    pRegFrame->ss         = ss_r0 & ~X86_SEL_RPL;     /* set rpl to ring 0 */
+                    pRegFrame->ss.Sel     = ss_r0 & ~X86_SEL_RPL;     /* set rpl to ring 0 */
                     STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
                     PGMPhysReleasePageMappingLock(pVM, &PageMappingLock);
@@ -737,5 +737,5 @@
     STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
 
-    Log(("TRAP%02X: forwarding to REM (ss rpl=%d eflags=%08X VMIF=%d handler=%08X\n", iGate, pRegFrame->ss & X86_SEL_RPL, pRegFrame->eflags.u32, PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame), pVM->trpm.s.aGuestTrapHandler[iGate]));
+    Log(("TRAP%02X: forwarding to REM (ss rpl=%d eflags=%08X VMIF=%d handler=%08X\n", iGate, pRegFrame->ss.Sel & X86_SEL_RPL, pRegFrame->eflags.u32, PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame), pVM->trpm.s.aGuestTrapHandler[iGate]));
 #endif
     return VINF_EM_RAW_GUEST_TRAP;
@@ -760,5 +760,5 @@
 VMMDECL(int) TRPMRaiseXcpt(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt)
 {
-    LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x\n", pCtxCore->cs, pCtxCore->eip, enmXcpt));
+    LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt));
 /** @todo dispatch the trap. */
     pVCpu->trpm.s.uActiveVector            = enmXcpt;
@@ -787,5 +787,5 @@
 VMMDECL(int) TRPMRaiseXcptErr(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr)
 {
-    LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32\n", pCtxCore->cs, pCtxCore->eip, enmXcpt, uErr));
+    LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr));
 /** @todo dispatch the trap. */
     pVCpu->trpm.s.uActiveVector            = enmXcpt;
@@ -815,5 +815,5 @@
 VMMDECL(int) TRPMRaiseXcptErrCR2(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr, RTGCUINTPTR uCR2)
 {
-    LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32 uCR2=%RGv\n", pCtxCore->cs, pCtxCore->eip, enmXcpt, uErr, uCR2));
+    LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32 uCR2=%RGv\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr, uCR2));
 /** @todo dispatch the trap. */
     pVCpu->trpm.s.uActiveVector            = enmXcpt;
Index: trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp	(revision 41906)
@@ -1931,66 +1931,66 @@
     {
         Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
-            "rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
-            "r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
-            "r14=%016RX64 r15=%016RX64\n"
-            "rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
-            "cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
-            "ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
-            "es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
-            "fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
-            "gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
-            "ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
-            "cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
-            "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
-            "dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
-            "gdtr=%016RX64:%04x  idtr=%016RX64:%04x  eflags=%08x\n"
-            "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
-            "tr  ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
-            "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
-            ,
-            pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
-            pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
-            pCtx->r14, pCtx->r15,
-            pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
-            (RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
-            (RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
-            (RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
-            (RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
-            (RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
-            (RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
-            pCtx->cr0,  pCtx->cr2, pCtx->cr3,  pCtx->cr4,
-            pCtx->dr[0],  pCtx->dr[1], pCtx->dr[2],  pCtx->dr[3],
-            pCtx->dr[4],  pCtx->dr[5], pCtx->dr[6],  pCtx->dr[7],
-            pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
-            (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
-            (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
-            pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
+             "rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
+             "r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
+             "r14=%016RX64 r15=%016RX64\n"
+             "rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
+             "cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
+             "ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
+             "es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
+             "fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
+             "gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
+             "ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
+             "cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
+             "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
+             "dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
+             "gdtr=%016RX64:%04x  idtr=%016RX64:%04x  eflags=%08x\n"
+             "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
+             "tr  ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
+             "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
+             ,
+             pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
+             pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
+             pCtx->r14, pCtx->r15,
+             pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
+             pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
+             pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
+             pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
+             pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
+             pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
+             pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
+             pCtx->cr0,  pCtx->cr2, pCtx->cr3,  pCtx->cr4,
+             pCtx->dr[0],  pCtx->dr[1], pCtx->dr[2],  pCtx->dr[3],
+             pCtx->dr[4],  pCtx->dr[5], pCtx->dr[6],  pCtx->dr[7],
+             pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
+             pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
+             pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
+             pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
     }
     else
         Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
-            "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
-            "cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
-            "ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
-            "es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
-            "fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
-            "gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
-            "ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
-            "gdtr=%016RX64:%04x  idtr=%016RX64:%04x  eflags=%08x\n"
-            "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
-            "tr  ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
-            "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
-            ,
-            pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
-            pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
-            (RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0],  pCtx->dr[1],
-            (RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2],  pCtx->dr[3],
-            (RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4],  pCtx->dr[5],
-            (RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6],  pCtx->dr[7],
-            (RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0,  pCtx->cr2,
-            (RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3,  pCtx->cr4,
-            pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
-            (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
-            (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
-            pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
+             "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
+             "cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
+             "ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
+             "es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
+             "fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
+             "gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
+             "ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
+             "gdtr=%016RX64:%04x  idtr=%016RX64:%04x  eflags=%08x\n"
+             "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
+             "tr  ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
+             "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
+             ,
+             pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
+             pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
+             pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0],  pCtx->dr[1],
+             pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2],  pCtx->dr[3],
+             pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4],  pCtx->dr[5],
+             pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6],  pCtx->dr[7],
+             pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0,  pCtx->cr2,
+             pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3,  pCtx->cr4,
+             pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
+             pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
+             pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
+             pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
 
     Log(("FPU:\n"
Index: trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 41906)
@@ -923,5 +923,5 @@
 
     /* Set CPL */
-    pVMCB->guest.u8CPL     = pCtx->ssHid.Attr.n.u2Dpl;
+    pVMCB->guest.u8CPL     = pCtx->ss.Attr.n.u2Dpl;
 
     /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
@@ -946,6 +946,6 @@
 #endif
         /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
-        pVMCB->guest.FS.u64Base    = pCtx->fsHid.u64Base;
-        pVMCB->guest.GS.u64Base    = pCtx->gsHid.u64Base;
+        pVMCB->guest.FS.u64Base    = pCtx->fs.u64Base;
+        pVMCB->guest.GS.u64Base    = pCtx->gs.u64Base;
     }
     else
@@ -1644,17 +1644,17 @@
      * register (yet).
      */
-    if (   !pCtx->csHid.Attr.n.u1Granularity
-        &&  pCtx->csHid.Attr.n.u1Present
-        &&  pCtx->csHid.u32Limit > UINT32_C(0xfffff))
-    {
-        Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
-        pCtx->csHid.Attr.n.u1Granularity = 1;
+    if (   !pCtx->cs.Attr.n.u1Granularity
+        &&  pCtx->cs.Attr.n.u1Present
+        &&  pCtx->cs.u32Limit > UINT32_C(0xfffff))
+    {
+        Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
+        pCtx->cs.Attr.n.u1Granularity = 1;
     }
 #define SVM_ASSERT_SEL_GRANULARITY(reg) \
-        AssertMsg(   !pCtx->reg##Hid.Attr.n.u1Present \
-                  || (   pCtx->reg##Hid.Attr.n.u1Granularity \
-                      ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
-                      :  pCtx->reg##Hid.u32Limit <= 0xfffff), \
-                  ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
+        AssertMsg(   !pCtx->reg.Attr.n.u1Present \
+                  || (   pCtx->reg.Attr.n.u1Granularity \
+                      ? (pCtx->reg.u32Limit & 0xfff) == 0xfff \
+                      :  pCtx->reg.u32Limit <= 0xfffff), \
+                  ("%#x %#x %#llx\n", pCtx->reg.u32Limit, pCtx->reg.Attr.u, pCtx->reg.u64Base))
     SVM_ASSERT_SEL_GRANULARITY(ss);
     SVM_ASSERT_SEL_GRANULARITY(cs);
@@ -1672,5 +1672,5 @@
      */
     Assert(!(pVMCB->guest.u8CPL & ~0x3));
-    pCtx->ssHid.Attr.n.u2Dpl = pVMCB->guest.u8CPL & 0x3;
+    pCtx->ss.Attr.n.u2Dpl = pVMCB->guest.u8CPL & 0x3;
 
     /*
@@ -1775,5 +1775,5 @@
 #ifdef DBGFTRACE_ENABLED /** @todo DTrace */
     RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x at %04:%08RX64 %RX64 %RX64 %RX64",
-                      exitCode, pCtx->cs, pCtx->rip,
+                      exitCode, pCtx->cs.Sel, pCtx->rip,
                       pVMCB->ctrl.u64ExitInfo1, pVMCB->ctrl.u64ExitInfo2, pVMCB->ctrl.ExitIntInfo.au64[0]);
 #endif
@@ -1825,5 +1825,5 @@
             }
             /* Return to ring 3 to deal with the debug exit code. */
-            Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
+            Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
             break;
         }
@@ -2031,5 +2031,5 @@
                     break;
             }
-            Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
+            Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->esi));
             hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
             goto ResumeExecution;
@@ -2971,5 +2971,5 @@
      * Only allow 32 & 64 bit code.
      */
-    DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
+    DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs.Sel, &pRegFrame->cs);
     if (enmMode != DISCPUMODE_16BIT)
     {
Index: trunk/src/VBox/VMM/VMMR0/HWSVMR0.h
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWSVMR0.h	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR0/HWSVMR0.h	(revision 41906)
@@ -200,19 +200,25 @@
 #define SVM_HIDSEGATTR_SVM2VMX(a)     (a & 0xFF) | ((a & 0x0F00) << 4)
 
-#define SVM_WRITE_SELREG(REG, reg)                                                 \
-{                                                                                  \
-        pVMCB->guest.REG.u16Sel   = pCtx->reg;                                     \
-        pVMCB->guest.REG.u32Limit = pCtx->reg##Hid.u32Limit;                       \
-        pVMCB->guest.REG.u64Base  = pCtx->reg##Hid.u64Base;                        \
-        pVMCB->guest.REG.u16Attr  = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg##Hid.Attr.u); \
-}
-
-#define SVM_READ_SELREG(REG, reg)                                                    \
-{                                                                                    \
-        pCtx->reg                = pVMCB->guest.REG.u16Sel;                          \
-        pCtx->reg##Hid.u32Limit  = pVMCB->guest.REG.u32Limit;                        \
-        pCtx->reg##Hid.u64Base   = pVMCB->guest.REG.u64Base;                         \
-        pCtx->reg##Hid.Attr.u    = SVM_HIDSEGATTR_SVM2VMX(pVMCB->guest.REG.u16Attr); \
-}
+#define SVM_WRITE_SELREG(REG, reg) \
+    do \
+    { \
+        Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
+        Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
+        pVMCB->guest.REG.u16Sel     = pCtx->reg.Sel; \
+        pVMCB->guest.REG.u32Limit   = pCtx->reg.u32Limit; \
+        pVMCB->guest.REG.u64Base    = pCtx->reg.u64Base; \
+        pVMCB->guest.REG.u16Attr    = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg.Attr.u); \
+    } while (0)
+
+#define SVM_READ_SELREG(REG, reg) \
+    do \
+    { \
+        pCtx->reg.Sel       = pVMCB->guest.REG.u16Sel; \
+        pCtx->reg.ValidSel  = pVMCB->guest.REG.u16Sel; \
+        pCtx->reg.fFlags    = CPUMSELREG_FLAGS_VALID; \
+        pCtx->reg.u32Limit  = pVMCB->guest.REG.u32Limit; \
+        pCtx->reg.u64Base   = pVMCB->guest.REG.u64Base; \
+        pCtx->reg.Attr.u    = SVM_HIDSEGATTR_SVM2VMX(pVMCB->guest.REG.u16Attr); \
+    } while (0)
 
 #endif /* IN_RING0 */
@@ -222,4 +228,4 @@
 RT_C_DECLS_END
 
-#endif /* ___VMMR0_HWSVMR0_h */
-
+#endif /* !___VMMR0_HWSVMR0_h */
+
Index: trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 41906)
@@ -904,12 +904,12 @@
         /** @todo Check stack limit. */
         pCtx->sp -= 2;
-        LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
-        rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
+        LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss.Sel, pCtx->sp, pCtx->eflags.u));
+        rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
         pCtx->sp -= 2;
-        LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
-        rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
+        LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss.Sel, pCtx->sp, pCtx->cs.Sel));
+        rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
         pCtx->sp -= 2;
-        LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
-        rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
+        LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss.Sel, pCtx->sp, ip));
+        rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
 
         /*
@@ -917,6 +917,6 @@
          */
         pCtx->rip           = offset;
-        pCtx->cs            = sel;
-        pCtx->csHid.u64Base = sel << 4;
+        pCtx->cs.Sel        = sel;
+        pCtx->cs.u64Base    = sel << 4;
         pCtx->eflags.u     &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
 
@@ -1009,5 +1009,5 @@
                 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
                 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu,
-                     u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
+                     u8Interrupt, u8Interrupt, rc, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
                 if (RT_SUCCESS(rc))
                 {
@@ -1642,21 +1642,21 @@
                      * DPL of all hidden selector registers must match the current CPL (0).
                      */
-                    pCtx->csHid.Attr.n.u2Dpl  = 0;
-                    pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
-
-                    pCtx->dsHid.Attr.n.u2Dpl  = 0;
-                    pCtx->esHid.Attr.n.u2Dpl  = 0;
-                    pCtx->fsHid.Attr.n.u2Dpl  = 0;
-                    pCtx->gsHid.Attr.n.u2Dpl  = 0;
-                    pCtx->ssHid.Attr.n.u2Dpl  = 0;
+                    pCtx->cs.Attr.n.u2Dpl  = 0;
+                    pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
+
+                    pCtx->ds.Attr.n.u2Dpl  = 0;
+                    pCtx->es.Attr.n.u2Dpl  = 0;
+                    pCtx->fs.Attr.n.u2Dpl  = 0;
+                    pCtx->gs.Attr.n.u2Dpl  = 0;
+                    pCtx->ss.Attr.n.u2Dpl  = 0;
                 }
                 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
             }
             else if (   CPUMIsGuestInRealModeEx(pCtx)
-                     && pCtx->csHid.u64Base == 0xffff0000)
+                     && pCtx->cs.u64Base == 0xffff0000)
             {
                 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
-                pCtx->csHid.u64Base = 0xf0000;
-                pCtx->cs = 0xf000;
+                pCtx->cs.u64Base = 0xf0000;
+                pCtx->cs.Sel     =  0xf000;
             }
         }
@@ -1686,5 +1686,5 @@
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
     {
-        if (pCtx->ldtr == 0)
+        if (pCtx->ldtr.Sel == 0)
         {
             rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR,         0);
@@ -1696,8 +1696,8 @@
         else
         {
-            rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR,         pCtx->ldtr);
-            rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT,         pCtx->ldtrHid.u32Limit);
-            rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE,        pCtx->ldtrHid.u64Base);
-            rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
+            rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR,         pCtx->ldtr.Sel);
+            rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT,         pCtx->ldtr.u32Limit);
+            rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE,        pCtx->ldtr.u64Base);
+            rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr.Attr.u);
         }
         AssertRC(rc);
@@ -1735,9 +1735,9 @@
         else
         {
-            rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR,         pCtx->tr);
-            rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT,         pCtx->trHid.u32Limit);
-            rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE,        pCtx->trHid.u64Base);
-
-            val = pCtx->trHid.Attr.u;
+            rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR,         pCtx->tr.Sel);
+            rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT,         pCtx->tr.u32Limit);
+            rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE,        pCtx->tr.u64Base);
+
+            val = pCtx->tr.Attr.u;
 
             /* The TSS selector must be busy (REM bugs? see defect #XXXX). */
@@ -2076,7 +2076,7 @@
         {
             /* Update these as wrmsr might have changed them. */
-            rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
+            rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fs.u64Base);
             AssertRC(rc);
-            rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
+            rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gs.u64Base);
             AssertRC(rc);
         }
@@ -3215,5 +3215,5 @@
 #endif
 
-    Log2(("E%d: New EIP=%x:%RGv\n", (uint32_t)exitReason, pCtx->cs, (RTGCPTR)pCtx->rip));
+    Log2(("E%d: New EIP=%x:%RGv\n", (uint32_t)exitReason, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
     Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
     Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
@@ -3233,5 +3233,5 @@
 #ifdef DBGFTRACE_ENABLED /** @todo DTrace later. */
     RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x %016RX64 at %04:%08RX64 %RX64",
-                      exitReason, (uint64_t)exitQualification, pCtx->cs, pCtx->rip, (uint64_t)intInfo);
+                      exitReason, (uint64_t)exitQualification, pCtx->cs.Sel, pCtx->rip, (uint64_t)intInfo);
 #endif
     STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
@@ -3445,5 +3445,5 @@
                     break;
                 }
-                Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
+                Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
                 rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
                                          cbInstr, errCode);
@@ -3506,5 +3506,5 @@
                 }
                 /* Return to ring 3 to deal with the debug exit code. */
-                Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
+                Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
                 break;
             }
@@ -3516,5 +3516,5 @@
                 if (rc == VINF_EM_RAW_GUEST_TRAP)
                 {
-                    Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
+                    Log(("Guest #BP at %04x:%RGv\n", pCtx->cs.Sel, pCtx->rip));
                     rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
                                              cbInstr, errCode);
@@ -3528,5 +3528,5 @@
                     goto ResumeExecution;
                 }
-                Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
+                Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
                 break;
             }
@@ -3542,5 +3542,5 @@
                     ||  !pVM->hwaccm.s.vmx.pRealModeTSS)
                 {
-                    Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
+                    Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, errCode));
                     rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
                                              cbInstr, errCode);
@@ -3552,5 +3552,5 @@
                 Assert(CPUMIsGuestInRealModeEx(pCtx));
 
-                LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip));
+                LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
 
                 rc2 = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
@@ -3695,11 +3695,12 @@
                         }
                         pCtx->ip            = aIretFrame[0];
-                        pCtx->cs            = aIretFrame[1];
-                        pCtx->csHid.u64Base = pCtx->cs << 4;
+                        pCtx->cs.Sel        = aIretFrame[1];
+                        pCtx->cs.ValidSel   = aIretFrame[1];
+                        pCtx->cs.u64Base    = (uint32_t)pCtx->cs.Sel << 4;
                         pCtx->eflags.u      =   (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask))
                                               | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
                         pCtx->sp           += sizeof(aIretFrame);
 
-                        LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
+                        LogFlow(("iret to %04x:%x\n", pCtx->cs.Sel, pCtx->ip));
                         fUpdateRIP = false;
                         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
@@ -3813,5 +3814,5 @@
                 }
 
-                Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
+                Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
                 rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
                                          cbInstr, errCode);
@@ -3827,5 +3828,5 @@
                     &&  pVM->hwaccm.s.vmx.pRealModeTSS)
                 {
-                    Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
+                    Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs.Sel, pCtx->eip, errCode));
                     rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
                                             cbInstr, errCode);
Index: trunk/src/VBox/VMM/VMMR0/HWVMXR0.h
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWVMXR0.h	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR0/HWVMXR0.h	(revision 41906)
@@ -217,13 +217,14 @@
 
 # define VMX_WRITE_SELREG(REG, reg) \
-{                                                                                               \
-        rc  = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG,      pCtx->reg);                       \
-        rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,    pCtx->reg##Hid.u32Limit);         \
-        rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_##REG##_BASE,     pCtx->reg##Hid.u64Base);        \
+    do \
+    { \
+        rc  = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG,        pCtx->reg.Sel);                 \
+        rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,      pCtx->reg.u32Limit);            \
+        rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_##REG##_BASE,     pCtx->reg.u64Base);             \
         if ((pCtx->eflags.u32 & X86_EFL_VM))                                                    \
         {                                                                                       \
             /* Must override this or else VT-x will fail with invalid guest state errors. */    \
             /* DPL=3, present, code/data, r/w/accessed. */                                      \
-            val = (pCtx->reg##Hid.Attr.u & ~0xFF) | 0xF3;                                       \
+            val = (pCtx->reg.Attr.u & ~0xFF) | 0xF3;                                            \
         }                                                                                       \
         else                                                                                    \
@@ -236,11 +237,11 @@
         }                                                                                       \
         else                                                                                    \
-        if (   (   pCtx->reg                                                                    \
+        if (   (   pCtx->reg.Sel                                                                \
                 || !CPUMIsGuestInPagedProtectedModeEx(pCtx)                                     \
-                || (!pCtx->csHid.Attr.n.u1DefBig && !CPUMIsGuestIn64BitCodeEx(pCtx))            \
+                || (!pCtx->cs.Attr.n.u1DefBig && !CPUMIsGuestIn64BitCodeEx(pCtx))               \
                 )                                                                               \
-            && pCtx->reg##Hid.Attr.n.u1Present == 1)                                            \
+            && pCtx->reg.Attr.n.u1Present == 1)                                                 \
         {                                                                                       \
-            val = pCtx->reg##Hid.Attr.u | X86_SEL_TYPE_ACCESSED;                                \
+            val = pCtx->reg.Attr.u | X86_SEL_TYPE_ACCESSED;                                     \
         }                                                                                       \
         else                                                                                    \
@@ -248,30 +249,34 @@
                                                                                                 \
         rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, val);                        \
-}
+    } while (0)
 
 # define VMX_READ_SELREG(REG, reg) \
-{                                                                          \
-        VMXReadCachedVMCS(VMX_VMCS16_GUEST_FIELD_##REG,           &val);   \
-        pCtx->reg                = val;                                    \
-        VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,         &val);   \
-        pCtx->reg##Hid.u32Limit    = val;                                  \
-        VMXReadCachedVMCS(VMX_VMCS64_GUEST_##REG##_BASE,          &val);   \
-        pCtx->reg##Hid.u64Base     = val;                                  \
-        VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val);   \
-        pCtx->reg##Hid.Attr.u    = val;                                    \
-}
+    do \
+    { \
+        VMXReadCachedVMCS(VMX_VMCS16_GUEST_FIELD_##REG,           &val); \
+        pCtx->reg.Sel       = val; \
+        pCtx->reg.ValidSel  = val; \
+        pCtx->reg.fFlags    = CPUMSELREG_FLAGS_VALID; \
+        VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,         &val); \
+        pCtx->reg.u32Limit  = val; \
+        VMXReadCachedVMCS(VMX_VMCS64_GUEST_##REG##_BASE,          &val); \
+        pCtx->reg.u64Base   = val; \
+        VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \
+        pCtx->reg.Attr.u    = val; \
+    } while (0)
 
 /* Don't read from the cache in this macro; used only in case of failure where the cache is out of sync. */
 # define VMX_LOG_SELREG(REG, szSelReg, val) \
-{                                                                          \
-        VMXReadVMCS(VMX_VMCS16_GUEST_FIELD_##REG,           &(val));       \
-        Log(("%s Selector     %x\n", szSelReg, (val)));                    \
-        VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,         &(val));       \
-        Log(("%s Limit        %x\n", szSelReg, (val)));                    \
-        VMXReadVMCS(VMX_VMCS64_GUEST_##REG##_BASE,          &(val));       \
-        Log(("%s Base         %RX64\n", szSelReg, (uint64_t)(val)));       \
-        VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val));       \
-        Log(("%s Attributes   %x\n", szSelReg, (val)));                    \
-}
+    do \
+    { \
+        VMXReadVMCS(VMX_VMCS16_GUEST_FIELD_##REG,           &(val)); \
+        Log(("%s Selector     %x\n", szSelReg, (val))); \
+        VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,         &(val)); \
+        Log(("%s Limit        %x\n", szSelReg, (val))); \
+        VMXReadVMCS(VMX_VMCS64_GUEST_##REG##_BASE,          &(val)); \
+        Log(("%s Base         %RX64\n", szSelReg, (uint64_t)(val))); \
+        VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val)); \
+        Log(("%s Attributes   %x\n", szSelReg, (val))); \
+    } while (0)
 
 /**
Index: trunk/src/VBox/VMM/VMMR3/CPUM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 41906)
@@ -176,15 +176,15 @@
     SSMFIELD_ENTRY(         CPUMCTX, rsp),
     SSMFIELD_ENTRY_OLD(              lss_esp, sizeof(uint32_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, ss),
+    SSMFIELD_ENTRY(         CPUMCTX, ss.Sel),
     SSMFIELD_ENTRY_OLD(              ssPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, gs),
+    SSMFIELD_ENTRY(         CPUMCTX, gs.Sel),
     SSMFIELD_ENTRY_OLD(              gsPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, fs),
+    SSMFIELD_ENTRY(         CPUMCTX, fs.Sel),
     SSMFIELD_ENTRY_OLD(              fsPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, es),
+    SSMFIELD_ENTRY(         CPUMCTX, es.Sel),
     SSMFIELD_ENTRY_OLD(              esPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, ds),
+    SSMFIELD_ENTRY(         CPUMCTX, ds.Sel),
     SSMFIELD_ENTRY_OLD(              dsPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, cs),
+    SSMFIELD_ENTRY(         CPUMCTX, cs.Sel),
     SSMFIELD_ENTRY_OLD(              csPadding, sizeof(uint16_t)*3),
     SSMFIELD_ENTRY(         CPUMCTX, rflags),
@@ -198,22 +198,22 @@
     SSMFIELD_ENTRY(         CPUMCTX, r14),
     SSMFIELD_ENTRY(         CPUMCTX, r15),
-    SSMFIELD_ENTRY(         CPUMCTX, esHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, esHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, esHid.Attr),
-    SSMFIELD_ENTRY(         CPUMCTX, csHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, csHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, csHid.Attr),
-    SSMFIELD_ENTRY(         CPUMCTX, ssHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, ssHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, ssHid.Attr),
-    SSMFIELD_ENTRY(         CPUMCTX, dsHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, dsHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, dsHid.Attr),
-    SSMFIELD_ENTRY(         CPUMCTX, fsHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, fsHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, fsHid.Attr),
-    SSMFIELD_ENTRY(         CPUMCTX, gsHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, gsHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, gsHid.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, es.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, es.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, es.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, cs.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, cs.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, cs.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, ss.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, ss.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, ss.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, ds.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, ds.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, ds.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, fs.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, fs.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, fs.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, gs.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, gs.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, gs.Attr),
     SSMFIELD_ENTRY(         CPUMCTX, cr0),
     SSMFIELD_ENTRY(         CPUMCTX, cr2),
@@ -234,7 +234,7 @@
     SSMFIELD_ENTRY(         CPUMCTX, idtr.pIdt),
     SSMFIELD_ENTRY_OLD(              idtrPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, ldtr),
+    SSMFIELD_ENTRY(         CPUMCTX, ldtr.Sel),
     SSMFIELD_ENTRY_OLD(              ldtrPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(         CPUMCTX, tr),
+    SSMFIELD_ENTRY(         CPUMCTX, tr.Sel),
     SSMFIELD_ENTRY_OLD(              trPadding, sizeof(uint16_t)),
     SSMFIELD_ENTRY(         CPUMCTX, SysEnter.cs),
@@ -248,10 +248,10 @@
     SSMFIELD_ENTRY(         CPUMCTX, msrSFMASK),
     SSMFIELD_ENTRY(         CPUMCTX, msrKERNELGSBASE),
-    SSMFIELD_ENTRY(         CPUMCTX, ldtrHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, ldtrHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, ldtrHid.Attr),
-    SSMFIELD_ENTRY(         CPUMCTX, trHid.u64Base),
-    SSMFIELD_ENTRY(         CPUMCTX, trHid.u32Limit),
-    SSMFIELD_ENTRY(         CPUMCTX, trHid.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, ldtr.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, ldtr.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, ldtr.Attr),
+    SSMFIELD_ENTRY(         CPUMCTX, tr.u64Base),
+    SSMFIELD_ENTRY(         CPUMCTX, tr.u32Limit),
+    SSMFIELD_ENTRY(         CPUMCTX, tr.Attr),
     SSMFIELD_ENTRY_TERM()
 };
@@ -305,16 +305,16 @@
     SSMFIELD_ENTRY(             CPUMCTX, rcx),
     SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, rsp),
-    SSMFIELD_ENTRY(             CPUMCTX, ss),
+    SSMFIELD_ENTRY(             CPUMCTX, ss.Sel),
     SSMFIELD_ENTRY_OLD(                  ssPadding, sizeof(uint16_t)),
     SSMFIELD_ENTRY_OLD(         CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
-    SSMFIELD_ENTRY(             CPUMCTX, gs),
+    SSMFIELD_ENTRY(             CPUMCTX, gs.Sel),
     SSMFIELD_ENTRY_OLD(                  gsPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(             CPUMCTX, fs),
+    SSMFIELD_ENTRY(             CPUMCTX, fs.Sel),
     SSMFIELD_ENTRY_OLD(                  fsPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(             CPUMCTX, es),
+    SSMFIELD_ENTRY(             CPUMCTX, es.Sel),
     SSMFIELD_ENTRY_OLD(                  esPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(             CPUMCTX, ds),
+    SSMFIELD_ENTRY(             CPUMCTX, ds.Sel),
     SSMFIELD_ENTRY_OLD(                  dsPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(             CPUMCTX, cs),
+    SSMFIELD_ENTRY(             CPUMCTX, cs.Sel),
     SSMFIELD_ENTRY_OLD(                  csPadding, sizeof(uint16_t)*3),
     SSMFIELD_ENTRY(             CPUMCTX, rflags),
@@ -328,22 +328,22 @@
     SSMFIELD_ENTRY(             CPUMCTX, r14),
     SSMFIELD_ENTRY(             CPUMCTX, r15),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, esHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, esHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, esHid.Attr),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, csHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, csHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, csHid.Attr),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, ssHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, ssHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, ssHid.Attr),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, dsHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, dsHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, dsHid.Attr),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, fsHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, fsHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, fsHid.Attr),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, gsHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, gsHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, gsHid.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, es.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, es.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, es.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, cs.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, cs.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, cs.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, ss.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, ss.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, ss.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, ds.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, ds.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, ds.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, fs.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, fs.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, fs.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, gs.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, gs.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, gs.Attr),
     SSMFIELD_ENTRY(             CPUMCTX, cr0),
     SSMFIELD_ENTRY(             CPUMCTX, cr2),
@@ -367,7 +367,7 @@
     SSMFIELD_ENTRY_OLD(                  idtrPadding, sizeof(uint16_t)),
     SSMFIELD_ENTRY_OLD(                  idtrPadding64, sizeof(uint64_t)),
-    SSMFIELD_ENTRY(             CPUMCTX, ldtr),
+    SSMFIELD_ENTRY(             CPUMCTX, ldtr.Sel),
     SSMFIELD_ENTRY_OLD(                  ldtrPadding, sizeof(uint16_t)),
-    SSMFIELD_ENTRY(             CPUMCTX, tr),
+    SSMFIELD_ENTRY(             CPUMCTX, tr.Sel),
     SSMFIELD_ENTRY_OLD(                  trPadding, sizeof(uint16_t)),
     SSMFIELD_ENTRY(             CPUMCTX, SysEnter.cs),
@@ -383,10 +383,10 @@
     SSMFIELD_ENTRY_OLD(                  msrGSBASE, sizeof(uint64_t)),
     SSMFIELD_ENTRY(             CPUMCTX, msrKERNELGSBASE),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, ldtrHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, ldtrHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, ldtrHid.Attr),
-    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, trHid.u64Base),
-    SSMFIELD_ENTRY(             CPUMCTX, trHid.u32Limit),
-    SSMFIELD_ENTRY(             CPUMCTX, trHid.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, ldtr.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, ldtr.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, ldtr.Attr),
+    SSMFIELD_ENTRY_U32_ZX_U64(  CPUMCTX, tr.u64Base),
+    SSMFIELD_ENTRY(             CPUMCTX, tr.u32Limit),
+    SSMFIELD_ENTRY(             CPUMCTX, tr.Attr),
     SSMFIELD_ENTRY_OLD(                  padding, sizeof(uint32_t)*2),
     SSMFIELD_ENTRY_TERM()
@@ -1358,46 +1358,55 @@
     pCtx->eflags.Bits.u1Reserved0   = 1;
 
-    pCtx->cs                        = 0xf000;
-    pCtx->csHid.u64Base             = UINT64_C(0xffff0000);
-    pCtx->csHid.u32Limit            = 0x0000ffff;
-    pCtx->csHid.Attr.n.u1DescType   = 1; /* code/data segment */
-    pCtx->csHid.Attr.n.u1Present    = 1;
-    pCtx->csHid.Attr.n.u4Type       = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
-
-    pCtx->dsHid.u32Limit            = 0x0000ffff;
-    pCtx->dsHid.Attr.n.u1DescType   = 1; /* code/data segment */
-    pCtx->dsHid.Attr.n.u1Present    = 1;
-    pCtx->dsHid.Attr.n.u4Type       = X86_SEL_TYPE_RW;
-
-    pCtx->esHid.u32Limit            = 0x0000ffff;
-    pCtx->esHid.Attr.n.u1DescType   = 1; /* code/data segment */
-    pCtx->esHid.Attr.n.u1Present    = 1;
-    pCtx->esHid.Attr.n.u4Type       = X86_SEL_TYPE_RW;
-
-    pCtx->fsHid.u32Limit            = 0x0000ffff;
-    pCtx->fsHid.Attr.n.u1DescType   = 1; /* code/data segment */
-    pCtx->fsHid.Attr.n.u1Present    = 1;
-    pCtx->fsHid.Attr.n.u4Type       = X86_SEL_TYPE_RW;
-
-    pCtx->gsHid.u32Limit            = 0x0000ffff;
-    pCtx->gsHid.Attr.n.u1DescType   = 1; /* code/data segment */
-    pCtx->gsHid.Attr.n.u1Present    = 1;
-    pCtx->gsHid.Attr.n.u4Type       = X86_SEL_TYPE_RW;
-
-    pCtx->ssHid.u32Limit            = 0x0000ffff;
-    pCtx->ssHid.Attr.n.u1Present    = 1;
-    pCtx->ssHid.Attr.n.u1DescType   = 1; /* code/data segment */
-    pCtx->ssHid.Attr.n.u4Type       = X86_SEL_TYPE_RW;
+    pCtx->cs.Sel                    = 0xf000;
+    pCtx->cs.ValidSel               = 0xf000;
+    pCtx->cs.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.u64Base                = UINT64_C(0xffff0000);
+    pCtx->cs.u32Limit               = 0x0000ffff;
+    pCtx->cs.Attr.n.u1DescType      = 1; /* code/data segment */
+    pCtx->cs.Attr.n.u1Present       = 1;
+    pCtx->cs.Attr.n.u4Type          = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
+
+    pCtx->ds.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->ds.u32Limit               = 0x0000ffff;
+    pCtx->ds.Attr.n.u1DescType      = 1; /* code/data segment */
+    pCtx->ds.Attr.n.u1Present       = 1;
+    pCtx->ds.Attr.n.u4Type          = X86_SEL_TYPE_RW;
+
+    pCtx->es.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->es.u32Limit               = 0x0000ffff;
+    pCtx->es.Attr.n.u1DescType      = 1; /* code/data segment */
+    pCtx->es.Attr.n.u1Present       = 1;
+    pCtx->es.Attr.n.u4Type          = X86_SEL_TYPE_RW;
+
+    pCtx->fs.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->fs.u32Limit               = 0x0000ffff;
+    pCtx->fs.Attr.n.u1DescType      = 1; /* code/data segment */
+    pCtx->fs.Attr.n.u1Present       = 1;
+    pCtx->fs.Attr.n.u4Type          = X86_SEL_TYPE_RW;
+
+    pCtx->gs.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->gs.u32Limit               = 0x0000ffff;
+    pCtx->gs.Attr.n.u1DescType      = 1; /* code/data segment */
+    pCtx->gs.Attr.n.u1Present       = 1;
+    pCtx->gs.Attr.n.u4Type          = X86_SEL_TYPE_RW;
+
+    pCtx->ss.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->ss.u32Limit               = 0x0000ffff;
+    pCtx->ss.Attr.n.u1Present       = 1;
+    pCtx->ss.Attr.n.u1DescType      = 1; /* code/data segment */
+    pCtx->ss.Attr.n.u4Type          = X86_SEL_TYPE_RW;
 
     pCtx->idtr.cbIdt                = 0xffff;
     pCtx->gdtr.cbGdt                = 0xffff;
 
-    pCtx->ldtrHid.u32Limit          = 0xffff;
-    pCtx->ldtrHid.Attr.n.u1Present  = 1;
-    pCtx->ldtrHid.Attr.n.u4Type     = X86_SEL_TYPE_SYS_LDT;
-
-    pCtx->trHid.u32Limit            = 0xffff;
-    pCtx->trHid.Attr.n.u1Present    = 1;
-    pCtx->trHid.Attr.n.u4Type       = X86_SEL_TYPE_SYS_386_TSS_BUSY;    /* Deduction, not properly documented by Intel. */
+    pCtx->ldtr.fFlags               = CPUMSELREG_FLAGS_VALID;
+    pCtx->ldtr.u32Limit             = 0xffff;
+    pCtx->ldtr.Attr.n.u1Present     = 1;
+    pCtx->ldtr.Attr.n.u4Type        = X86_SEL_TYPE_SYS_LDT;
+
+    pCtx->tr.fFlags                 = CPUMSELREG_FLAGS_VALID;
+    pCtx->tr.u32Limit               = 0xffff;
+    pCtx->tr.Attr.n.u1Present       = 1;
+    pCtx->tr.Attr.n.u4Type          = X86_SEL_TYPE_SYS_386_TSS_BUSY;    /* Deduction, not properly documented by Intel. */
 
     pCtx->dr[6]                     = X86_DR6_INIT_VAL;
@@ -2614,6 +2623,6 @@
                     pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
                     pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
-                    pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
-                    pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
+                    pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
+                    pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
             else
                 pHlp->pfnPrintf(pHlp,
@@ -2623,6 +2632,6 @@
                     pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
                     pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
-                    pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
-                    pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
+                    pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
+                    pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
             break;
 
@@ -2642,8 +2651,8 @@
                     pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
                     pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
-                    pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
-                    pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
+                    pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
+                    pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
                     pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
-                    pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
+                    pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
             else
                 pHlp->pfnPrintf(pHlp,
@@ -2655,8 +2664,8 @@
                     pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
                     pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
-                    pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
-                    pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
+                    pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
+                    pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
                     pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
-                    pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
+                    pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
             break;
 
@@ -2687,16 +2696,16 @@
                     pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
                     pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
-                    pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
+                    pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
+                    pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
+                    pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
+                    pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
+                    pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
+                    pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
                     pszPrefix, pCtx->cr0,  pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3,  pszPrefix, pCtx->cr4,
                     pszPrefix, pCtx->dr[0],  pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2],  pszPrefix, pCtx->dr[3],
                     pszPrefix, pCtx->dr[4],  pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6],  pszPrefix, pCtx->dr[7],
                     pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
-                    pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
+                    pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
+                    pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
                     pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
             else
@@ -2717,13 +2726,13 @@
                     pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
                     pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
-                    pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0],  pszPrefix, pCtx->dr[1],
-                    pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2],  pszPrefix, pCtx->dr[3],
-                    pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4],  pszPrefix, pCtx->dr[5],
-                    pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6],  pszPrefix, pCtx->dr[7],
-                    pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0,  pszPrefix, pCtx->cr2,
-                    pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3,  pszPrefix, pCtx->cr4,
+                    pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0],  pszPrefix, pCtx->dr[1],
+                    pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2],  pszPrefix, pCtx->dr[3],
+                    pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4],  pszPrefix, pCtx->dr[5],
+                    pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6],  pszPrefix, pCtx->dr[7],
+                    pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0,  pszPrefix, pCtx->cr2,
+                    pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3,  pszPrefix, pCtx->cr4,
                     pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
-                    pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
-                    pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
+                    pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
+                    pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
                     pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
 
@@ -2964,8 +2973,8 @@
             /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
             /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
-            (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
+            pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
             pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
             pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
-            (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
+            (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
             pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
     }
@@ -3000,5 +3009,5 @@
             pCtx->r14, pCtx->r15,
             X86_EFL_GET_IOPL(efl), szEFlags,
-            (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
+            pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
             pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
             pCtx->cr4, pCtx->ldtr, pCtx->tr,
@@ -3827,11 +3836,11 @@
         if (CPUMAreHiddenSelRegsValid(pVCpu))
         {
-            State.f64Bits         = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
-            State.GCPtrSegBase    = pCtx->csHid.u64Base;
-            State.GCPtrSegEnd     = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
-            State.cbSegLimit      = pCtx->csHid.u32Limit;
+            State.f64Bits         = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
+            State.GCPtrSegBase    = pCtx->cs.u64Base;
+            State.GCPtrSegEnd     = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
+            State.cbSegLimit      = pCtx->cs.u32Limit;
             enmDisCpuMode         = (State.f64Bits)
                                     ? DISCPUMODE_64BIT
-                                    : pCtx->csHid.Attr.n.u1DefBig
+                                    : pCtx->cs.Attr.n.u1DefBig
                                     ? DISCPUMODE_32BIT
                                     : DISCPUMODE_16BIT;
@@ -3841,8 +3850,8 @@
             DBGFSELINFO SelInfo;
 
-            rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
+            rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs.Sel, &SelInfo);
             if (RT_FAILURE(rc))
             {
-                AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
+                AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs.Sel, GCPtrPC, rc));
                 return rc;
             }
@@ -3851,8 +3860,8 @@
              * Validate the selector.
              */
-            rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
+            rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss.Sel);
             if (RT_FAILURE(rc))
             {
-                AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
+                AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs.Sel, GCPtrPC, rc));
                 return rc;
             }
@@ -3867,5 +3876,5 @@
         /* real or V86 mode */
         enmDisCpuMode         = DISCPUMODE_16BIT;
-        State.GCPtrSegBase    = pCtx->cs * 16;
+        State.GCPtrSegBase    = pCtx->cs.Sel * 16;
         State.GCPtrSegEnd     = 0xFFFFFFFF;
         State.cbSegLimit      = 0xFFFFFFFF;
@@ -3895,5 +3904,5 @@
     }
     else
-        Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
+        Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
 
     /* Release mapping lock acquired in cpumR3DisasInstrRead. */
@@ -4009,5 +4018,5 @@
      * Are we in Ring-0?
      */
-    if (    pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
+    if (    pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
         &&  !pCtxCore->eflags.Bits.u1VM)
     {
@@ -4020,11 +4029,11 @@
          * Set CPL to Ring-1.
          */
-        pCtxCore->ss |= 1;
-        if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
-            pCtxCore->cs |= 1;
+        pCtxCore->ss.Sel |= 1;
+        if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
+            pCtxCore->cs.Sel |= 1;
     }
     else
     {
-        AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
+        AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
                   ("ring-1 code not supported\n"));
         /*
@@ -4043,7 +4052,7 @@
      */
     AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
-    AssertReleaseMsg(   pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
+    AssertReleaseMsg(   pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL)
                      || pCtxCore->eflags.Bits.u1VM,
-                     ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
+                     ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
     Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
 
@@ -4082,12 +4091,12 @@
     if (!pCtxCore)
         pCtxCore = CPUMCTX2CORE(pCtx);
-    Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss & X86_SEL_RPL));
-    AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
-              ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
+    Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
+    AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
+              ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
 
     /*
      * Are we executing in raw ring-1?
      */
-    if (    (pCtxCore->ss & X86_SEL_RPL) == 1
+    if (    (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
         &&  !pCtxCore->eflags.Bits.u1VM)
     {
@@ -4098,19 +4107,19 @@
         /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
         /** @todo See what happens if we remove this. */
-        if ((pCtxCore->ds & X86_SEL_RPL) == 1)
-            pCtxCore->ds &= ~X86_SEL_RPL;
-        if ((pCtxCore->es & X86_SEL_RPL) == 1)
-            pCtxCore->es &= ~X86_SEL_RPL;
-        if ((pCtxCore->fs & X86_SEL_RPL) == 1)
-            pCtxCore->fs &= ~X86_SEL_RPL;
-        if ((pCtxCore->gs & X86_SEL_RPL) == 1)
-            pCtxCore->gs &= ~X86_SEL_RPL;
+        if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
+            pCtxCore->ds.Sel &= ~X86_SEL_RPL;
+        if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
+            pCtxCore->es.Sel &= ~X86_SEL_RPL;
+        if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
+            pCtxCore->fs.Sel &= ~X86_SEL_RPL;
+        if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
+            pCtxCore->gs.Sel &= ~X86_SEL_RPL;
 
         /*
          * Ring-1 selector => Ring-0.
          */
-        pCtxCore->ss &= ~X86_SEL_RPL;
-        if ((pCtxCore->cs & X86_SEL_RPL) == 1)
-            pCtxCore->cs &= ~X86_SEL_RPL;
+        pCtxCore->ss.Sel &= ~X86_SEL_RPL;
+        if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
+            pCtxCore->cs.Sel &= ~X86_SEL_RPL;
     }
     else
@@ -4123,12 +4132,12 @@
         {
             /** @todo See what happens if we remove this. */
-            if ((pCtxCore->ds & X86_SEL_RPL) == 1)
-                pCtxCore->ds &= ~X86_SEL_RPL;
-            if ((pCtxCore->es & X86_SEL_RPL) == 1)
-                pCtxCore->es &= ~X86_SEL_RPL;
-            if ((pCtxCore->fs & X86_SEL_RPL) == 1)
-                pCtxCore->fs &= ~X86_SEL_RPL;
-            if ((pCtxCore->gs & X86_SEL_RPL) == 1)
-                pCtxCore->gs &= ~X86_SEL_RPL;
+            if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
+                pCtxCore->ds.Sel &= ~X86_SEL_RPL;
+            if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
+                pCtxCore->es.Sel &= ~X86_SEL_RPL;
+            if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
+                pCtxCore->fs.Sel &= ~X86_SEL_RPL;
+            if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
+                pCtxCore->gs.Sel &= ~X86_SEL_RPL;
         }
     }
Index: trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp	(revision 41906)
@@ -1013,8 +1013,8 @@
 
 #define CPU_REG_SEG(UName, LName) \
-    CPU_REG_RW_AS(#LName,           UName,          U16, LName,                 cpumR3RegGet_Generic, cpumR3RegSet_seg,     NULL,                       NULL                ), \
-    CPU_REG_RW_AS(#LName "_attr",   UName##_ATTR,   U32, LName##Hid.Attr.u,     cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       g_aCpumRegFields_seg), \
-    CPU_REG_RW_AS(#LName "_base",   UName##_BASE,   U64, LName##Hid.u64Base,    cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       NULL                ), \
-    CPU_REG_RW_AS(#LName "_lim",    UName##_LIMIT,  U32, LName##Hid.u32Limit,   cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       NULL                )
+    CPU_REG_RW_AS(#LName,           UName,          U16, LName.Sel,             cpumR3RegGet_Generic, cpumR3RegSet_seg,     NULL,                       NULL                ), \
+    CPU_REG_RW_AS(#LName "_attr",   UName##_ATTR,   U32, LName.Attr.u,          cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       g_aCpumRegFields_seg), \
+    CPU_REG_RW_AS(#LName "_base",   UName##_BASE,   U64, LName.u64Base,         cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       NULL                ), \
+    CPU_REG_RW_AS(#LName "_lim",    UName##_LIMIT,  U32, LName.u32Limit,        cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       NULL                )
 
 #define CPU_REG_MM(n) \
Index: trunk/src/VBox/VMM/VMMR3/CSAM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/CSAM.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/CSAM.cpp	(revision 41906)
@@ -2295,5 +2295,5 @@
     {
         /* Assuming 32 bits code for now. */
-        Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == DISCPUMODE_32BIT);
+        Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs.Sel, &pCtxCore->cs) == DISCPUMODE_32BIT);
 
         pInstrGC = SELMToFlat(pVM, DISSELREG_CS, pCtxCore, pInstrGC);
Index: trunk/src/VBox/VMM/VMMR3/DBGF.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/DBGF.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/DBGF.cpp	(revision 41906)
@@ -588,5 +588,5 @@
         /* @todo SMP support!! */
         PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
-        RTGCPTR  eip = pCtx->rip + pCtx->csHid.u64Base;
+        RTGCPTR  eip = pCtx->rip + pCtx->cs.u64Base;
 #endif
         for (iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aBreakpoints); iBp++)
Index: trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp	(revision 41906)
@@ -353,6 +353,6 @@
         else
             pCtxCore = CPUMGetHyperCtxCore(pVCpu);
-        Sel        = pCtxCore->cs;
-        pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
+        Sel        = pCtxCore->cs.Sel;
+        pHiddenSel = (PCPUMSELREGHID)&pCtxCore->cs;
         GCPtr      = pCtxCore->rip;
     }
@@ -413,5 +413,5 @@
         {   /* Assume the current CS defines the execution mode. */
             pCtxCore   = CPUMGetGuestCtxCore(pVCpu);
-            pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
+            pHiddenSel = (CPUMSELREGHID *)&pCtxCore->cs;
 
             SelInfo.u.Raw.Gen.u1Present     = pHiddenSel->Attr.n.u1Present;
Index: trunk/src/VBox/VMM/VMMR3/DBGFStack.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/DBGFStack.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/DBGFStack.cpp	(revision 41906)
@@ -301,5 +301,5 @@
         pCur->AddrPC = *pAddrPC;
     else
-        rc = DBGFR3AddrFromSelOff(pVM, idCpu, &pCur->AddrPC, pCtxCore->cs, pCtxCore->rip);
+        rc = DBGFR3AddrFromSelOff(pVM, idCpu, &pCur->AddrPC, pCtxCore->cs.Sel, pCtxCore->rip);
     if (RT_SUCCESS(rc))
     {
@@ -341,10 +341,10 @@
             pCur->AddrStack = *pAddrStack;
         else
-            rc = DBGFR3AddrFromSelOff(pVM, idCpu, &pCur->AddrStack, pCtxCore->ss, pCtxCore->rsp & fAddrMask);
+            rc = DBGFR3AddrFromSelOff(pVM, idCpu, &pCur->AddrStack, pCtxCore->ss.Sel, pCtxCore->rsp & fAddrMask);
 
         if (pAddrFrame)
             pCur->AddrFrame = *pAddrFrame;
         else if (RT_SUCCESS(rc))
-            rc = DBGFR3AddrFromSelOff(pVM, idCpu, &pCur->AddrFrame, pCtxCore->ss, pCtxCore->rbp & fAddrMask);
+            rc = DBGFR3AddrFromSelOff(pVM, idCpu, &pCur->AddrFrame, pCtxCore->ss.Sel, pCtxCore->rbp & fAddrMask);
     }
     else
Index: trunk/src/VBox/VMM/VMMR3/EM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/EM.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/EM.cpp	(revision 41906)
@@ -965,7 +965,7 @@
 
     if (pCtx->eflags.Bits.u1VM)
-        Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
+        Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
     else
-        Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
+        Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
 #endif
     STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
@@ -1243,5 +1243,5 @@
     }
 
-    unsigned uSS = pCtx->ss;
+    unsigned uSS = pCtx->ss.Sel;
     if (    pCtx->eflags.Bits.u1VM
         ||  (uSS & X86_SEL_RPL) == 3)
@@ -1276,6 +1276,6 @@
         // Let's start with pure 32 bits ring 0 code first
         /** @todo What's pure 32-bit mode? flat? */
-        if (    !(pCtx->ssHid.Attr.n.u1DefBig)
-            ||  !(pCtx->csHid.Attr.n.u1DefBig))
+        if (    !(pCtx->ss.Attr.n.u1DefBig)
+            ||  !(pCtx->cs.Attr.n.u1DefBig))
         {
             Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
Index: trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp	(revision 41906)
@@ -231,5 +231,5 @@
 #endif /* 0 */
     STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
-    Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
+    Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
 #ifdef VBOX_WITH_REM
     EMRemLock(pVM);
@@ -469,5 +469,5 @@
     PCPUMCTX pCtx = pVCpu->em.s.pCtx;
 
-    LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
+    LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
     *pfFFDone = false;
 
@@ -509,5 +509,5 @@
          */
         if (TRPMHasTrap(pVCpu))
-            Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
+            Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
 
         uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
@@ -518,7 +518,7 @@
                 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
             else if (CPUMIsGuestIn64BitCodeEx(pCtx))
-                Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
+                Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
             else
-                Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs,          pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
+                Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs.Sel,          pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
         }
         else
@@ -527,7 +527,7 @@
                 Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
             else if (CPUMIsGuestIn64BitCodeEx(pCtx))
-                Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
+                Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
             else
-                Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs,          pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
+                Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel,          pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
         }
 #endif /* LOG_ENABLED */
Index: trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41906)
@@ -123,5 +123,5 @@
     PCPUMCTX    pCtx = pVCpu->em.s.pCtx;
     Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
-    Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
+    Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
 
     /*
@@ -131,5 +131,5 @@
     CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
     rc = VMMR3ResumeHyper(pVM, pVCpu);
-    Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
+    Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
     rc = CPUMR3RawLeave(pVCpu, NULL, rc);
     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
@@ -367,5 +367,5 @@
 
     STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
-    Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
+    Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
 #ifdef VBOX_WITH_REM
     EMRemLock(pVM);
@@ -578,5 +578,5 @@
      */
     /** @todo move this up before the dispatching? */
-    if (    (pCtx->ss & X86_SEL_RPL) <= 1
+    if (    (pCtx->ss.Sel & X86_SEL_RPL) <= 1
         &&  !pCtx->eflags.Bits.u1VM)
     {
@@ -643,5 +643,6 @@
     int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
     Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
-         pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "",  GCPhys, fFlags,
+         pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
+         (enmType == TRPM_SOFTWARE_INT) ? " software" : "",  GCPhys, fFlags,
          fFlags & X86_PTE_P  ? "P " : "NP", fFlags & X86_PTE_US ? "U"  : "S",
          fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G  ? " G" : "", rc2));
@@ -684,5 +685,6 @@
             {
                 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
-                                        (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0);
+                                           SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs)
+                                        == DISCPUMODE_32BIT ? PATMFL_CODE32 : 0);
                 if (RT_SUCCESS(rc))
                 {
@@ -929,10 +931,11 @@
             return VERR_EM_RAW_PATCH_CONFLICT;
         }
-        if (   (pCtx->ss & X86_SEL_RPL) == 0
+        if (   (pCtx->ss.Sel & X86_SEL_RPL) == 0
             && !pCtx->eflags.Bits.u1VM
             && !PATMIsPatchGCAddr(pVM, pCtx->eip))
         {
             int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
-                                        (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0);
+                                        (   SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs)
+                                         == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0);
             if (RT_SUCCESS(rc))
             {
@@ -1039,7 +1042,7 @@
         }
 #endif /* VBOX_WITH_STATISTICS */
-        if (    (pCtx->ss & X86_SEL_RPL) == 0
+        if (    (pCtx->ss.Sel & X86_SEL_RPL) == 0
             &&  !pCtx->eflags.Bits.u1VM
-            &&  SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT)
+            &&  SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs) == DISCPUMODE_32BIT)
         {
             STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
@@ -1339,5 +1342,5 @@
     int      rc = VERR_IPE_UNINITIALIZED_STATUS;
     PCPUMCTX pCtx = pVCpu->em.s.pCtx;
-    LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
+    LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
     pVCpu->em.s.fForceRAW = false;
     *pfFFDone = false;
@@ -1361,5 +1364,5 @@
         Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
 # endif
-        Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
+        Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) == 3 || (pCtx->ss.Sel & X86_SEL_RPL) == 0);
         AssertMsg(   (pCtx->eflags.u32 & X86_EFL_IF)
                   || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
@@ -1401,5 +1404,5 @@
          * Scan code before executing it. Don't bother with user mode or V86 code
          */
-        if (    (pCtx->ss & X86_SEL_RPL) <= 1
+        if (    (pCtx->ss.Sel & X86_SEL_RPL) <= 1
             &&  !pCtx->eflags.Bits.u1VM
             && !PATMIsPatchGCAddr(pVM, pCtx->eip))
@@ -1427,11 +1430,11 @@
         PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
         if (pCtx->eflags.Bits.u1VM)
-            Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
-        else if ((pCtx->ss & X86_SEL_RPL) == 1)
+            Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
+        else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
         {
             bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
-            Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
-        }
-        else if ((pCtx->ss & X86_SEL_RPL) == 3)
+            Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), fCSAMScanned));
+        }
+        else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
             Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
 #endif /* LOG_ENABLED */
@@ -1461,5 +1464,5 @@
         STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
 
-        LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
+        LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL)));
         LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
 
@@ -1542,5 +1545,5 @@
             ||  VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
         {
-            Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
+            Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss.Sel & X86_SEL_RPL) != 1);
 
             STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
Index: trunk/src/VBox/VMM/VMMR3/HWACCM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41906)
@@ -1517,7 +1517,6 @@
 
             /* After a real mode switch to protected mode we must force
-             * CPL to 0. Our real mode emulation had to set it to 3.
-             */
-            pCtx->ssHid.Attr.n.u2Dpl  = 0;
+               CPL to 0. Our real mode emulation had to set it to 3. */
+            pCtx->ss.Attr.n.u2Dpl  = 0;
         }
     }
@@ -2163,5 +2162,5 @@
             {
                 char     szOutput[256];
-                rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
+                rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
                                         szOutput, sizeof(szOutput), &cbCurInstr);
                 if (RT_SUCCESS(rc))
@@ -2305,20 +2304,20 @@
             if (CPUMIsGuestInRealModeEx(pCtx))
             {
-                /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
-                 * The base must also be equal to (sel << 4).
-                 */
-                if (   (   pCtx->cs != (pCtx->csHid.u64Base >> 4)
-                        && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
-                    || (pCtx->csHid.u32Limit != 0xffff)
-                    || (pCtx->dsHid.u32Limit != 0xffff)
-                    || (pCtx->esHid.u32Limit != 0xffff)
-                    || (pCtx->ssHid.u32Limit != 0xffff)
-                    || (pCtx->fsHid.u32Limit != 0xffff)
-                    || (pCtx->gsHid.u32Limit != 0xffff)
-                    || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
-                    || pCtx->es != (pCtx->esHid.u64Base >> 4)
-                    || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
-                    || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
-                    || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
+                /* VT-x will not allow high selector bases in v86 mode; fall
+                   back to the recompiler in that case.
+                   The base must also be equal to (sel << 4). */
+                if (   (   pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
+                        && pCtx->cs.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
+                    || (pCtx->cs.u32Limit != 0xffff)
+                    || (pCtx->ds.u32Limit != 0xffff)
+                    || (pCtx->es.u32Limit != 0xffff)
+                    || (pCtx->ss.u32Limit != 0xffff)
+                    || (pCtx->fs.u32Limit != 0xffff)
+                    || (pCtx->gs.u32Limit != 0xffff)
+                    || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
+                    || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
+                    || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
+                    || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
+                    || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4))
                 {
                     return false;
@@ -2328,16 +2327,16 @@
             {
                 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
-                /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
-                 * from real to protected mode. (all sorts of RPL & DPL assumptions)
-                 */
+                /* Verify the requirements for executing code in protected
+                   mode. VT-x can't handle the CPU state right after a switch
+                   from real to protected mode. (all sorts of RPL & DPL assumptions) */
                 if (    pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
                     &&  enmGuestMode >= PGMMODE_PROTECTED)
                 {
-                    if (   (pCtx->cs & X86_SEL_RPL)
-                        || (pCtx->ds & X86_SEL_RPL)
-                        || (pCtx->es & X86_SEL_RPL)
-                        || (pCtx->fs & X86_SEL_RPL)
-                        || (pCtx->gs & X86_SEL_RPL)
-                        || (pCtx->ss & X86_SEL_RPL))
+                    if (   (pCtx->cs.Sel & X86_SEL_RPL)
+                        || (pCtx->ds.Sel & X86_SEL_RPL)
+                        || (pCtx->es.Sel & X86_SEL_RPL)
+                        || (pCtx->fs.Sel & X86_SEL_RPL)
+                        || (pCtx->gs.Sel & X86_SEL_RPL)
+                        || (pCtx->ss.Sel & X86_SEL_RPL))
                     {
                         return false;
@@ -2346,6 +2345,6 @@
                 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
                 if (    pCtx->gdtr.cbGdt
-                    &&  (   pCtx->tr > pCtx->gdtr.cbGdt
-                         || pCtx->ldtr > pCtx->gdtr.cbGdt))
+                    &&  (   pCtx->tr.Sel > pCtx->gdtr.cbGdt
+                         || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
                 {
                         return false;
@@ -2370,5 +2369,5 @@
 
                 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
-                if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
+                if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
                     return false;
 
@@ -2376,7 +2375,7 @@
                 /* Windows XP; switch to protected mode; all selectors are marked not present in the
                  * hidden registers (possible recompiler bug; see load_seg_vm) */
-                if (pCtx->csHid.Attr.n.u1Present == 0)
+                if (pCtx->cs.Attr.n.u1Present == 0)
                     return false;
-                if (pCtx->ssHid.Attr.n.u1Present == 0)
+                if (pCtx->ss.Attr.n.u1Present == 0)
                     return false;
 
@@ -2385,13 +2384,13 @@
                 /** @todo This check is actually wrong, it doesn't take the direction of the
                  *        stack segment into account. But, it does the job for now. */
-                if (pCtx->rsp >= pCtx->ssHid.u32Limit)
+                if (pCtx->rsp >= pCtx->ss.u32Limit)
                     return false;
 #if 0
-                if (    pCtx->cs >= pCtx->gdtr.cbGdt
-                    ||  pCtx->ss >= pCtx->gdtr.cbGdt
-                    ||  pCtx->ds >= pCtx->gdtr.cbGdt
-                    ||  pCtx->es >= pCtx->gdtr.cbGdt
-                    ||  pCtx->fs >= pCtx->gdtr.cbGdt
-                    ||  pCtx->gs >= pCtx->gdtr.cbGdt)
+                if (    pCtx->cs.Sel >= pCtx->gdtr.cbGdt
+                    ||  pCtx->ss.Sel >= pCtx->gdtr.cbGdt
+                    ||  pCtx->ds.Sel >= pCtx->gdtr.cbGdt
+                    ||  pCtx->es.Sel >= pCtx->gdtr.cbGdt
+                    ||  pCtx->fs.Sel >= pCtx->gdtr.cbGdt
+                    ||  pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
                     return false;
 #endif
Index: trunk/src/VBox/VMM/VMMR3/PATM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41906)
@@ -4088,5 +4088,5 @@
         if (pInstrGCFlat != pInstrGC)
         {
-            Log(("PATMR3InstallPatch: code selector not wide open: %04x:%RRv != %RRv eflags=%08x\n", pCtx->cs, pInstrGCFlat, pInstrGC, pCtx->eflags.u32));
+            Log(("PATMR3InstallPatch: code selector not wide open: %04x:%RRv != %RRv eflags=%08x\n", pCtx->cs.Sel, pInstrGCFlat, pInstrGC, pCtx->eflags.u32));
             return VERR_PATCHING_REFUSED;
         }
@@ -6105,5 +6105,5 @@
 #ifdef DEBUG
         char szBuf[256];
-        DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCurPatchInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
+        DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, pCurPatchInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
                            szBuf, sizeof(szBuf), NULL);
         Log(("DIRTY: %s\n", szBuf));
@@ -6168,5 +6168,5 @@
 #ifdef DEBUG
                 char szBuf[256];
-                DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCurInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
+                DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, pCurInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
                                    szBuf, sizeof(szBuf), NULL);
                 Log(("NEW:   %s\n", szBuf));
@@ -6184,5 +6184,5 @@
 #ifdef DEBUG
                 char szBuf[256];
-                DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCurInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
+                DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, pCurInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
                                    szBuf, sizeof(szBuf), NULL);
                 Log(("NEW:   %s (FAILED)\n", szBuf));
@@ -6221,5 +6221,5 @@
 #ifdef DEBUG
                             char szBuf[256];
-                            DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCurPatchInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
+                            DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, pCurPatchInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
                                                szBuf, sizeof(szBuf), NULL);
                             Log(("FILL:  %s\n", szBuf));
@@ -6233,5 +6233,5 @@
 #ifdef DEBUG
                                 char szBuf[256];
-                                DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCurPatchInstrGC + i,
+                                DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, pCurPatchInstrGC + i,
                                                    DBGF_DISAS_FLAGS_DEFAULT_MODE, szBuf, sizeof(szBuf), NULL);
                                 Log(("FILL:  %s\n", szBuf));
@@ -6425,5 +6425,5 @@
 
         char szBuf[256];
-        DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pEip, DBGF_DISAS_FLAGS_DEFAULT_MODE, szBuf, sizeof(szBuf), NULL);
+        DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, pEip, DBGF_DISAS_FLAGS_DEFAULT_MODE, szBuf, sizeof(szBuf), NULL);
 
         /* Very bad. We crashed in emitted code. Probably stack? */
@@ -6542,5 +6542,5 @@
 
     Log2(("pPatchBlockGC %RRv - pEip %RRv corresponding GC address %RRv\n", PATCHCODE_PTR_GC(&pPatch->patch), pEip, pNewEip));
-    DBGFR3DisasInstrLog(pVCpu, pCtx->cs, pNewEip, "PATCHRET: ");
+    DBGFR3DisasInstrLog(pVCpu, pCtx->cs.Sel, pNewEip, "PATCHRET: ");
     if (pNewEip >= pPatch->patch.pPrivInstrGC && pNewEip < pPatch->patch.pPrivInstrGC + pPatch->patch.cbPatchJump)
     {
Index: trunk/src/VBox/VMM/VMMR3/VMM.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/VMM.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/VMM.cpp	(revision 41906)
@@ -1330,8 +1330,10 @@
     PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
 
-    pCtx->cs                        = uVector << 8;
-    pCtx->csHid.u64Base             = uVector << 12;
-    pCtx->csHid.u32Limit            = 0x0000ffff;
-    pCtx->rip                       = 0;
+    pCtx->cs.Sel        = uVector << 8;
+    pCtx->cs.ValidSel   = uVector << 8;
+    pCtx->cs.fFlags     = CPUMSELREG_FLAGS_VALID;
+    pCtx->cs.u64Base    = uVector << 12;
+    pCtx->cs.u32Limit   = UINT32_C(0x0000ffff);
+    pCtx->rip           = 0;
 
     Log(("vmmR3SendSipi for VCPU %d with vector %x\n", uVector));
Index: trunk/src/VBox/VMM/VMMR3/VMMTests.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/VMMTests.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMR3/VMMTests.cpp	(revision 41906)
@@ -448,19 +448,19 @@
 
 #define SYNC_SEL(pHyperCtx, reg)                                                        \
-        if (pHyperCtx->reg)                                                             \
+        if (pHyperCtx->reg.Sel)                                                         \
         {                                                                               \
             DBGFSELINFO selInfo;                                                        \
-            int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg, &selInfo);       \
+            int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg.Sel, &selInfo);   \
             AssertRC(rc2);                                                              \
                                                                                         \
-            pHyperCtx->reg##Hid.u64Base              = selInfo.GCPtrBase;               \
-            pHyperCtx->reg##Hid.u32Limit             = selInfo.cbLimit;                 \
-            pHyperCtx->reg##Hid.Attr.n.u1Present     = selInfo.u.Raw.Gen.u1Present;     \
-            pHyperCtx->reg##Hid.Attr.n.u1DefBig      = selInfo.u.Raw.Gen.u1DefBig;      \
-            pHyperCtx->reg##Hid.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity; \
-            pHyperCtx->reg##Hid.Attr.n.u4Type        = selInfo.u.Raw.Gen.u4Type;        \
-            pHyperCtx->reg##Hid.Attr.n.u2Dpl         = selInfo.u.Raw.Gen.u2Dpl;         \
-            pHyperCtx->reg##Hid.Attr.n.u1DescType    = selInfo.u.Raw.Gen.u1DescType;    \
-            pHyperCtx->reg##Hid.Attr.n.u1Long        = selInfo.u.Raw.Gen.u1Long;        \
+            pHyperCtx->reg.u64Base              = selInfo.GCPtrBase;                    \
+            pHyperCtx->reg.u32Limit             = selInfo.cbLimit;                      \
+            pHyperCtx->reg.Attr.n.u1Present     = selInfo.u.Raw.Gen.u1Present;          \
+            pHyperCtx->reg.Attr.n.u1DefBig      = selInfo.u.Raw.Gen.u1DefBig;           \
+            pHyperCtx->reg.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity;      \
+            pHyperCtx->reg.Attr.n.u4Type        = selInfo.u.Raw.Gen.u4Type;             \
+            pHyperCtx->reg.Attr.n.u2Dpl         = selInfo.u.Raw.Gen.u2Dpl;              \
+            pHyperCtx->reg.Attr.n.u1DescType    = selInfo.u.Raw.Gen.u1DescType;         \
+            pHyperCtx->reg.Attr.n.u1Long        = selInfo.u.Raw.Gen.u1Long;             \
         }
 
Index: trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/CPUMRC.cpp	(revision 41906)
@@ -95,14 +95,14 @@
 
             pGstCtxCore->eip        = *pEsp++;
-            pGstCtxCore->cs         = (RTSEL)*pEsp++;
+            pGstCtxCore->cs.Sel     = (RTSEL)*pEsp++;
             pGstCtxCore->eflags.u32 = *pEsp++;
             pGstCtxCore->esp        = *pEsp++;
-            pGstCtxCore->ss         = (RTSEL)*pEsp++;
+            pGstCtxCore->ss.Sel     = (RTSEL)*pEsp++;
             if (pGstCtxCore->eflags.Bits.u1VM)
             {
-                pGstCtxCore->es     = (RTSEL)*pEsp++;
-                pGstCtxCore->ds     = (RTSEL)*pEsp++;
-                pGstCtxCore->fs     = (RTSEL)*pEsp++;
-                pGstCtxCore->gs     = (RTSEL)*pEsp++;
+                pGstCtxCore->es.Sel = (RTSEL)*pEsp++;
+                pGstCtxCore->ds.Sel = (RTSEL)*pEsp++;
+                pGstCtxCore->fs.Sel = (RTSEL)*pEsp++;
+                pGstCtxCore->gs.Sel = (RTSEL)*pEsp++;
             }
 
Index: trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm
===================================================================
--- trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm	(revision 41906)
@@ -74,5 +74,5 @@
     mov     ecx, [edx + CPUMCPU.Guest.eip]
     mov     [eax +  0h], ecx
-    mov     ecx, [edx + CPUMCPU.Guest.cs]
+    mov     ecx, [edx + CPUMCPU.Guest.cs.Sel]
     mov     [eax +  4h], ecx
     mov     ecx, [edx + CPUMCPU.Guest.eflags]
@@ -80,5 +80,5 @@
     mov     ecx, [edx + CPUMCPU.Guest.esp]
     mov     [eax + 0ch], ecx
-    mov     ecx, [edx + CPUMCPU.Guest.ss]
+    mov     ecx, [edx + CPUMCPU.Guest.ss.Sel]
     mov     [eax + 10h], ecx
 
@@ -91,7 +91,7 @@
     ; todo: potential trouble loading invalid es,fs,gs,ds because
     ;       of a VMM imposed exception?
-    mov     es,  [edx + CPUMCPU.Guest.es]
-    mov     fs,  [edx + CPUMCPU.Guest.fs]
-    mov     gs,  [edx + CPUMCPU.Guest.gs]
+    mov     es,  [edx + CPUMCPU.Guest.es.Sel]
+    mov     fs,  [edx + CPUMCPU.Guest.fs.Sel]
+    mov     gs,  [edx + CPUMCPU.Guest.gs.Sel]
     mov     esi, [edx + CPUMCPU.Guest.esi]
     mov     edi, [edx + CPUMCPU.Guest.edi]
@@ -100,5 +100,5 @@
     mov     ecx, [edx + CPUMCPU.Guest.ecx]
     mov     eax, [edx + CPUMCPU.Guest.eax]
-    push    dword [edx + CPUMCPU.Guest.ds]
+    push    dword [edx + CPUMCPU.Guest.ds.Sel]
     mov     edx, [edx + CPUMCPU.Guest.edx]
     pop     ds
@@ -108,11 +108,11 @@
 CPUMGCRestoreInt_V86:
     ; iret restores ds, es, fs & gs
-    mov     ecx, [edx + CPUMCPU.Guest.es]
+    mov     ecx, [edx + CPUMCPU.Guest.es.Sel]
     mov     [eax + 14h], ecx
-    mov     ecx, [edx + CPUMCPU.Guest.ds]
+    mov     ecx, [edx + CPUMCPU.Guest.ds.Sel]
     mov     [eax + 18h], ecx
-    mov     ecx, [edx + CPUMCPU.Guest.fs]
+    mov     ecx, [edx + CPUMCPU.Guest.fs.Sel]
     mov     [eax + 1Ch], ecx
-    mov     ecx, [edx + CPUMCPU.Guest.gs]
+    mov     ecx, [edx + CPUMCPU.Guest.gs.Sel]
     mov     [eax + 20h], ecx
     mov     esi, [edx + CPUMCPU.Guest.esi]
@@ -172,11 +172,11 @@
     ;; @todo  load segment registers *before* enabling WP.
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS | CPUM_HANDLER_CTXCORE_IN_EBP
-    mov     gs, [ebp + CPUMCTXCORE.gs]
+    mov     gs, [ebp + CPUMCTXCORE.gs.Sel]
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS | CPUM_HANDLER_CTXCORE_IN_EBP
-    mov     fs, [ebp + CPUMCTXCORE.fs]
+    mov     fs, [ebp + CPUMCTXCORE.fs.Sel]
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES | CPUM_HANDLER_CTXCORE_IN_EBP
-    mov     es, [ebp + CPUMCTXCORE.es]
+    mov     es, [ebp + CPUMCTXCORE.es.Sel]
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS | CPUM_HANDLER_CTXCORE_IN_EBP
-    mov     ds, [ebp + CPUMCTXCORE.ds]
+    mov     ds, [ebp + CPUMCTXCORE.ds.Sel]
 
     mov     eax, [ebp + CPUMCTXCORE.eax]
@@ -202,12 +202,12 @@
 
     ; construct iret stack frame
-    push    dword [ebp + CPUMCTXCORE.gs]
-    push    dword [ebp + CPUMCTXCORE.fs]
-    push    dword [ebp + CPUMCTXCORE.ds]
-    push    dword [ebp + CPUMCTXCORE.es]
-    push    dword [ebp + CPUMCTXCORE.ss]
+    push    dword [ebp + CPUMCTXCORE.gs.Sel]
+    push    dword [ebp + CPUMCTXCORE.fs.Sel]
+    push    dword [ebp + CPUMCTXCORE.ds.Sel]
+    push    dword [ebp + CPUMCTXCORE.es.Sel]
+    push    dword [ebp + CPUMCTXCORE.ss.Sel]
     push    dword [ebp + CPUMCTXCORE.esp]
     push    dword [ebp + CPUMCTXCORE.eflags]
-    push    dword [ebp + CPUMCTXCORE.cs]
+    push    dword [ebp + CPUMCTXCORE.cs.Sel]
     push    dword [ebp + CPUMCTXCORE.eip]
 
@@ -253,8 +253,8 @@
     ; Setup iretd
     ;
-    push    dword [edx + CPUMCPU.Guest.ss]
+    push    dword [edx + CPUMCPU.Guest.ss.Sel]
     push    dword [edx + CPUMCPU.Guest.esp]
     push    dword [edx + CPUMCPU.Guest.eflags]
-    push    dword [edx + CPUMCPU.Guest.cs]
+    push    dword [edx + CPUMCPU.Guest.cs.Sel]
     push    dword [edx + CPUMCPU.Guest.eip]
 
@@ -263,9 +263,9 @@
     ;
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES
-    mov     es,  [edx + CPUMCPU.Guest.es]
+    mov     es,  [edx + CPUMCPU.Guest.es.Sel]
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS
-    mov     fs,  [edx + CPUMCPU.Guest.fs]
+    mov     fs,  [edx + CPUMCPU.Guest.fs.Sel]
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS
-    mov     gs,  [edx + CPUMCPU.Guest.gs]
+    mov     gs,  [edx + CPUMCPU.Guest.gs.Sel]
 
 %ifdef VBOX_WITH_STATISTICS
@@ -302,5 +302,5 @@
     mov     ecx, [edx + CPUMCPU.Guest.ecx]
     mov     eax, [edx + CPUMCPU.Guest.eax]
-    push    dword [edx + CPUMCPU.Guest.ds]
+    push    dword [edx + CPUMCPU.Guest.ds.Sel]
     mov     edx, [edx + CPUMCPU.Guest.edx]
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS
@@ -331,14 +331,14 @@
     ; Setup iretd
     ;
-    push    dword [edx + CPUMCPU.Guest.gs]
-    push    dword [edx + CPUMCPU.Guest.fs]
-    push    dword [edx + CPUMCPU.Guest.ds]
-    push    dword [edx + CPUMCPU.Guest.es]
-
-    push    dword [edx + CPUMCPU.Guest.ss]
+    push    dword [edx + CPUMCPU.Guest.gs.Sel]
+    push    dword [edx + CPUMCPU.Guest.fs.Sel]
+    push    dword [edx + CPUMCPU.Guest.ds.Sel]
+    push    dword [edx + CPUMCPU.Guest.es.Sel]
+
+    push    dword [edx + CPUMCPU.Guest.ss.Sel]
     push    dword [edx + CPUMCPU.Guest.esp]
 
     push    dword [edx + CPUMCPU.Guest.eflags]
-    push    dword [edx + CPUMCPU.Guest.cs]
+    push    dword [edx + CPUMCPU.Guest.cs.Sel]
     push    dword [edx + CPUMCPU.Guest.eip]
 
Index: trunk/src/VBox/VMM/VMMRC/CSAMRC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRC/CSAMRC.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/CSAMRC.cpp	(revision 41906)
@@ -102,5 +102,5 @@
         cpl = 3;
     else
-        cpl = (pRegFrame->ss & X86_SEL_RPL);
+        cpl = (pRegFrame->ss.Sel & X86_SEL_RPL);
 
     Log(("CSAMGCCodePageWriteHandler: code page write at %RGv original address %RGv (cpl=%d)\n", pvFault, (RTGCUINTPTR)pvRange + offRange, cpl));
Index: trunk/src/VBox/VMM/VMMRC/PATMRC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRC/PATMRC.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/PATMRC.cpp	(revision 41906)
@@ -155,5 +155,5 @@
 
     /* Very important check -> otherwise we have a security leak. */
-    AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss & X86_SEL_RPL) == 1, VERR_ACCESS_DENIED);
+    AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss.Sel & X86_SEL_RPL) == 1, VERR_ACCESS_DENIED);
     Assert(PATMIsPatchGCAddr(pVM, pRegFrame->eip));
 
@@ -455,5 +455,5 @@
     int rc;
 
-    AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss & X86_SEL_RPL) == 1, VERR_ACCESS_DENIED);
+    AssertReturn(!pRegFrame->eflags.Bits.u1VM && (pRegFrame->ss.Sel & X86_SEL_RPL) == 1, VERR_ACCESS_DENIED);
 
     /* Int 3 in PATM generated code? (most common case) */
@@ -510,5 +510,5 @@
             }
 
-            DISCPUMODE enmCpuMode = SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pRegFrame->eflags, pRegFrame->cs, 0);
+            DISCPUMODE enmCpuMode = SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pRegFrame->eflags, pRegFrame->cs.Sel, 0);
             if (enmCpuMode != DISCPUMODE_32BIT)
             {
Index: trunk/src/VBox/VMM/VMMRC/SELMRC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRC/SELMRC.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/SELMRC.cpp	(revision 41906)
@@ -140,16 +140,16 @@
 
 #ifdef LOG_ENABLED
-    if (Sel == (pRegFrame->cs & X86_SEL_MASK))
-        Log(("GDT write to selector in CS register %04X\n", pRegFrame->cs));
-    else if (Sel == (pRegFrame->ds & X86_SEL_MASK))
-        Log(("GDT write to selector in DS register %04X\n", pRegFrame->ds));
-    else if (Sel == (pRegFrame->es & X86_SEL_MASK))
-        Log(("GDT write to selector in ES register %04X\n", pRegFrame->es));
-    else if (Sel == (pRegFrame->fs & X86_SEL_MASK))
-        Log(("GDT write to selector in FS register %04X\n", pRegFrame->fs));
-    else if (Sel == (pRegFrame->gs & X86_SEL_MASK))
-        Log(("GDT write to selector in GS register %04X\n", pRegFrame->gs));
-    else if (Sel == (pRegFrame->ss & X86_SEL_MASK))
-        Log(("GDT write to selector in SS register %04X\n", pRegFrame->ss));
+    if (Sel == (pRegFrame->cs.Sel & X86_SEL_MASK))
+        Log(("GDT write to selector in CS register %04X\n", pRegFrame->cs.Sel));
+    else if (Sel == (pRegFrame->ds.Sel & X86_SEL_MASK))
+        Log(("GDT write to selector in DS register %04X\n", pRegFrame->ds.Sel));
+    else if (Sel == (pRegFrame->es.Sel & X86_SEL_MASK))
+        Log(("GDT write to selector in ES register %04X\n", pRegFrame->es.Sel));
+    else if (Sel == (pRegFrame->fs.Sel & X86_SEL_MASK))
+        Log(("GDT write to selector in FS register %04X\n", pRegFrame->fs.Sel));
+    else if (Sel == (pRegFrame->gs.Sel & X86_SEL_MASK))
+        Log(("GDT write to selector in GS register %04X\n", pRegFrame->gs.Sel));
+    else if (Sel == (pRegFrame->ss.Sel & X86_SEL_MASK))
+        Log(("GDT write to selector in SS register %04X\n", pRegFrame->ss.Sel));
 #endif
     return VINF_SUCCESS;
Index: trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp	(revision 41906)
@@ -257,6 +257,6 @@
     AssertMsg(     rc != VINF_SUCCESS
               ||   (   pRegFrame->eflags.Bits.u1IF
-                    && ( pRegFrame->eflags.Bits.u2IOPL < (unsigned)(pRegFrame->ss & X86_SEL_RPL) || pRegFrame->eflags.Bits.u1VM))
-              , ("rc=%Rrc\neflags=%RX32 ss=%RTsel IOPL=%d\n", rc, pRegFrame->eflags.u32, pRegFrame->ss, pRegFrame->eflags.Bits.u2IOPL));
+                    && ( pRegFrame->eflags.Bits.u2IOPL < (unsigned)(pRegFrame->ss.Sel & X86_SEL_RPL) || pRegFrame->eflags.Bits.u1VM))
+              , ("rc=%Rrc\neflags=%RX32 ss=%RTsel IOPL=%d\n", rc, pRegFrame->eflags.u32, pRegFrame->ss.Sel, pRegFrame->eflags.Bits.u2IOPL));
     PGMRZDynMapReleaseAutoSet(pVCpu);
     return rc;
@@ -281,5 +281,5 @@
     PVMCPU      pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
 
-    LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
+    LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
 
     /*
@@ -302,5 +302,5 @@
 
     rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-    Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
+    Log6(("TRPMGC01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
     return rc;
 }
@@ -328,5 +328,5 @@
     PVMCPU      pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
 
-    LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs, pRegFrame->eip, uDr6));
+    LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
 
     /*
@@ -346,5 +346,5 @@
     AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_1);
 
-    Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs, pRegFrame->eip, uDr6));
+    Log6(("TRPMGCHyper01: %Rrc (%04x:%08x %RTreg)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip, uDr6));
     return rc;
 }
@@ -365,6 +365,6 @@
 DECLASM(int) TRPMGCTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
-    RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
+    LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
+    RTLogComPrintf("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
     NOREF(pTrpmCpu);
     return VERR_TRPM_DONT_PANIC;
@@ -389,6 +389,6 @@
 DECLASM(int) TRPMGCHyperTrap02Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
-    RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs, pRegFrame->eip);
+    LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
+    RTLogComPrintf("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip);
     NOREF(pTrpmCpu);
     return VERR_TRPM_DONT_PANIC;
@@ -409,5 +409,5 @@
 DECLASM(int) TRPMGCTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGC03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
+    LogFlow(("TRPMGC03: %04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
     PVM     pVM   = TRPMCPU_2_VM(pTrpmCpu);
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
@@ -418,5 +418,5 @@
      * PATM is using INT3s, let them have a go first.
      */
-    if (    (pRegFrame->ss & X86_SEL_RPL) == 1
+    if (    (pRegFrame->ss.Sel & X86_SEL_RPL) == 1
         &&  !pRegFrame->eflags.Bits.u1VM)
     {
@@ -428,5 +428,5 @@
         {
             rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-            Log6(("TRPMGC03: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
+            Log6(("TRPMGC03: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
             return rc;
         }
@@ -436,5 +436,5 @@
     /* anything we should do with this? Schedule it in GC? */
     rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-    Log6(("TRPMGC03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGC03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
     return rc;
 }
@@ -457,5 +457,5 @@
 DECLASM(int) TRPMGCHyperTrap03Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGCHyper03: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
+    LogFlow(("TRPMGCHyper03: %04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
     PVM     pVM   = TRPMCPU_2_VM(pTrpmCpu);
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
@@ -467,5 +467,5 @@
     AssertStmt(rc != VINF_EM_RAW_GUEST_TRAP, rc = VERR_TRPM_IPE_2);
 
-    Log6(("TRPMGCHyper03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGCHyper03: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
     return rc;
 }
@@ -485,5 +485,5 @@
 DECLASM(int) TRPMGCTrap06Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGC06: %04x:%08x efl=%x\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->eflags.u32));
+    LogFlow(("TRPMGC06: %04x:%08x efl=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->eflags.u32));
     PVM     pVM   = TRPMCPU_2_VM(pTrpmCpu);
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
@@ -497,11 +497,11 @@
          */
         RTGCPTR PC;
-        rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
+        rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
                                           pRegFrame->rip, &PC);
         if (RT_FAILURE(rc))
         {
-            Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
+            Log(("TRPMGCTrap06Handler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
             rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_GUEST_TRAP, pRegFrame);
-            Log6(("TRPMGC06: %Rrc (%04x:%08x) (SELM)\n", rc, pRegFrame->cs, pRegFrame->eip));
+            Log6(("TRPMGC06: %Rrc (%04x:%08x) (SELM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
             return rc;
         }
@@ -513,5 +513,5 @@
         {
             rc = trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
-            Log6(("TRPMGC06: %Rrc (%04x:%08x) (EM)\n", rc, pRegFrame->cs, pRegFrame->eip));
+            Log6(("TRPMGC06: %Rrc (%04x:%08x) (EM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
             return rc;
         }
@@ -535,5 +535,5 @@
             {
                 rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-                Log6(("TRPMGC06: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs, pRegFrame->eip));
+                Log6(("TRPMGC06: %Rrc (%04x:%08x) (PATM)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
                 return rc;
             }
@@ -576,5 +576,5 @@
 
     rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-    Log6(("TRPMGC06: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGC06: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
     return rc;
 }
@@ -596,5 +596,5 @@
 DECLASM(int) TRPMGCTrap07Handler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGC07: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
+    LogFlow(("TRPMGC07: %04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
     PVM     pVM   = TRPMCPU_2_VM(pTrpmCpu);
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
@@ -603,5 +603,5 @@
     int rc = CPUMHandleLazyFPU(pVCpu);
     rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-    Log6(("TRPMGC07: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGC07: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
     return rc;
 }
@@ -621,5 +621,5 @@
 DECLASM(int) TRPMGCTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("TRPMGC0b: %04x:%08x\n", pRegFrame->cs, pRegFrame->eip));
+    LogFlow(("TRPMGC0b: %04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip));
     PVM     pVM   = TRPMCPU_2_VM(pTrpmCpu);
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
@@ -632,5 +632,5 @@
      */
     RTGCPTR GCPtr;
-    if (   SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
+    if (   SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
                                         (RTGCPTR)pRegFrame->eip, &GCPtr)
         == VINF_SUCCESS)
@@ -697,5 +697,5 @@
              */
             pTrpmCpu->uActiveVector = UINT32_MAX;
-            Log6(("TRPMGC0b: %Rrc (%04x:%08x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs, pRegFrame->eip));
+            Log6(("TRPMGC0b: %Rrc (%04x:%08x) (CG)\n", VINF_EM_RAW_RING_SWITCH, pRegFrame->cs.Sel, pRegFrame->eip));
             PGMRZDynMapReleaseAutoSet(pVCpu);
             return VINF_EM_RAW_RING_SWITCH;
@@ -706,5 +706,5 @@
      * Pass trap 0b as is to the recompiler in all other cases.
      */
-    Log6(("TRPMGC0b: %Rrc (%04x:%08x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGC0b: %Rrc (%04x:%08x)\n", VINF_EM_RAW_GUEST_TRAP, pRegFrame->cs.Sel, pRegFrame->eip));
     PGMRZDynMapReleaseAutoSet(pVCpu);
     return VINF_EM_RAW_GUEST_TRAP;
@@ -890,5 +890,5 @@
         {
             uint32_t efl = CPUMRawGetEFlags(pVCpu, pRegFrame);
-            if (X86_EFL_GET_IOPL(efl) >= (unsigned)(pRegFrame->ss & X86_SEL_RPL))
+            if (X86_EFL_GET_IOPL(efl) >= (unsigned)(pRegFrame->ss.Sel & X86_SEL_RPL))
             {
                 LogFlow(("trpmGCTrap0dHandlerRing3: CLI/STI -> REM\n"));
@@ -945,5 +945,5 @@
 static int trpmGCTrap0dHandler(PVM pVM, PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame)
 {
-    LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv\n", pRegFrame->ss, pRegFrame->eip, pTrpmCpu->uActiveErrorCode));
+    LogFlow(("trpmGCTrap0dHandler: cs:eip=%RTsel:%08RX32 uErr=%RGv\n", pRegFrame->cs.Sel, pRegFrame->eip, pTrpmCpu->uActiveErrorCode));
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
 
@@ -954,10 +954,10 @@
     RTGCPTR PC;
     uint32_t cBits;
-    int rc = SELMValidateAndConvertCSAddrGCTrap(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
+    int rc = SELMValidateAndConvertCSAddrGCTrap(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel,
                                                 pRegFrame->rip, &PC, &cBits);
     if (RT_FAILURE(rc))
     {
         Log(("trpmGCTrap0dHandler: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Rrc !!\n",
-             pRegFrame->cs, pRegFrame->eip, pRegFrame->ss & X86_SEL_RPL, rc));
+             pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->ss.Sel & X86_SEL_RPL, rc));
         STAM_PROFILE_STOP(&pVM->trpm.s.StatTrap0dDisasm, a);
         return trpmGCExitTrap(pVM, pVCpu, VINF_EM_RAW_EMULATE_INSTR, pRegFrame);
@@ -1004,5 +1004,5 @@
      * Deal with Ring-0 (privileged instructions)
      */
-    if (    (pRegFrame->ss & X86_SEL_RPL) <= 1
+    if (    (pRegFrame->ss.Sel & X86_SEL_RPL) <= 1
         &&  !pRegFrame->eflags.Bits.u1VM)
         return trpmGCTrap0dHandlerRing0(pVM, pVCpu, pRegFrame, &Cpu, PC);
@@ -1024,5 +1024,5 @@
     X86EFLAGS eflags;
     eflags.u32 = CPUMRawGetEFlags(pVCpu, pRegFrame); /* Get the correct value. */
-    Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
+    Log3(("TRPM #GP V86: cs:eip=%04x:%08x IOPL=%d efl=%08x\n", pRegFrame->cs.Sel, pRegFrame->eip, eflags.Bits.u2IOPL, eflags.u));
     if (eflags.Bits.u2IOPL != 3)
     {
@@ -1053,5 +1053,5 @@
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
 
-    LogFlow(("TRPMGC0d: %04x:%08x err=%x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode));
+    LogFlow(("TRPMGC0d: %04x:%08x err=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode));
 
     PGMRZDynMapStartAutoSet(pVCpu);
@@ -1088,5 +1088,5 @@
             break;
         }
-    Log6(("TRPMGC0d: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGC0d: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
     return rc;
 }
@@ -1112,5 +1112,5 @@
     PVMCPU  pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu);
 
-    LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x\n", pRegFrame->cs, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2));
+    LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2));
 
     /*
@@ -1164,5 +1164,5 @@
     }
     rc = trpmGCExitTrap(pVM, pVCpu, rc, pRegFrame);
-    Log6(("TRPMGC0e: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs, pRegFrame->eip));
+    Log6(("TRPMGC0e: %Rrc (%04x:%08x)\n", rc, pRegFrame->cs.Sel, pRegFrame->eip));
     return rc;
 }
@@ -1303,10 +1303,10 @@
         {
             case TRPM_TRAP_IN_MOV_GS:
-                pRegFrame->eax = 0;
-                pRegFrame->gs = 0; /* prevent recursive trouble. */
+                pRegFrame->eax    = 0;
+                pRegFrame->gs.Sel = 0; /* prevent recursive trouble. */
                 break;
             case TRPM_TRAP_IN_MOV_FS:
-                pRegFrame->eax = 0;
-                pRegFrame->fs = 0; /* prevent recursive trouble. */
+                pRegFrame->eax    = 0;
+                pRegFrame->fs.Sel = 0; /* prevent recursive trouble. */
                 return VINF_SUCCESS;
 
@@ -1349,9 +1349,9 @@
              */
             case TRPM_TRAP_IN_IRET:
-                CtxCore.eip = *pEsp++;
-                CtxCore.cs = (RTSEL)*pEsp++;
+                CtxCore.eip        = *pEsp++;
+                CtxCore.cs.Sel     = (RTSEL)*pEsp++;
                 CtxCore.eflags.u32 = *pEsp++;
-                CtxCore.esp = *pEsp++;
-                CtxCore.ss = (RTSEL)*pEsp++;
+                CtxCore.esp        = *pEsp++;
+                CtxCore.ss.Sel     = (RTSEL)*pEsp++;
                 rc = VINF_EM_RAW_IRET_TRAP;
                 break;
@@ -1361,13 +1361,13 @@
              */
             case TRPM_TRAP_IN_IRET | TRPM_TRAP_IN_V86:
-                CtxCore.eip = *pEsp++;
-                CtxCore.cs = (RTSEL)*pEsp++;
+                CtxCore.eip        = *pEsp++;
+                CtxCore.cs.Sel     = (RTSEL)*pEsp++;
                 CtxCore.eflags.u32 = *pEsp++;
-                CtxCore.esp = *pEsp++;
-                CtxCore.ss = (RTSEL)*pEsp++;
-                CtxCore.es = (RTSEL)*pEsp++;
-                CtxCore.ds = (RTSEL)*pEsp++;
-                CtxCore.fs = (RTSEL)*pEsp++;
-                CtxCore.gs = (RTSEL)*pEsp++;
+                CtxCore.esp        = *pEsp++;
+                CtxCore.ss.Sel     = (RTSEL)*pEsp++;
+                CtxCore.es.Sel     = (RTSEL)*pEsp++;
+                CtxCore.ds.Sel     = (RTSEL)*pEsp++;
+                CtxCore.fs.Sel     = (RTSEL)*pEsp++;
+                CtxCore.gs.Sel     = (RTSEL)*pEsp++;
                 rc = VINF_EM_RAW_IRET_TRAP;
                 break;
Index: trunk/src/VBox/VMM/VMMRC/TRPMRCHandlersA.asm
===================================================================
--- trunk/src/VBox/VMM/VMMRC/TRPMRCHandlersA.asm	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/TRPMRCHandlersA.asm	(revision 41906)
@@ -265,8 +265,8 @@
     mov     [esp + CPUMCTXCORE.esp], eax
     mov     eax, [esp + 18h + ESPOFF]           ; ss
-    mov     dword [esp + CPUMCTXCORE.ss], eax
+    mov     dword [esp + CPUMCTXCORE.ss.Sel], eax
 
     mov     eax, [esp + 0ch + ESPOFF]           ; cs
-    mov     dword [esp + CPUMCTXCORE.cs], eax
+    mov     dword [esp + CPUMCTXCORE.cs.Sel], eax
     mov     eax, [esp + 08h + ESPOFF]           ; eip
     mov     [esp + CPUMCTXCORE.eip], eax
@@ -288,11 +288,11 @@
 
     mov     eax, es
-    mov     dword [esp + CPUMCTXCORE.es], eax
+    mov     dword [esp + CPUMCTXCORE.es.Sel], eax
     mov     eax, ds
-    mov     dword [esp + CPUMCTXCORE.ds], eax
+    mov     dword [esp + CPUMCTXCORE.ds.Sel], eax
     mov     eax, fs
-    mov     dword [esp + CPUMCTXCORE.fs], eax
+    mov     dword [esp + CPUMCTXCORE.fs.Sel], eax
     mov     eax, gs
-    mov     dword [esp + CPUMCTXCORE.gs], eax
+    mov     dword [esp + CPUMCTXCORE.gs.Sel], eax
 
     test    dword [esp + CPUMCTXCORE.eflags], X86_EFL_VM
@@ -303,14 +303,14 @@
     ;
     mov     eax, dword [esp + ESPOFF + 1Ch]
-    mov     dword [esp + CPUMCTXCORE.es], eax
+    mov     dword [esp + CPUMCTXCORE.es.Sel], eax
 
     mov     eax, dword [esp + ESPOFF + 20h]
-    mov     dword [esp + CPUMCTXCORE.ds], eax
+    mov     dword [esp + CPUMCTXCORE.ds.Sel], eax
 
     mov     eax, dword [esp + ESPOFF + 24h]
-    mov     dword [esp + CPUMCTXCORE.fs], eax
+    mov     dword [esp + CPUMCTXCORE.fs.Sel], eax
 
     mov     eax, dword [esp + ESPOFF + 28h]
-    mov     dword [esp + CPUMCTXCORE.gs], eax
+    mov     dword [esp + CPUMCTXCORE.gs.Sel], eax
 
 gt_SkipV86Entry:
@@ -467,24 +467,24 @@
     mov     eax, [esp + CPUMCTXCORE.esp]
     mov     [esp + 14h + ESPOFF], eax           ; esp
-    mov     eax, dword [esp + CPUMCTXCORE.ss]
+    mov     eax, dword [esp + CPUMCTXCORE.ss.Sel]
     mov     [esp + 18h + ESPOFF], eax           ; ss
 
-    mov     eax, dword [esp + CPUMCTXCORE.gs]
+    mov     eax, dword [esp + CPUMCTXCORE.gs.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_GS
     mov     gs, eax
 
-    mov     eax, dword [esp + CPUMCTXCORE.fs]
+    mov     eax, dword [esp + CPUMCTXCORE.fs.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_FS
     mov     fs, eax
 
-    mov     eax, dword [esp + CPUMCTXCORE.es]
+    mov     eax, dword [esp + CPUMCTXCORE.es.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_ES
     mov     es, eax
 
-    mov     eax, dword [esp + CPUMCTXCORE.ds]
+    mov     eax, dword [esp + CPUMCTXCORE.ds.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_DS
     mov     ds, eax
 
-    mov     eax, dword [esp + CPUMCTXCORE.cs]
+    mov     eax, dword [esp + CPUMCTXCORE.cs.Sel]
     mov     [esp + 0ch + ESPOFF], eax           ; cs
     mov     eax, [esp + CPUMCTXCORE.eflags]
@@ -512,19 +512,19 @@
     mov     eax, [esp + CPUMCTXCORE.esp]
     mov     [esp + 14h + ESPOFF], eax           ; esp
-    mov     eax, dword [esp + CPUMCTXCORE.ss]
+    mov     eax, dword [esp + CPUMCTXCORE.ss.Sel]
     mov     [esp + 18h + ESPOFF], eax           ; ss
 
-    mov     eax, dword [esp + CPUMCTXCORE.es]
+    mov     eax, dword [esp + CPUMCTXCORE.es.Sel]
     mov     [esp + 1ch + ESPOFF], eax           ; es
-    mov     eax, dword [esp + CPUMCTXCORE.ds]
+    mov     eax, dword [esp + CPUMCTXCORE.ds.Sel]
     mov     [esp + 20h + ESPOFF], eax           ; ds
-    mov     eax, dword [esp + CPUMCTXCORE.fs]
+    mov     eax, dword [esp + CPUMCTXCORE.fs.Sel]
     mov     [esp + 24h + ESPOFF], eax           ; fs
-    mov     eax, dword [esp + CPUMCTXCORE.gs]
+    mov     eax, dword [esp + CPUMCTXCORE.gs.Sel]
     mov     [esp + 28h + ESPOFF], eax           ; gs
 
     mov     eax, [esp + CPUMCTXCORE.eip]
     mov     [esp + 08h + ESPOFF], eax           ; eip
-    mov     eax, dword [esp + CPUMCTXCORE.cs]
+    mov     eax, dword [esp + CPUMCTXCORE.cs.Sel]
     mov     [esp + 0ch + ESPOFF], eax           ; cs
     mov     eax, [esp + CPUMCTXCORE.eflags]
@@ -549,5 +549,5 @@
     lea     ebx, [esp + 14h + ESPOFF]   ; calc esp at trap
     mov     [esp + CPUMCTXCORE.esp], ebx; update esp in register frame
-    mov     [esp + CPUMCTXCORE.ss], ss  ; update ss in register frame
+    mov     [esp + CPUMCTXCORE.ss.Sel], ss ; update ss in register frame
 
     ; tell cpum about the context core.
@@ -656,15 +656,15 @@
     mov     edi, [esp + CPUMCTXCORE.edi]
 
-    mov     eax, dword [esp + CPUMCTXCORE.gs]
+    mov     eax, dword [esp + CPUMCTXCORE.gs.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_GS | TRPM_TRAP_IN_HYPER
     mov     gs, eax
 
-    mov     eax, dword [esp + CPUMCTXCORE.fs]
+    mov     eax, dword [esp + CPUMCTXCORE.fs.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_FS | TRPM_TRAP_IN_HYPER
     mov     fs, eax
 
-    mov     eax, dword [esp + CPUMCTXCORE.es]
+    mov     eax, dword [esp + CPUMCTXCORE.es.Sel]
     mov     es, eax
-    mov     eax, dword [esp + CPUMCTXCORE.ds]
+    mov     eax, dword [esp + CPUMCTXCORE.ds.Sel]
     mov     ds, eax
 
@@ -673,5 +673,5 @@
     mov     eax, [esp + CPUMCTXCORE.eip]
     mov     [esp + 08h + ESPOFF], eax           ; eip
-    mov     eax, dword [esp + CPUMCTXCORE.cs]
+    mov     eax, dword [esp + CPUMCTXCORE.cs.Sel]
     mov     [esp + 0ch + ESPOFF], eax           ; cs
     mov     eax, [esp + CPUMCTXCORE.eflags]
@@ -769,5 +769,5 @@
     mov     [esp + CPUMCTXCORE.eip], eax
     mov     eax, dword [esp + 08h + ESPOFF]     ; cs
-    mov     [esp + CPUMCTXCORE.cs], eax
+    mov     [esp + CPUMCTXCORE.cs.Sel], eax
     mov     eax, [esp + 0ch + ESPOFF]           ; eflags
     mov     [esp + CPUMCTXCORE.eflags], eax
@@ -776,5 +776,5 @@
     mov     [esp + CPUMCTXCORE.esp], eax
     mov     eax, dword [esp + 14h + ESPOFF]     ; ss
-    mov     [esp + CPUMCTXCORE.ss], eax
+    mov     [esp + CPUMCTXCORE.ss.Sel], eax
 
 %if GC_ARCH_BITS == 64
@@ -792,11 +792,11 @@
 
     mov     eax, es
-    mov     dword [esp + CPUMCTXCORE.es], eax
+    mov     dword [esp + CPUMCTXCORE.es.Sel], eax
     mov     eax, ds
-    mov     dword [esp + CPUMCTXCORE.ds], eax
+    mov     dword [esp + CPUMCTXCORE.ds.Sel], eax
     mov     eax, fs
-    mov     dword [esp + CPUMCTXCORE.fs], eax
+    mov     dword [esp + CPUMCTXCORE.fs.Sel], eax
     mov     eax, gs
-    mov     dword [esp + CPUMCTXCORE.gs], eax
+    mov     dword [esp + CPUMCTXCORE.gs.Sel], eax
 
     test    dword [esp + CPUMCTXCORE.eflags], X86_EFL_VM
@@ -807,14 +807,14 @@
     ;
     mov     eax, dword [esp + ESPOFF + 18h]
-    mov     dword [esp + CPUMCTXCORE.es], eax
+    mov     dword [esp + CPUMCTXCORE.es.Sel], eax
 
     mov     eax, dword [esp + ESPOFF + 1Ch]
-    mov     dword [esp + CPUMCTXCORE.ds], eax
+    mov     dword [esp + CPUMCTXCORE.ds.Sel], eax
 
     mov     eax, dword [esp + ESPOFF + 20h]
-    mov     dword [esp + CPUMCTXCORE.fs], eax
+    mov     dword [esp + CPUMCTXCORE.fs.Sel], eax
 
     mov     eax, dword [esp + ESPOFF + 24h]
-    mov     dword [esp + CPUMCTXCORE.gs], eax
+    mov     dword [esp + CPUMCTXCORE.gs.Sel], eax
 
 ti_SkipV86Entry:
@@ -925,5 +925,5 @@
     lea     eax, [esp + 14h + ESPOFF]      ; calc esp at trap
     mov     [esp + CPUMCTXCORE.esp], eax   ; update esp in register frame
-    mov     [esp + CPUMCTXCORE.ss], ss     ; update ss in register frame
+    mov     [esp + CPUMCTXCORE.ss.Sel], ss ; update ss in register frame
 
 %ifdef DEBUG_STUFF_INT
@@ -964,15 +964,15 @@
     jnz     short ti_SkipSelRegs
 
-    mov     eax, [esp + CPUMCTXCORE.gs]
+    mov     eax, [esp + CPUMCTXCORE.gs.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_GS | TRPM_TRAP_IN_HYPER
     mov     gs, eax
 
-    mov     eax, [esp + CPUMCTXCORE.fs]
+    mov     eax, [esp + CPUMCTXCORE.fs.Sel]
     TRPM_NP_GP_HANDLER NAME(trpmGCTrapInGeneric), TRPM_TRAP_IN_MOV_FS | TRPM_TRAP_IN_HYPER
     mov     fs, eax
 
-    mov     eax, [esp + CPUMCTXCORE.es]
+    mov     eax, [esp + CPUMCTXCORE.es.Sel]
     mov     es, eax
-    mov     eax, [esp + CPUMCTXCORE.ds]
+    mov     eax, [esp + CPUMCTXCORE.ds.Sel]
     mov     ds, eax
 
@@ -1099,15 +1099,15 @@
 
     movzx   eax, word [ecx + VBOXTSS.cs]
-    mov     dword [esp + CPUMCTXCORE.cs], eax
+    mov     dword [esp + CPUMCTXCORE.cs.Sel], eax
     movzx   eax, word [ecx + VBOXTSS.ds]
-    mov     dword [esp + CPUMCTXCORE.ds], eax
+    mov     dword [esp + CPUMCTXCORE.ds.Sel], eax
     movzx   eax, word [ecx + VBOXTSS.es]
-    mov     dword [esp + CPUMCTXCORE.es], eax
+    mov     dword [esp + CPUMCTXCORE.es.Sel], eax
     movzx   eax, word [ecx + VBOXTSS.fs]
-    mov     dword [esp + CPUMCTXCORE.fs], eax
+    mov     dword [esp + CPUMCTXCORE.fs.Sel], eax
     movzx   eax, word [ecx + VBOXTSS.gs]
-    mov     dword [esp + CPUMCTXCORE.gs], eax
+    mov     dword [esp + CPUMCTXCORE.gs.Sel], eax
     movzx   eax, word [ecx + VBOXTSS.ss]
-    mov     [esp + CPUMCTXCORE.ss], eax
+    mov     [esp + CPUMCTXCORE.ss.Sel], eax
     mov     eax, [ecx + VBOXTSS.esp]
     mov     [esp + CPUMCTXCORE.esp], eax
@@ -1260,5 +1260,5 @@
 tddrf_regs:
     COM_S_PRINT ' ***',10,13,'cs:eip='
-    movzx   ecx, word [eax + CPUMCTXCORE.cs]
+    movzx   ecx, word [eax + CPUMCTXCORE.cs.Sel]
     COM_S_DWORD_REG ecx
     COM_S_CHAR ':'
@@ -1267,5 +1267,5 @@
 
     COM_S_PRINT '    ss:esp='
-    movzx   ecx, word [eax + CPUMCTXCORE.ss]
+    movzx   ecx, word [eax + CPUMCTXCORE.ss.Sel]
     COM_S_DWORD_REG ecx
     COM_S_CHAR ':'
@@ -1323,17 +1323,17 @@
 
     COM_S_PRINT 10,13,' ds='
-    movzx   ecx, word [eax + CPUMCTXCORE.ds]
+    movzx   ecx, word [eax + CPUMCTXCORE.ds.Sel]
     COM_S_DWORD_REG ecx
 
     COM_S_PRINT '   es='
-    movzx   ecx, word [eax + CPUMCTXCORE.es]
+    movzx   ecx, word [eax + CPUMCTXCORE.es.Sel]
     COM_S_DWORD_REG ecx
 
     COM_S_PRINT '   fs='
-    movzx   ecx, word [eax + CPUMCTXCORE.fs]
+    movzx   ecx, word [eax + CPUMCTXCORE.fs.Sel]
     COM_S_DWORD_REG ecx
 
     COM_S_PRINT '   gs='
-    movzx   ecx, word [eax + CPUMCTXCORE.gs]
+    movzx   ecx, word [eax + CPUMCTXCORE.gs.Sel]
     COM_S_DWORD_REG ecx
 
Index: trunk/src/VBox/VMM/VMMRC/VMMRC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRC/VMMRC.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/VMMRC.cpp	(revision 41906)
@@ -371,5 +371,5 @@
 {
     int rc = vmmGCTestTmpPFHandler(pVM, pRegFrame);
-    pRegFrame->fs = 0x30;
+    pRegFrame->fs.Sel = 0x30;
     return rc;
 }
Index: trunk/src/VBox/VMM/VMMRC/VMMRC.mac
===================================================================
--- trunk/src/VBox/VMM/VMMRC/VMMRC.mac	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRC/VMMRC.mac	(revision 41906)
@@ -39,5 +39,5 @@
    [section .VMMR0.%1 progbits alloc noexec nowrite align=1 ]
   %else
-   [section .VMMR0.%1 align=1 ]
+   [section .VMMR0.%1 ]
   %endif
  %endmacro
Index: trunk/src/VBox/VMM/VMMRZ/DBGFRZ.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMRZ/DBGFRZ.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/VMMRZ/DBGFRZ.cpp	(revision 41906)
@@ -46,5 +46,5 @@
 {
 #ifdef IN_RC
-    const bool fInHyper = !(pRegFrame->ss & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
+    const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
 #else
     const bool fInHyper = false;
@@ -66,5 +66,5 @@
                 pVCpu->dbgf.s.fSingleSteppingRaw = false;
                 LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
-                         pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs, pRegFrame->rip));
+                         pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
 
                 return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
@@ -81,5 +81,5 @@
     {
         pVCpu->dbgf.s.fSingleSteppingRaw = false;
-        LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs, pRegFrame->rip));
+        LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
         return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
     }
@@ -91,8 +91,8 @@
      */
     AssertMsg(uDr6 & X86_DR6_BS, ("hey! we're not doing guest BPs yet! dr6=%RTreg %04x:%RGv\n",
-                                  uDr6, pRegFrame->cs, pRegFrame->rip));
+                                  uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
 #endif
 
-    LogFlow(("DBGFRZTrap01Handler: guest debug event %RTreg at %04x:%RGv!\n", uDr6, pRegFrame->cs, pRegFrame->rip));
+    LogFlow(("DBGFRZTrap01Handler: guest debug event %RTreg at %04x:%RGv!\n", uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
     return fInHyper ? VERR_DBGF_HYPER_DB_XCPT : VINF_EM_RAW_GUEST_TRAP;
 }
@@ -113,5 +113,5 @@
 {
 #ifdef IN_RC
-    const bool fInHyper = !(pRegFrame->ss & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
+    const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
 #else
     const bool fInHyper = false;
@@ -125,5 +125,5 @@
     {
         RTGCPTR pPc;
-        int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid,
+        int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
 #ifdef IN_RC
                                               pRegFrame->eip - 1,
@@ -143,5 +143,5 @@
 
                 LogFlow(("DBGFRZTrap03Handler: hit breakpoint %d at %RGv (%04x:%RGv) cHits=0x%RX64\n",
-                         pVM->dbgf.s.aBreakpoints[iBp].iBp, pPc, pRegFrame->cs, pRegFrame->rip,
+                         pVM->dbgf.s.aBreakpoints[iBp].iBp, pPc, pRegFrame->cs.Sel, pRegFrame->rip,
                          pVM->dbgf.s.aBreakpoints[iBp].cHits));
                 return fInHyper
Index: trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac
===================================================================
--- trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac	(revision 41905)
+++ trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac	(revision 41906)
@@ -544,5 +544,5 @@
     ; Setup stack.
     DEBUG_CHAR('3')
-    mov     ax, [edx + CPUMCPU.Hyper.ss]
+    mov     ax, [edx + CPUMCPU.Hyper.ss.Sel]
     mov     ss, ax
     mov     esp, [edx + CPUMCPU.Hyper.esp]
@@ -553,9 +553,9 @@
     and     dword [0ffffffffh], ~0200h      ; clear busy flag (2nd type2 bit)
     DEBUG_CHAR('5')
-    ltr     word [edx + CPUMCPU.Hyper.tr]
+    ltr     word [edx + CPUMCPU.Hyper.tr.Sel]
     DEBUG_CHAR('6')
 
     ; Activate the ldt (now we can safely crash).
-    lldt    [edx + CPUMCPU.Hyper.ldtr]
+    lldt    [edx + CPUMCPU.Hyper.ldtr.Sel]
     DEBUG_CHAR('7')
 
@@ -750,16 +750,16 @@
     mov     [edx + CPUMCPU.Guest.esp], eax
     ; selectors
-    mov     eax, [esp + 4 + CPUMCTXCORE.ss]
-    mov     [edx + CPUMCPU.Guest.ss], eax
-    mov     eax, [esp + 4 + CPUMCTXCORE.gs]
-    mov     [edx + CPUMCPU.Guest.gs], eax
-    mov     eax, [esp + 4 + CPUMCTXCORE.fs]
-    mov     [edx + CPUMCPU.Guest.fs], eax
-    mov     eax, [esp + 4 + CPUMCTXCORE.es]
-    mov     [edx + CPUMCPU.Guest.es], eax
-    mov     eax, [esp + 4 + CPUMCTXCORE.ds]
-    mov     [edx + CPUMCPU.Guest.ds], eax
-    mov     eax, [esp + 4 + CPUMCTXCORE.cs]
-    mov     [edx + CPUMCPU.Guest.cs], eax
+    mov     eax, [esp + 4 + CPUMCTXCORE.ss.Sel]
+    mov     [edx + CPUMCPU.Guest.ss.Sel], eax
+    mov     eax, [esp + 4 + CPUMCTXCORE.gs.Sel]
+    mov     [edx + CPUMCPU.Guest.gs.Sel], eax
+    mov     eax, [esp + 4 + CPUMCTXCORE.fs.Sel]
+    mov     [edx + CPUMCPU.Guest.fs.Sel], eax
+    mov     eax, [esp + 4 + CPUMCTXCORE.es.Sel]
+    mov     [edx + CPUMCPU.Guest.es.Sel], eax
+    mov     eax, [esp + 4 + CPUMCTXCORE.ds.Sel]
+    mov     [edx + CPUMCPU.Guest.ds.Sel], eax
+    mov     eax, [esp + 4 + CPUMCTXCORE.cs.Sel]
+    mov     [edx + CPUMCPU.Guest.cs.Sel], eax
     ; flags
     mov     eax, [esp + 4 + CPUMCTXCORE.eflags]
@@ -833,16 +833,16 @@
     mov     [edx + CPUMCPU.Hyper.esp], eax
     ; selectors
-    mov     eax, [ecx + CPUMCTXCORE.ss]
-    mov     [edx + CPUMCPU.Hyper.ss], eax
-    mov     eax, [ecx + CPUMCTXCORE.gs]
-    mov     [edx + CPUMCPU.Hyper.gs], eax
-    mov     eax, [ecx + CPUMCTXCORE.fs]
-    mov     [edx + CPUMCPU.Hyper.fs], eax
-    mov     eax, [ecx + CPUMCTXCORE.es]
-    mov     [edx + CPUMCPU.Hyper.es], eax
-    mov     eax, [ecx + CPUMCTXCORE.ds]
-    mov     [edx + CPUMCPU.Hyper.ds], eax
-    mov     eax, [ecx + CPUMCTXCORE.cs]
-    mov     [edx + CPUMCPU.Hyper.cs], eax
+    mov     eax, [ecx + CPUMCTXCORE.ss.Sel]
+    mov     [edx + CPUMCPU.Hyper.ss.Sel], eax
+    mov     eax, [ecx + CPUMCTXCORE.gs.Sel]
+    mov     [edx + CPUMCPU.Hyper.gs.Sel], eax
+    mov     eax, [ecx + CPUMCTXCORE.fs.Sel]
+    mov     [edx + CPUMCPU.Hyper.fs.Sel], eax
+    mov     eax, [ecx + CPUMCTXCORE.es.Sel]
+    mov     [edx + CPUMCPU.Hyper.es.Sel], eax
+    mov     eax, [ecx + CPUMCTXCORE.ds.Sel]
+    mov     [edx + CPUMCPU.Hyper.ds.Sel], eax
+    mov     eax, [ecx + CPUMCTXCORE.cs.Sel]
+    mov     [edx + CPUMCPU.Hyper.cs.Sel], eax
     ; flags
     mov     eax, [ecx + CPUMCTXCORE.eflags]
@@ -916,5 +916,5 @@
 %endif
     ; str     [edx + CPUMCPU.Hyper.tr] - double fault only, and it won't be right then either.
-    sldt    [edx + CPUMCPU.Hyper.ldtr]
+    sldt    [edx + CPUMCPU.Hyper.ldtr.Sel]
 
     ; No need to save CRx here. They are set dynamically according to Guest/Host requirements.
Index: trunk/src/VBox/VMM/include/CPUMInternal.mac
===================================================================
--- trunk/src/VBox/VMM/include/CPUMInternal.mac	(revision 41905)
+++ trunk/src/VBox/VMM/include/CPUMInternal.mac	(revision 41906)
@@ -115,34 +115,46 @@
     .Hyper.r14                resq    1
     .Hyper.r15                resq    1
-    .Hyper.es                 resw    1
-    .Hyper.esPadding          resw    3
-    .Hyper.esHid.u64Base      resq    1
-    .Hyper.esHid.u32Limit     resd    1
-    .Hyper.esHid.Attr         resd    1
-    .Hyper.cs                 resw    1
-    .Hyper.csPadding          resw    3
-    .Hyper.csHid.u64Base      resq    1
-    .Hyper.csHid.u32Limit     resd    1
-    .Hyper.csHid.Attr         resd    1
-    .Hyper.ss                 resw    1
-    .Hyper.ssPadding          resw    3
-    .Hyper.ssHid.u64Base      resq    1
-    .Hyper.ssHid.u32Limit     resd    1
-    .Hyper.ssHid.Attr         resd    1
-    .Hyper.ds                 resw    1
-    .Hyper.dsPadding          resw    3
-    .Hyper.dsHid.u64Base      resq    1
-    .Hyper.dsHid.u32Limit     resd    1
-    .Hyper.dsHid.Attr         resd    1
-    .Hyper.fs                 resw    1
-    .Hyper.fsPadding          resw    3
-    .Hyper.fsHid.u64Base      resq    1
-    .Hyper.fsHid.u32Limit     resd    1
-    .Hyper.fsHid.Attr         resd    1
-    .Hyper.gs                 resw    1
-    .Hyper.gsPadding          resw    3
-    .Hyper.gsHid.u64Base      resq    1
-    .Hyper.gsHid.u32Limit     resd    1
-    .Hyper.gsHid.Attr         resd    1
+    .Hyper.es.Sel             resw    1
+    .Hyper.es.PaddingSel      resw    1
+    .Hyper.es.ValidSel        resw    1
+    .Hyper.es.fFlags          resw    1
+    .Hyper.es.u64Base         resq    1
+    .Hyper.es.u32Limit        resd    1
+    .Hyper.es.Attr            resd    1
+    .Hyper.cs.Sel             resw    1
+    .Hyper.cs.PaddingSel      resw    1
+    .Hyper.cs.ValidSel        resw    1
+    .Hyper.cs.fFlags          resw    1
+    .Hyper.cs.u64Base         resq    1
+    .Hyper.cs.u32Limit        resd    1
+    .Hyper.cs.Attr            resd    1
+    .Hyper.ss.Sel             resw    1
+    .Hyper.ss.PaddingSel      resw    1
+    .Hyper.ss.ValidSel        resw    1
+    .Hyper.ss.fFlags          resw    1
+    .Hyper.ss.u64Base         resq    1
+    .Hyper.ss.u32Limit        resd    1
+    .Hyper.ss.Attr            resd    1
+    .Hyper.ds.Sel             resw    1
+    .Hyper.ds.PaddingSel      resw    1
+    .Hyper.ds.ValidSel        resw    1
+    .Hyper.ds.fFlags          resw    1
+    .Hyper.ds.u64Base         resq    1
+    .Hyper.ds.u32Limit        resd    1
+    .Hyper.ds.Attr            resd    1
+    .Hyper.fs.Sel             resw    1
+    .Hyper.fs.PaddingSel      resw    1
+    .Hyper.fs.ValidSel        resw    1
+    .Hyper.fs.fFlags          resw    1
+    .Hyper.fs.u64Base         resq    1
+    .Hyper.fs.u32Limit        resd    1
+    .Hyper.fs.Attr            resd    1
+    .Hyper.gs.Sel             resw    1
+    .Hyper.gs.PaddingSel      resw    1
+    .Hyper.gs.ValidSel        resw    1
+    .Hyper.gs.fFlags          resw    1
+    .Hyper.gs.u64Base         resq    1
+    .Hyper.gs.u32Limit        resd    1
+    .Hyper.gs.Attr            resd    1
     .Hyper.eip                resq    1
     .Hyper.eflags             resq    1
@@ -160,14 +172,18 @@
     .Hyper.idtr.cbIdt         resw    1
     .Hyper.idtr.pIdt          resq    1
-    .Hyper.ldtr               resw    1
-    .Hyper.ldtrPadding        resw    3
-    .Hyper.ldtrHid.u64Base    resq    1
-    .Hyper.ldtrHid.u32Limit   resd    1
-    .Hyper.ldtrHid.Attr       resd    1
-    .Hyper.tr                 resw    1
-    .Hyper.trPadding          resw    3
-    .Hyper.trHid.u64Base      resq    1
-    .Hyper.trHid.u32Limit     resd    1
-    .Hyper.trHid.Attr         resd    1
+    .Hyper.ldtr.Sel           resw    1
+    .Hyper.ldtr.PaddingSel    resw    1
+    .Hyper.ldtr.ValidSel      resw    1
+    .Hyper.ldtr.fFlags        resw    1
+    .Hyper.ldtr.u64Base       resq    1
+    .Hyper.ldtr.u32Limit      resd    1
+    .Hyper.ldtr.Attr          resd    1
+    .Hyper.tr.Sel             resw    1
+    .Hyper.tr.PaddingSel      resw    1
+    .Hyper.tr.ValidSel        resw    1
+    .Hyper.tr.fFlags          resw    1
+    .Hyper.tr.u64Base         resq    1
+    .Hyper.tr.u32Limit        resd    1
+    .Hyper.tr.Attr            resd    1
     .Hyper.SysEnter.cs        resb    8
     .Hyper.SysEnter.eip       resb    8
@@ -319,34 +335,46 @@
     .Guest.r14                resq    1
     .Guest.r15                resq    1
-    .Guest.es                 resw    1
-    .Guest.esPadding          resw    3
-    .Guest.esHid.u64Base      resq    1
-    .Guest.esHid.u32Limit     resd    1
-    .Guest.esHid.Attr         resd    1
-    .Guest.cs                 resw    1
-    .Guest.csPadding          resw    3
-    .Guest.csHid.u64Base      resq    1
-    .Guest.csHid.u32Limit     resd    1
-    .Guest.csHid.Attr         resd    1
-    .Guest.ss                 resw    1
-    .Guest.ssPadding          resw    3
-    .Guest.ssHid.u64Base      resq    1
-    .Guest.ssHid.u32Limit     resd    1
-    .Guest.ssHid.Attr         resd    1
-    .Guest.ds                 resw    1
-    .Guest.dsPadding          resw    3
-    .Guest.dsHid.u64Base      resq    1
-    .Guest.dsHid.u32Limit     resd    1
-    .Guest.dsHid.Attr         resd    1
-    .Guest.fs                 resw    1
-    .Guest.fsPadding          resw    3
-    .Guest.fsHid.u64Base      resq    1
-    .Guest.fsHid.u32Limit     resd    1
-    .Guest.fsHid.Attr         resd    1
-    .Guest.gs                 resw    1
-    .Guest.gsPadding          resw    3
-    .Guest.gsHid.u64Base      resq    1
-    .Guest.gsHid.u32Limit     resd    1
-    .Guest.gsHid.Attr         resd    1
+    .Guest.es.Sel             resw    1
+    .Guest.es.PaddingSel      resw    1
+    .Guest.es.ValidSel        resw    1
+    .Guest.es.fFlags          resw    1
+    .Guest.es.u64Base         resq    1
+    .Guest.es.u32Limit        resd    1
+    .Guest.es.Attr            resd    1
+    .Guest.cs.Sel             resw    1
+    .Guest.cs.PaddingSel      resw    1
+    .Guest.cs.ValidSel        resw    1
+    .Guest.cs.fFlags          resw    1
+    .Guest.cs.u64Base         resq    1
+    .Guest.cs.u32Limit        resd    1
+    .Guest.cs.Attr            resd    1
+    .Guest.ss.Sel             resw    1
+    .Guest.ss.PaddingSel      resw    1
+    .Guest.ss.ValidSel        resw    1
+    .Guest.ss.fFlags          resw    1
+    .Guest.ss.u64Base         resq    1
+    .Guest.ss.u32Limit        resd    1
+    .Guest.ss.Attr            resd    1
+    .Guest.ds.Sel             resw    1
+    .Guest.ds.PaddingSel      resw    1
+    .Guest.ds.ValidSel        resw    1
+    .Guest.ds.fFlags          resw    1
+    .Guest.ds.u64Base         resq    1
+    .Guest.ds.u32Limit        resd    1
+    .Guest.ds.Attr            resd    1
+    .Guest.fs.Sel             resw    1
+    .Guest.fs.PaddingSel      resw    1
+    .Guest.fs.ValidSel        resw    1
+    .Guest.fs.fFlags          resw    1
+    .Guest.fs.u64Base         resq    1
+    .Guest.fs.u32Limit        resd    1
+    .Guest.fs.Attr            resd    1
+    .Guest.gs.Sel             resw    1
+    .Guest.gs.PaddingSel      resw    1
+    .Guest.gs.ValidSel        resw    1
+    .Guest.gs.fFlags          resw    1
+    .Guest.gs.u64Base         resq    1
+    .Guest.gs.u32Limit        resd    1
+    .Guest.gs.Attr            resd    1
     .Guest.eip                resq    1
     .Guest.eflags             resq    1
@@ -364,14 +392,18 @@
     .Guest.idtr.cbIdt         resw    1
     .Guest.idtr.pIdt          resq    1
-    .Guest.ldtr               resw    1
-    .Guest.ldtrPadding        resw    3
-    .Guest.ldtrHid.u64Base    resq    1
-    .Guest.ldtrHid.u32Limit   resd    1
-    .Guest.ldtrHid.Attr       resd    1
-    .Guest.tr                 resw    1
-    .Guest.trPadding          resw    3
-    .Guest.trHid.u64Base      resq    1
-    .Guest.trHid.u32Limit     resd    1
-    .Guest.trHid.Attr         resd    1
+    .Guest.ldtr.Sel           resw    1
+    .Guest.ldtr.PaddingSel    resw    1
+    .Guest.ldtr.ValidSel      resw    1
+    .Guest.ldtr.fFlags        resw    1
+    .Guest.ldtr.u64Base       resq    1
+    .Guest.ldtr.u32Limit      resd    1
+    .Guest.ldtr.Attr          resd    1
+    .Guest.tr.Sel             resw    1
+    .Guest.tr.PaddingSel      resw    1
+    .Guest.tr.ValidSel        resw    1
+    .Guest.tr.fFlags          resw    1
+    .Guest.tr.u64Base         resq    1
+    .Guest.tr.u32Limit        resd    1
+    .Guest.tr.Attr            resd    1
     .Guest.SysEnter.cs        resb    8
     .Guest.SysEnter.eip       resb    8
Index: trunk/src/VBox/VMM/include/EMHandleRCTmpl.h
===================================================================
--- trunk/src/VBox/VMM/include/EMHandleRCTmpl.h	(revision 41905)
+++ trunk/src/VBox/VMM/include/EMHandleRCTmpl.h	(revision 41906)
@@ -112,5 +112,7 @@
         case VINF_PATM_HC_MMIO_PATCH_READ:
             rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
-                                    PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0));
+                                      PATMFL_MMIO_ACCESS
+                                    | (    SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs)
+                                        == DISCPUMODE_32BIT ? PATMFL_CODE32 : 0));
             if (RT_FAILURE(rc))
                 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
Index: trunk/src/VBox/VMM/testcase/tstMicroRCA.asm
===================================================================
--- trunk/src/VBox/VMM/testcase/tstMicroRCA.asm	(revision 41905)
+++ trunk/src/VBox/VMM/testcase/tstMicroRCA.asm	(revision 41906)
@@ -502,5 +502,5 @@
                               ;40
 
-    test    byte [esp + CPUMCTXCORE.cs], 3h ; check CPL of the cs selector
+    test    byte [esp + CPUMCTXCORE.cs.Sel], 3h ; check CPL of the cs selector
     jmp short tstTrapHandler_Fault_Hyper ;; @todo
     jz short tstTrapHandler_Fault_Hyper
@@ -516,5 +516,5 @@
     lea     ebx, [esp + 14h + 040h]     ; calc esp at trap
     mov     [esp + CPUMCTXCORE.esp], ebx; update esp in register frame
-    mov     [esp + CPUMCTXCORE.ss], ss  ; update ss in register frame
+    mov     [esp + CPUMCTXCORE.ss.Sel], ss  ; update ss in register frame
 
     mov     ecx, esp
Index: trunk/src/VBox/VMM/testcase/tstVMStruct.h
===================================================================
--- trunk/src/VBox/VMM/testcase/tstVMStruct.h	(revision 41905)
+++ trunk/src/VBox/VMM/testcase/tstVMStruct.h	(revision 41906)
@@ -148,10 +148,18 @@
     GEN_CHECK_OFF(CPUMCTX, rcx);
     GEN_CHECK_OFF(CPUMCTX, rsp);
+    GEN_CHECK_OFF(CPUMCTX, es);
+#ifndef VBOX_FOR_DTRACE_LIB
+    GEN_CHECK_OFF(CPUMCTX, es.Sel);
+    GEN_CHECK_OFF(CPUMCTX, es.ValidSel);
+    GEN_CHECK_OFF(CPUMCTX, es.fFlags);
+    GEN_CHECK_OFF(CPUMCTX, es.u64Base);
+    GEN_CHECK_OFF(CPUMCTX, es.u32Limit);
+    GEN_CHECK_OFF(CPUMCTX, es.Attr);
+#endif
+    GEN_CHECK_OFF(CPUMCTX, cs);
     GEN_CHECK_OFF(CPUMCTX, ss);
+    GEN_CHECK_OFF(CPUMCTX, ds);
+    GEN_CHECK_OFF(CPUMCTX, fs);
     GEN_CHECK_OFF(CPUMCTX, gs);
-    GEN_CHECK_OFF(CPUMCTX, fs);
-    GEN_CHECK_OFF(CPUMCTX, es);
-    GEN_CHECK_OFF(CPUMCTX, ds);
-    GEN_CHECK_OFF(CPUMCTX, cs);
     GEN_CHECK_OFF(CPUMCTX, rflags);
     GEN_CHECK_OFF(CPUMCTX, rip);
@@ -164,10 +172,4 @@
     GEN_CHECK_OFF(CPUMCTX, r14);
     GEN_CHECK_OFF(CPUMCTX, r15);
-    GEN_CHECK_OFF(CPUMCTX, esHid);
-    GEN_CHECK_OFF(CPUMCTX, csHid);
-    GEN_CHECK_OFF(CPUMCTX, ssHid);
-    GEN_CHECK_OFF(CPUMCTX, dsHid);
-    GEN_CHECK_OFF(CPUMCTX, fsHid);
-    GEN_CHECK_OFF(CPUMCTX, gsHid);
     GEN_CHECK_OFF(CPUMCTX, cr0);
     GEN_CHECK_OFF(CPUMCTX, cr2);
@@ -187,6 +189,14 @@
     GEN_CHECK_OFF(CPUMCTX, msrSFMASK);
     GEN_CHECK_OFF(CPUMCTX, msrKERNELGSBASE);
-    GEN_CHECK_OFF(CPUMCTX, ldtrHid);
-    GEN_CHECK_OFF(CPUMCTX, trHid);
+    GEN_CHECK_OFF(CPUMCTX, ldtr);
+    GEN_CHECK_OFF(CPUMCTX, tr);
+#ifndef VBOX_FOR_DTRACE_LIB
+    GEN_CHECK_OFF(CPUMCTX, tr.Sel);
+    GEN_CHECK_OFF(CPUMCTX, tr.ValidSel);
+    GEN_CHECK_OFF(CPUMCTX, tr.fFlags);
+    GEN_CHECK_OFF(CPUMCTX, tr.u64Base);
+    GEN_CHECK_OFF(CPUMCTX, tr.u32Limit);
+    GEN_CHECK_OFF(CPUMCTX, tr.Attr);
+#endif
 
     GEN_CHECK_SIZE(CPUMCTXMSRS);
Index: trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp
===================================================================
--- trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp	(revision 41905)
+++ trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp	(revision 41906)
@@ -295,19 +295,11 @@
     CHECK_MEMBER_ALIGNMENT(CPUMCTX, SysEnter, 8);
     CHECK_CPUMCTXCORE(rax);
-    CHECK_CPUMCTXCORE(rbx);
     CHECK_CPUMCTXCORE(rcx);
     CHECK_CPUMCTXCORE(rdx);
+    CHECK_CPUMCTXCORE(rbx);
+    CHECK_CPUMCTXCORE(rsp);
     CHECK_CPUMCTXCORE(rbp);
-    CHECK_CPUMCTXCORE(rsp);
+    CHECK_CPUMCTXCORE(rsi);
     CHECK_CPUMCTXCORE(rdi);
-    CHECK_CPUMCTXCORE(rsi);
-    CHECK_CPUMCTXCORE(rip);
-    CHECK_CPUMCTXCORE(rflags);
-    CHECK_CPUMCTXCORE(cs);
-    CHECK_CPUMCTXCORE(ds);
-    CHECK_CPUMCTXCORE(es);
-    CHECK_CPUMCTXCORE(fs);
-    CHECK_CPUMCTXCORE(gs);
-    CHECK_CPUMCTXCORE(ss);
     CHECK_CPUMCTXCORE(r8);
     CHECK_CPUMCTXCORE(r9);
@@ -318,10 +310,12 @@
     CHECK_CPUMCTXCORE(r14);
     CHECK_CPUMCTXCORE(r15);
-    CHECK_CPUMCTXCORE(esHid);
-    CHECK_CPUMCTXCORE(csHid);
-    CHECK_CPUMCTXCORE(ssHid);
-    CHECK_CPUMCTXCORE(dsHid);
-    CHECK_CPUMCTXCORE(fsHid);
-    CHECK_CPUMCTXCORE(gsHid);
+    CHECK_CPUMCTXCORE(es);
+    CHECK_CPUMCTXCORE(ss);
+    CHECK_CPUMCTXCORE(cs);
+    CHECK_CPUMCTXCORE(ds);
+    CHECK_CPUMCTXCORE(fs);
+    CHECK_CPUMCTXCORE(gs);
+    CHECK_CPUMCTXCORE(rip);
+    CHECK_CPUMCTXCORE(rflags);
 
 #if HC_ARCH_BITS == 32
