Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41934)
+++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41935)
@@ -446,5 +446,4 @@
 VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
 #ifdef VBOX_WITH_IEM
@@ -502,5 +501,4 @@
 {
     LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
 #ifdef VBOX_WITH_IEM
     NOREF(pvFault);
@@ -566,5 +564,4 @@
 {
     LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
 #ifdef VBOX_WITH_IEM
     NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
@@ -609,5 +606,4 @@
     int         rc;
 
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     Assert(!CPUMIsGuestIn64BitCode(pVCpu, pRegFrame));
     /** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
@@ -675,5 +671,4 @@
 VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint32_t iLeaf = pRegFrame->eax;
     NOREF(pVM);
@@ -703,5 +698,4 @@
 VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
 
@@ -730,6 +724,5 @@
 VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
 {
-    Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
-    uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
+    unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
 
     if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
@@ -765,6 +758,5 @@
 VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
-    uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
+    unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
 
     /* If X86_CR4_PCE is not set, then CPL must be zero. */
@@ -791,5 +783,4 @@
 VMMDECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
     NOREF(pVM);
@@ -831,5 +822,4 @@
 {
     uint32_t u32Dummy, u32ExtFeatures, cpl;
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     NOREF(pVM);
 
@@ -872,5 +862,4 @@
      * (in absence of segment override prefixes)????
      */
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     NOREF(pVM); NOREF(pRegFrame);
 #ifdef IN_RC
@@ -908,5 +897,4 @@
     /** @todo Clean up this mess. */
     LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     switch (DestRegCrx)
     {
@@ -1044,5 +1032,4 @@
     uint64_t val;
     int      rc;
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
 
     if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
@@ -1075,5 +1062,4 @@
 VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
 
@@ -1098,5 +1084,4 @@
 {
     NOREF(pVM);
-
     uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
     if (!(cr0 & X86_CR0_TS))
@@ -1119,5 +1104,4 @@
 VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint64_t val64;
     int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
@@ -1152,5 +1136,4 @@
 VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint64_t val;
     int      rc;
@@ -1194,5 +1177,4 @@
 {
     uint64_t val64;
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     NOREF(pVM);
 
@@ -3045,6 +3027,4 @@
 VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
-
     /* Check the current privilege level, this instruction is supervisor only. */
     if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 41934)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 41935)
@@ -7777,4 +7777,34 @@
 
 /**
+ * Updates the real CPU context structure with the context core (from the trap
+ * stack frame) before interpreting any instructions.
+ *
+ * @param   pCtx        The real CPU context.
+ * @param   pCtxCore    The trap stack CPU core context.
+ */
+DECLINLINE(void) iemCtxCoreToCtx(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore)
+{
+    PCPUMCTXCORE pDst = CPUMCTX2CORE(pCtx);
+    if (pDst != pCtxCore)
+        *pDst = *pCtxCore;
+}
+
+
+/**
+ * Updates the context core (from the trap stack frame) with the updated values
+ * from the real CPU context structure after instruction emulation.
+ *
+ * @param   pCtx        The real CPU context.
+ * @param   pCtxCore    The trap stack CPU core context.
+ */
+DECLINLINE(void) iemCtxToCtxCore(PCPUMCTXCORE pCtxCore, PCCPUMCTX pCtx)
+{
+    PCCPUMCTXCORE pSrc = CPUMCTX2CORE(pCtx);
+    if (pSrc != pCtxCore)
+        *pCtxCore = *pSrc;
+}
+
+
+/**
  * The actual code execution bits of IEMExecOne, IEMExecOneEx, and
  * IEMExecOneWithPrefetchedByPC.
@@ -7886,6 +7916,6 @@
     PIEMCPU  pIemCpu = &pVCpu->iem.s;
     PCPUMCTX pCtx    = pVCpu->iem.s.CTX_SUFF(pCtx);
-    AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
-
+
+    iemCtxCoreToCtx(pCtx, pCtxCore);
     iemInitDecoder(pIemCpu);
     uint32_t const cbOldWritten = pIemCpu->cbWritten;
@@ -7895,4 +7925,6 @@
     {
         rcStrict = iemExecOneInner(pVCpu, pIemCpu);
+        if (rcStrict == VINF_SUCCESS)
+            iemCtxToCtxCore(pCtxCore, pCtx);
         if (pcbWritten)
             *pcbWritten = pIemCpu->cbWritten - cbOldWritten;
@@ -7907,5 +7939,6 @@
     PIEMCPU  pIemCpu = &pVCpu->iem.s;
     PCPUMCTX pCtx    = pVCpu->iem.s.CTX_SUFF(pCtx);
-    AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
+
+    iemCtxCoreToCtx(pCtx, pCtxCore);
 
     VBOXSTRICTRC rcStrict;
@@ -7923,4 +7956,6 @@
     {
         rcStrict = iemExecOneInner(pVCpu, pIemCpu);
+        if (rcStrict == VINF_SUCCESS)
+            iemCtxToCtxCore(pCtxCore, pCtx);
     }
     return rcStrict;
Index: /trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac
===================================================================
--- /trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac	(revision 41934)
+++ /trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac	(revision 41935)
@@ -661,5 +661,4 @@
 
 
-GLOBALNAME End
 ;
 ; The description string (in the text section).
