Index: /trunk/include/VBox/err.h
===================================================================
--- /trunk/include/VBox/err.h	(revision 41936)
+++ /trunk/include/VBox/err.h	(revision 41937)
@@ -2108,4 +2108,6 @@
 /** Internal processing error \#2 in the IEM code.. */
 #define VERR_IEM_IPE_2                              (-5393)
+/** Internal processing error \#3 in the IEM code.. */
+#define VERR_IEM_IPE_3                              (-5394)
 /** @} */
 
Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41936)
+++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41937)
@@ -446,4 +446,5 @@
 VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
 #ifdef VBOX_WITH_IEM
@@ -501,4 +502,5 @@
 {
     LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
 #ifdef VBOX_WITH_IEM
     NOREF(pvFault);
@@ -564,4 +566,5 @@
 {
     LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
 #ifdef VBOX_WITH_IEM
     NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
@@ -606,4 +609,5 @@
     int         rc;
 
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     Assert(!CPUMIsGuestIn64BitCode(pVCpu, pRegFrame));
     /** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
@@ -671,4 +675,5 @@
 VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint32_t iLeaf = pRegFrame->eax;
     NOREF(pVM);
@@ -698,4 +703,5 @@
 VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
 
@@ -724,5 +730,6 @@
 VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
 {
-    unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
+    Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
+    uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
 
     if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
@@ -758,5 +765,6 @@
 VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
-    unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
+    uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
 
     /* If X86_CR4_PCE is not set, then CPL must be zero. */
@@ -783,4 +791,5 @@
 VMMDECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
     NOREF(pVM);
@@ -822,4 +831,5 @@
 {
     uint32_t u32Dummy, u32ExtFeatures, cpl;
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     NOREF(pVM);
 
@@ -862,4 +872,5 @@
      * (in absence of segment override prefixes)????
      */
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     NOREF(pVM); NOREF(pRegFrame);
 #ifdef IN_RC
@@ -897,4 +908,5 @@
     /** @todo Clean up this mess. */
     LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     switch (DestRegCrx)
     {
@@ -1032,4 +1044,5 @@
     uint64_t val;
     int      rc;
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
 
     if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
@@ -1062,4 +1075,5 @@
 VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
 
@@ -1084,4 +1098,5 @@
 {
     NOREF(pVM);
+
     uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
     if (!(cr0 & X86_CR0_TS))
@@ -1104,4 +1119,5 @@
 VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint64_t val64;
     int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
@@ -1136,4 +1152,5 @@
 VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     uint64_t val;
     int      rc;
@@ -1177,4 +1194,5 @@
 {
     uint64_t val64;
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     NOREF(pVM);
 
@@ -3027,4 +3045,6 @@
 VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
 {
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
+
     /* Check the current privilege level, this instruction is supervisor only. */
     if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 41936)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 41937)
@@ -7777,34 +7777,4 @@
 
 /**
- * Updates the real CPU context structure with the context core (from the trap
- * stack frame) before interpreting any instructions.
- *
- * @param   pCtx        The real CPU context.
- * @param   pCtxCore    The trap stack CPU core context.
- */
-DECLINLINE(void) iemCtxCoreToCtx(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore)
-{
-    PCPUMCTXCORE pDst = CPUMCTX2CORE(pCtx);
-    if (pDst != pCtxCore)
-        *pDst = *pCtxCore;
-}
-
-
-/**
- * Updates the context core (from the trap stack frame) with the updated values
- * from the real CPU context structure after instruction emulation.
- *
- * @param   pCtx        The real CPU context.
- * @param   pCtxCore    The trap stack CPU core context.
- */
-DECLINLINE(void) iemCtxToCtxCore(PCPUMCTXCORE pCtxCore, PCCPUMCTX pCtx)
-{
-    PCCPUMCTXCORE pSrc = CPUMCTX2CORE(pCtx);
-    if (pSrc != pCtxCore)
-        *pCtxCore = *pSrc;
-}
-
-
-/**
  * The actual code execution bits of IEMExecOne, IEMExecOneEx, and
  * IEMExecOneWithPrefetchedByPC.
@@ -7916,6 +7886,6 @@
     PIEMCPU  pIemCpu = &pVCpu->iem.s;
     PCPUMCTX pCtx    = pVCpu->iem.s.CTX_SUFF(pCtx);
-
-    iemCtxCoreToCtx(pCtx, pCtxCore);
+    AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
+
     iemInitDecoder(pIemCpu);
     uint32_t const cbOldWritten = pIemCpu->cbWritten;
@@ -7925,6 +7895,4 @@
     {
         rcStrict = iemExecOneInner(pVCpu, pIemCpu);
-        if (rcStrict == VINF_SUCCESS)
-            iemCtxToCtxCore(pCtxCore, pCtx);
         if (pcbWritten)
             *pcbWritten = pIemCpu->cbWritten - cbOldWritten;
@@ -7939,6 +7907,5 @@
     PIEMCPU  pIemCpu = &pVCpu->iem.s;
     PCPUMCTX pCtx    = pVCpu->iem.s.CTX_SUFF(pCtx);
-
-    iemCtxCoreToCtx(pCtx, pCtxCore);
+    AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
 
     VBOXSTRICTRC rcStrict;
@@ -7956,6 +7923,4 @@
     {
         rcStrict = iemExecOneInner(pVCpu, pIemCpu);
-        if (rcStrict == VINF_SUCCESS)
-            iemCtxToCtxCore(pCtxCore, pCtx);
     }
     return rcStrict;
