Changeset 42024 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Jul 5, 2012 12:10:53 PM (12 years ago)

Author:

vboxsync

Message:

VMM: RDTSCP support on Intel. Segregated some common CPU features from the AMD superset into Extended features as they're now available on Intel too.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• CPUMR0.cpp (modified) (1 diff)
• HWSVMR0.cpp (modified) (1 diff)
• HWVMXR0.cpp (modified) (10 diffs)
• TRPMR0.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -186 +186 @@
         {
             uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
-            if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_SEP)
+            if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
             {
 #ifdef RT_ARCH_X86
 # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
-                if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
+                if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
 # else
                 if (!ASMIsIntelCpu())

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -2219 +2219 @@
     {
         Log2(("SVM: Rdtscp\n"));
-        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
+        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtscp);
         rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
         if (rc == VINF_SUCCESS)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -568 +568 @@
             if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
                 val |= VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE;
+
+            if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
+                val |= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP;
 
             /* Mask away the bits that the CPU doesn't support */
@@ -1316 +1319 @@
          * Check if EFER MSR present.
          */
-        if (ASMCpuId_EDX(0x80000001) & (X86_CPUID_AMD_FEATURE_EDX_NX|X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
-        {
-            if (ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP)
+        if (ASMCpuId_EDX(0x80000001) & (X86_CPUID_EXT_FEATURE_EDX_NX | X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
+        {
+            if (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
             {
                 pMsr->u32IndexMSR = MSR_K6_STAR;
                 pMsr->u32Reserved = 0;
-                pMsr->u64Value    = ASMRdMsr(MSR_K6_STAR);                   /* legacy syscall eip, cs & ss */
+                pMsr->u64Value    = ASMRdMsr(MSR_K6_STAR);          /* legacy syscall eip, cs & ss */
                 pMsr++; idxMsr++;
             }
@@ -2098 +2101 @@
     CPUMGetGuestCpuId(pVCpu, 0x80000001, &ulTemp, &ulTemp, &ulTemp, &ulEdx);
     /* EFER MSR present? */
-    if (ulEdx & (X86_CPUID_AMD_FEATURE_EDX_NX|X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
+    if (ulEdx & (X86_CPUID_EXT_FEATURE_EDX_NX | X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
     {
         pMsr->u32IndexMSR = MSR_K6_EFER;
@@ -2105 +2108 @@
         /* VT-x will complain if only MSR_K6_EFER_LME is set. */
         if (!CPUMIsGuestInLongModeEx(pCtx))
-            pMsr->u64Value &= ~(MSR_K6_EFER_LMA|MSR_K6_EFER_LME);
+            pMsr->u64Value &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
         pMsr++; idxMsr++;
 
-        if (ulEdx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
+        if (ulEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
         {
             pMsr->u32IndexMSR = MSR_K8_LSTAR;
@@ -2161 +2164 @@
         if (u64CurTSC + pVCpu->hwaccm.s.vmx.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
         {
-            /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
+            /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
             rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, pVCpu->hwaccm.s.vmx.u64TSCOffset);
             AssertRC(rc);
@@ -2172 +2175 @@
         else
         {
-            /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
+            /* Fall back to rdtsc, rdtscp emulation as we would otherwise pass decreasing tsc values to the guest. */
             LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC,
                      pVCpu->hwaccm.s.vmx.u64TSCOffset, u64CurTSC + pVCpu->hwaccm.s.vmx.u64TSCOffset,
@@ -2332 +2335 @@
         switch (pMsr->u32IndexMSR)
         {
-        case MSR_K8_LSTAR:
-            pCtx->msrLSTAR = pMsr->u64Value;
-            break;
-        case MSR_K6_STAR:
-            pCtx->msrSTAR = pMsr->u64Value;
-            break;
-        case MSR_K8_SF_MASK:
-            pCtx->msrSFMASK = pMsr->u64Value;
-            break;
-        case MSR_K8_KERNEL_GS_BASE:
-            pCtx->msrKERNELGSBASE = pMsr->u64Value;
-            break;
-        case MSR_K6_EFER:
-            /* EFER can't be changed without causing a VM-exit. */
-            /* Assert(pCtx->msrEFER == pMsr->u64Value); */
-            break;
-        default:
-            AssertFailed();
-            return VERR_HM_UNEXPECTED_LD_ST_MSR;
+            case MSR_K8_LSTAR:
+                pCtx->msrLSTAR = pMsr->u64Value;
+                break;
+            case MSR_K6_STAR:
+                pCtx->msrSTAR = pMsr->u64Value;
+                break;
+            case MSR_K8_SF_MASK:
+                pCtx->msrSFMASK = pMsr->u64Value;
+                break;
+            case MSR_K8_KERNEL_GS_BASE:
+                pCtx->msrKERNELGSBASE = pMsr->u64Value;
+                break;
+            case MSR_K6_EFER:
+                /* EFER can't be changed without causing a VM-exit. */
+                /* Assert(pCtx->msrEFER == pMsr->u64Value); */
+                break;
+            default:
+                AssertFailed();
+                return VERR_HM_UNEXPECTED_LD_ST_MSR;
         }
     }
@@ -2453 +2456 @@
     else
     {
-        AssertMsg(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID, ("hwaccm uCurrentASID=%lu cpu uCurrentASID=%lu\n",
-                                                                       pVCpu->hwaccm.s.uCurrentASID, pCpu->uCurrentASID));
+        AssertMsg(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID,
+                  ("hwaccm->uCurrentASID=%lu hwaccm->cTLBFlushes=%lu cpu->uCurrentASID=%lu cpu->cTLBFlushes=%lu\n",
+                   pVCpu->hwaccm.s.uCurrentASID, pVCpu->hwaccm.s.cTLBFlushes,
+                   pCpu->uCurrentASID, pCpu->cTLBFlushes));
 
         /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
@@ -4046 +4051 @@
             /* Update EIP and continue execution. */
             Assert(cbInstr == 2);
+            pCtx->rip += cbInstr;
+            goto ResumeExecution;
+        }
+        rc = VINF_EM_RAW_EMULATE_INSTR;
+        break;
+    }
+
+    case VMX_EXIT_RDTSCP:                /* 51 Guest software attempted to execute RDTSCP. */
+    {
+        Log2(("VMX: Rdtscp\n"));
+        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtscp);
+        rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
+        if (rc == VINF_SUCCESS)
+        {
+            /* Update EIP and continue execution. */
+            Assert(cbInstr == 3);
             pCtx->rip += cbInstr;
             goto ResumeExecution;
@@ -4626 +4647 @@
     case VMX_EXIT_PORT_IO:              /* 30 I/O instruction. */
     case VMX_EXIT_RDPMC:                /* 15 Guest software attempted to execute RDPMC. */
+    case VMX_EXIT_RDTSCP:               /* 51 Guest software attempted to execute RDTSCP. */
         /* already handled above */
         AssertMsg(   rc == VINF_PGM_CHANGE_MODE

trunk/src/VBox/VMM/VMMR0/TRPMR0.cpp

@@ -62 +62 @@
      * Check if we're in long mode or not.
      */
-    if (    (ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
+    if (    (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
         &&  (ASMRdMsr(MSR_K6_EFER) & MSR_K6_EFER_LMA))
     {