Changeset 42024 in vbox for trunk/src/VBox/VMM/VMMR3
- Timestamp:
- Jul 5, 2012 12:10:53 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 78914
- Location:
- trunk/src/VBox/VMM/VMMR3
- Files:
-
- 3 edited
-
CPUM.cpp (modified) (16 diffs)
-
HWACCM.cpp (modified) (11 diffs)
-
VMMSwitcher.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r41965 r42024 684 684 */ 685 685 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit} 686 * Overrides the host CPUID leaf values used for calculating the guest CPUID 687 * leaves. This can be used to preserve the CPUID values when moving a VM 688 * to a different machine. Another use is restricting (or extending) the 689 * feature set exposed to the guest. */ 686 * Loads the host CPUID leaves to the guest copy. Overrides, if any, the host 687 * CPUID leaf values used for calculating the guest CPUID leaves. This can be 688 * used to preserve the CPUID values when moving a VM to a different machine. 689 * Another use is restricting (or extending) the feature set exposed to the 690 * guest. */ 690 691 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID"); 691 692 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg); … … 825 826 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present. 826 827 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */ 827 //| X86_CPUID_ AMD_FEATURE_EDX_SEP828 //| X86_CPUID_EXT_FEATURE_EDX_SEP 828 829 | X86_CPUID_AMD_FEATURE_EDX_MTRR 829 830 | X86_CPUID_AMD_FEATURE_EDX_PGE … … 832 833 | X86_CPUID_AMD_FEATURE_EDX_PAT 833 834 | X86_CPUID_AMD_FEATURE_EDX_PSE36 834 //| X86_CPUID_ AMD_FEATURE_EDX_NX - not virtualized, requires PAE.835 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE. 835 836 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX 836 837 | X86_CPUID_AMD_FEATURE_EDX_MMX 837 838 | X86_CPUID_AMD_FEATURE_EDX_FXSR 838 839 | X86_CPUID_AMD_FEATURE_EDX_FFXSR 839 //| X86_CPUID_ AMD_FEATURE_EDX_PAGE1GB840 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary841 //| X86_CPUID_ AMD_FEATURE_EDX_LONG_MODE - turned on when necessary840 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB 841 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP 842 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary 842 843 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX 843 844 | X86_CPUID_AMD_FEATURE_EDX_3DNOW 844 845 | 0; 845 846 pCPUM->aGuestCpuIdExt[1].ecx &= 0 846 //| X86_CPUID_ AMD_FEATURE_ECX_LAHF_SAHF847 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF 847 848 //| X86_CPUID_AMD_FEATURE_ECX_CMPL 848 849 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized. … … 866 867 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX); 867 868 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR); 868 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_ AMD_FEATURE_EDX_RDTSCP);869 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_ AMD_FEATURE_ECX_LAHF_SAHF);869 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP); 870 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); 870 871 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV); 871 872 … … 886 887 ))); 887 888 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10) 888 | X86_CPUID_ AMD_FEATURE_EDX_SEP889 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL 889 890 | RT_BIT(18) 890 891 | RT_BIT(19) 891 892 | RT_BIT(21) 892 893 | X86_CPUID_AMD_FEATURE_EDX_AXMMX 893 | X86_CPUID_ AMD_FEATURE_EDX_PAGE1GB894 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB 894 895 | RT_BIT(28) 895 896 ))); … … 929 930 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0; 930 931 931 /* 0x800000001: AMD only;shared feature bits are set dynamically. */932 /* 0x800000001: shared feature bits are set dynamically. */ 932 933 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1])); 933 934 … … 1220 1221 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc); 1221 1222 if (fEnable) 1222 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX E);1223 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX); 1223 1224 1224 1225 /* … … 1927 1928 1928 1929 /* CPUID(0x80000001).ecx */ 1929 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_ AMD_FEATURE_ECX_LAHF_SAHF);1930 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); 1930 1931 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); 1931 1932 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); … … 1972 1973 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC); 1973 1974 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/); 1974 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_SEP);1975 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP); 1975 1976 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR); 1976 1977 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE); … … 1981 1982 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/); 1982 1983 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/); 1983 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_NX);1984 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX); 1984 1985 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/); 1985 1986 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX); … … 1987 1988 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR); 1988 1989 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR); 1989 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_PAGE1GB);1990 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_RDTSCP);1990 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB); 1991 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP); 1991 1992 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/); 1992 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_LONG_MODE);1993 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE); 1993 1994 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX); 1994 1995 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW); … … 2089 2090 2090 2091 /* CPUID(0x80000001).ecx */ 2091 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_ AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU2092 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU 2092 2093 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU 2093 2094 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU … … 2134 2135 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC); 2135 2136 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/); 2136 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_SEP); //Intel: long mode only.2137 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only. 2137 2138 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR); 2138 2139 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE); … … 2143 2144 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/); 2144 2145 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/); 2145 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_NX);2146 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX); 2146 2147 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/); 2147 2148 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX); … … 2149 2150 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU 2150 2151 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR); 2151 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_PAGE1GB);2152 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_RDTSCP);2152 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB); 2153 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP); 2153 2154 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/); 2154 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_ AMD_FEATURE_EDX_LONG_MODE);2155 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE); 2155 2156 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX); 2156 2157 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW); … … 3436 3437 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23))); 3437 3438 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24))); 3438 pHlp->pfnPrintf(pHlp, " 25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));3439 pHlp->pfnPrintf(pHlp, " 26 - 1 GB large page support= %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));3440 pHlp->pfnPrintf(pHlp, " 27 - RDTSCP instruction= %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));3439 pHlp->pfnPrintf(pHlp, "AMD fast FXSAVE and FXRSTOR Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25))); 3440 pHlp->pfnPrintf(pHlp, "1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26))); 3441 pHlp->pfnPrintf(pHlp, "RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27))); 3441 3442 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28))); 3442 pHlp->pfnPrintf(pHlp, " 29 - AMD Long Mode= %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));3443 pHlp->pfnPrintf(pHlp, " 30 - AMD Extensions to 3DNow= %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));3444 pHlp->pfnPrintf(pHlp, " 31 - AMD 3DNow= %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));3443 pHlp->pfnPrintf(pHlp, "AMD Long Mode / Intel 64 ISA = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29))); 3444 pHlp->pfnPrintf(pHlp, "AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30))); 3445 pHlp->pfnPrintf(pHlp, "AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31))); 3445 3446 3446 3447 uint32_t uEcxGst = Guest.ecx; -
trunk/src/VBox/VMM/VMMR3/HWACCM.cpp
r41965 r42024 110 110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."), 111 111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."), 112 EXIT_REASON _NIL(),112 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."), 113 113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."), 114 114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."), … … 514 514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid"); 515 515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc"); 516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtscp, "/HWACCM/CPU%d/Exit/Instr/Rdtscp"); 516 517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc"); 517 518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr"); … … 928 929 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT) 929 930 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n")); 930 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP _EXIT)931 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP _EXIT\n"));931 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) 932 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP\n")); 932 933 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC) 933 934 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n")); … … 946 947 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT) 947 948 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n")); 948 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP _EXIT)949 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP _EXIT*must* be set\n"));949 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) 950 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP *must* be set\n")); 950 951 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC) 951 952 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n")); … … 1090 1091 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc))); 1091 1092 else 1092 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift)); 1093 { 1094 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", 1095 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift)); 1096 } 1093 1097 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc))); 1094 1098 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc))); … … 1188 1192 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */ 1189 1193 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF); 1190 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX E);1194 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX); 1191 1195 } 1192 1196 else … … 1195 1199 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE) 1196 1200 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE)) 1197 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX E);1201 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX); 1198 1202 1199 1203 LogRel((pVM->hwaccm.s.fAllow64BitGuests … … 1248 1252 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy); 1249 1253 if ( u32Eax < 0x80000001 1250 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_ AMD_FEATURE_EDX_LONG_MODE))1254 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)) 1251 1255 { 1252 1256 pVM->hwaccm.s.fTRPPatchingAllowed = false; … … 1377 1381 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP); 1378 1382 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); 1379 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);1380 1383 #ifdef VBOX_ENABLE_64_BITS_GUESTS 1381 1384 if (pVM->hwaccm.s.fAllow64BitGuests) … … 1383 1386 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE); 1384 1387 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE); 1385 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX E);1388 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX); 1386 1389 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF); 1387 1390 } … … 1389 1392 /* Turn on NXE if PAE has been enabled. */ 1390 1393 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)) 1391 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX E);1394 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX); 1392 1395 #endif 1393 1396 -
trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp
r41976 r42024 536 536 { 537 537 uint32_t u32OrMask = MSR_K6_EFER_LME | MSR_K6_EFER_SCE; 538 /** note: we don't care if cpuid 0x8000001 isn't supported as that implies long mode isn't either, so this switcher would never be used. */ 539 if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX)) 538 /* 539 * We don't care if cpuid 0x8000001 isn't supported as that implies 540 * long mode isn't supported either, so this switched would never be used. 541 */ 542 if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX)) 540 543 u32OrMask |= MSR_K6_EFER_NXE; 541 544
Note:
See TracChangeset
for help on using the changeset viewer.
