Changeset 42420 in vbox for trunk/src/VBox
- Timestamp:
- Jul 26, 2012 5:33:01 PM (12 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
-
VMMAll/CPUMAllRegs.cpp (modified) (1 diff)
-
VMMAll/SELMAll.cpp (modified) (1 diff)
-
VMMR3/CPUM.cpp (modified) (8 diffs)
-
VMMR3/DBGFDisas.cpp (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r42407 r42420 2531 2531 } 2532 2532 2533 /**2534 * Checks if the hidden selector registers are valid for the specified CPU.2535 *2536 * @returns true if they are.2537 * @returns false if not.2538 * @param pVCpu Pointer to the VM.2539 */2540 VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu)2541 {2542 bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID);2543 Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));2544 Assert(!pVCpu->cpum.s.fRemEntered);2545 return fRc;2546 }2547 2548 2549 2533 2550 2534 /** -
trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r42407 r42420 104 104 { 105 105 RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff; 106 if (CPUM AreHiddenSelRegsValid(pVCpu))106 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg)) 107 107 uFlat += pSReg->u64Base; 108 108 else 109 uFlat += ( (RTGCUINTPTR)pSReg->Sel << 4);109 uFlat += (RTGCUINTPTR)pSReg->Sel << 4; 110 110 return (RTGCPTR)uFlat; 111 111 } -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r42410 r42420 83 83 #define CPUM_SAVED_STATE_VERSION_VER1_6 6 84 84 85 #define CPUM_WITH_CHANGED_CPUMCTX 85 86 /** 87 * This was used in the saved state up to the early life of version 14. 88 * 89 * It indicates that we may have some out-of-sync hidden segement registers. 90 * It is only relevant for raw-mode. 91 */ 92 #define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12) 93 86 94 87 95 /******************************************************************************* … … 2498 2506 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID; 2499 2507 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel; 2500 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;2501 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;2502 2508 } 2503 2509 else … … 2509 2515 } 2510 2516 2511 /** @todo fix this. We can get most of the details from SELM after restore is 2512 * done. */ 2513 pVCpu->cpum.s.Guest.ldtr.fFlags = 0; 2514 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0; 2515 pVCpu->cpum.s.Guest.tr.fFlags = 0; 2516 pVCpu->cpum.s.Guest.tr.ValidSel = 0; 2517 /* This might not be 104% correct, but I think it's close 2518 enough for all practical purposes... (REM always loaded 2519 LDTR registers.) */ 2520 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID; 2521 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel; 2517 2522 } 2518 2523 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID; 2524 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel; 2519 2525 } 2520 2526 } 2521 2527 2522 /* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for 2523 raw-mode guest, so we have to do it ourselves. */ 2524 /** @todo eliminate CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */ 2525 if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2 2526 && !HWACCMIsEnabled(pVM)) 2528 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */ 2529 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2 2530 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM) 2527 2531 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++) 2528 pVM->aCpus[iCpu].cpum.s.fChanged |= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;2532 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; 2529 2533 2530 2534 /* … … 3997 4001 && pCtx->eflags.Bits.u1VM == 0) 3998 4002 { 3999 if ( CPUMAreHiddenSelRegsValid(pVCpu))4003 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs)) 4000 4004 { 4001 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long; 4002 State.GCPtrSegBase = pCtx->cs.u64Base; 4003 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base; 4004 State.cbSegLimit = pCtx->cs.u32Limit; 4005 enmDisCpuMode = (State.f64Bits) 4006 ? DISCPUMODE_64BIT 4007 : pCtx->cs.Attr.n.u1DefBig 4008 ? DISCPUMODE_32BIT 4009 : DISCPUMODE_16BIT; 4005 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs); 4006 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs)) 4007 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR; 4010 4008 } 4011 else 4012 { 4013 DBGFSELINFO SelInfo; 4014 4015 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs.Sel, &SelInfo); 4016 if (RT_FAILURE(rc)) 4017 { 4018 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs.Sel, GCPtrPC, rc)); 4019 return rc; 4020 } 4021 4022 /* 4023 * Validate the selector. 4024 */ 4025 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss.Sel); 4026 if (RT_FAILURE(rc)) 4027 { 4028 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs.Sel, GCPtrPC, rc)); 4029 return rc; 4030 } 4031 State.GCPtrSegBase = SelInfo.GCPtrBase; 4032 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase; 4033 State.cbSegLimit = SelInfo.cbLimit; 4034 enmDisCpuMode = SelInfo.u.Raw.Gen.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; 4035 } 4009 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long; 4010 State.GCPtrSegBase = pCtx->cs.u64Base; 4011 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base; 4012 State.cbSegLimit = pCtx->cs.u32Limit; 4013 enmDisCpuMode = (State.f64Bits) 4014 ? DISCPUMODE_64BIT 4015 : pCtx->cs.Attr.n.u1DefBig 4016 ? DISCPUMODE_32BIT 4017 : DISCPUMODE_16BIT; 4036 4018 } 4037 4019 else … … 4205 4187 PATMRawEnter(pVM, pCtxCore); 4206 4188 } 4207 4208 /*4209 * Invalidate the hidden registers.4210 */4211 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;4212 4189 4213 4190 /* … … 4330 4307 4331 4308 /* 4332 * Get and reset the flags , leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.4309 * Get and reset the flags. 4333 4310 */ 4334 4311 uint32_t fFlags = pVCpu->cpum.s.fChanged; 4335 pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */4312 pVCpu->cpum.s.fChanged = 0; 4336 4313 4337 4314 /** @todo change the switcher to use the fChanged flags. */ … … 4348 4325 4349 4326 /** 4350 * Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.4327 * Leaves REM. 4351 4328 * 4352 4329 * @param pVCpu Pointer to the VMCPU. … … 4359 4336 Assert(pVCpu->cpum.s.fRemEntered); 4360 4337 4361 if (fNoOutOfSyncSels)4362 pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;4363 else4364 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;4365 4366 4338 pVCpu->cpum.s.fRemEntered = false; 4367 4339 } -
trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp
r41965 r42420 340 340 VMCPU_ASSERT_EMT(pVCpu); 341 341 RTGCPTR GCPtr = *pGCPtr; 342 int rc; 342 343 343 344 /* … … 345 346 */ 346 347 PCCPUMCTXCORE pCtxCore = NULL; 347 PCPUMSELREGHID pHiddenSel = NULL; 348 int rc; 349 if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_CURRENT_HYPER)) 350 { 351 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST) 352 pCtxCore = CPUMGetGuestCtxCore(pVCpu); 348 PCCPUMSELREG pSRegCS = NULL; 349 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST) 350 { 351 pCtxCore = CPUMGetGuestCtxCore(pVCpu); 352 Sel = pCtxCore->cs.Sel; 353 pSRegCS = &pCtxCore->cs; 354 GCPtr = pCtxCore->rip; 355 } 356 else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER) 357 { 358 pCtxCore = CPUMGetHyperCtxCore(pVCpu); 359 Sel = pCtxCore->cs.Sel; 360 GCPtr = pCtxCore->rip; 361 } 362 /* 363 * Check if the selector matches the guest CS, use the hidden 364 * registers from that if they are valid. Saves time and effort. 365 */ 366 else 367 { 368 pCtxCore = CPUMGetGuestCtxCore(pVCpu); 369 if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT) 370 pSRegCS = &pCtxCore->cs; 353 371 else 354 pCtxCore = CPUMGetHyperCtxCore(pVCpu); 355 Sel = pCtxCore->cs.Sel; 356 pHiddenSel = (PCPUMSELREGHID)&pCtxCore->cs; 357 GCPtr = pCtxCore->rip; 372 pCtxCore = NULL; 358 373 } 359 374 360 375 /* 361 376 * Read the selector info - assume no stale selectors and nasty stuff like that. 362 * Since the selector flags in the CPUMCTX structures aren't up to date unless 363 * we recently visited REM, we'll not search for the selector there. 377 * 378 * Note! We CANNOT load invalid hidden selector registers since that would 379 * mean that log/debug statements or the debug will influence the 380 * guest state and make things behave differently. 364 381 */ 365 382 DBGFSELINFO SelInfo; … … 367 384 bool fRealModeAddress = false; 368 385 369 if ( pHiddenSel 370 && ( (fFlags & DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID) 371 || CPUMAreHiddenSelRegsValid(pVCpu))) 386 if ( pSRegCS 387 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS)) 372 388 { 373 389 SelInfo.Sel = Sel; 374 390 SelInfo.SelGate = 0; 375 SelInfo.GCPtrBase = p HiddenSel->u64Base;376 SelInfo.cbLimit = p HiddenSel->u32Limit;391 SelInfo.GCPtrBase = pSRegCS->u64Base; 392 SelInfo.cbLimit = pSRegCS->u32Limit; 377 393 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode) 378 394 ? DBGFSELINFO_FLAGS_LONG_MODE 379 : enmMode != PGMMODE_REAL && (!pCtxCore || !pCtxCore->eflags.Bits.u1VM)395 : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM 380 396 ? DBGFSELINFO_FLAGS_PROT_MODE 381 397 : DBGFSELINFO_FLAGS_REAL_MODE; … … 385 401 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff; 386 402 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf; 387 SelInfo.u.Raw.Gen.u1Present = p HiddenSel->Attr.n.u1Present;388 SelInfo.u.Raw.Gen.u1Granularity = p HiddenSel->Attr.n.u1Granularity;;389 SelInfo.u.Raw.Gen.u1DefBig = p HiddenSel->Attr.n.u1DefBig;390 SelInfo.u.Raw.Gen.u1Long = p HiddenSel->Attr.n.u1Long;391 SelInfo.u.Raw.Gen.u1DescType = p HiddenSel->Attr.n.u1DescType;392 SelInfo.u.Raw.Gen.u4Type = p HiddenSel->Attr.n.u4Type;403 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present; 404 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;; 405 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig; 406 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long; 407 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType; 408 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type; 393 409 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE); 394 410 } … … 409 425 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf; 410 426 411 if ( (fFlags & DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID) 412 || CPUMAreHiddenSelRegsValid(pVCpu)) 413 { /* Assume the current CS defines the execution mode. */ 414 pCtxCore = CPUMGetGuestCtxCore(pVCpu); 415 pHiddenSel = (CPUMSELREGHID *)&pCtxCore->cs; 416 417 SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present; 418 SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;; 419 SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig; 420 SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long; 421 SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType; 422 SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type; 427 pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs; 428 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS)) 429 { 430 /* Assume the current CS defines the execution mode. */ 431 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present; 432 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;; 433 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig; 434 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long; 435 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType; 436 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type; 423 437 } 424 438 else 425 439 { 440 pSRegCS = NULL; 426 441 SelInfo.u.Raw.Gen.u1Present = 1; 427 442 SelInfo.u.Raw.Gen.u1Granularity = 1;
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