Changeset 42622 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Aug 6, 2012 1:43:53 PM (12 years ago)

Author:

vboxsync

Message:

VMM/HWVMXR0: Flush VPIDs on 32-bit hosts.

File:

• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -2262 +2262 @@
 
     /* First sync back EIP, ESP, and EFLAGS. */
-    rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP,              &val);
+    rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP,            &val);
     AssertRC(rc);
     pCtx->rip               = val;
-    rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP,              &val);
+    rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP,            &val);
     AssertRC(rc);
     pCtx->rsp               = val;
@@ -2331 +2331 @@
 
     /* System MSRs */
-    VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS,    &val);
+    VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS,      &val);
     pCtx->SysEnter.cs       = val;
     VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP,     &val);
@@ -2341 +2341 @@
     VMX_READ_SELREG(LDTR, ldtr);
 
-    VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT,     &val);
+    VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT,       &val);
     pCtx->gdtr.cbGdt        = val;
     VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE,        &val);
     pCtx->gdtr.pGdt         = val;
 
-    VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT,     &val);
+    VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT,       &val);
     pCtx->idtr.cbIdt        = val;
     VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE,        &val);
@@ -2390 +2390 @@
                 pCtx->msrSFMASK = pMsr->u64Value;
                 break;
-
             /* The KERNEL_GS_BASE MSR doesn't work reliably with auto load/store. See @bugref{6208}  */
 #if 0
@@ -2400 +2399 @@
                 CPUMSetGuestMsr(pVCpu, MSR_K8_TSC_AUX, pMsr->u64Value);
                 break;
-
             case MSR_K6_EFER:
                 /* EFER can't be changed without causing a VM-exit. */
@@ -4990 +4988 @@
 static void hmR0VmxFlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr)
 {
-#if HC_ARCH_BITS == 32
-    /*
-     * If we get a flush in 64-bit guest mode, then force a full TLB flush. invvpid probably takes only 32-bit addresses.
-     */
-    if (   CPUMIsGuestInLongMode(pVCpu)
-        && !VMX_IS_64BIT_HOST_MODE())
-    {
-        VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
+    uint64_t descriptor[2];
+
+    Assert(pVM->hwaccm.s.vmx.fVPID);
+    if (enmFlush == VMX_FLUSH_VPID_ALL_CONTEXTS)
+    {
+        descriptor[0] = 0;
+        descriptor[1] = 0;
     }
     else
-#endif
-    {
-        uint64_t descriptor[2];
-
-        Assert(pVM->hwaccm.s.vmx.fVPID);
-        if (enmFlush == VMX_FLUSH_VPID_ALL_CONTEXTS)
-        {
-            descriptor[0] = 0;
-            descriptor[1] = 0;
-        }
-        else
-        {
-            AssertPtr(pVCpu);
-            Assert(pVCpu->hwaccm.s.uCurrentASID != 0);
-            descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
-            descriptor[1] = GCPtr;
-        }
-        int rc = VMXR0InvVPID(enmFlush, &descriptor[0]); NOREF(rc);
-        AssertMsg(rc == VINF_SUCCESS,
-                  ("VMXR0InvVPID %x %x %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hwaccm.s.uCurrentASID : 0, GCPtr, rc));
-    }
+    {
+        AssertPtr(pVCpu);
+        Assert(pVCpu->hwaccm.s.uCurrentASID != 0);
+        descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
+        descriptor[1] = GCPtr;
+    }
+    int rc = VMXR0InvVPID(enmFlush, &descriptor[0]); NOREF(rc);
+    AssertMsg(rc == VINF_SUCCESS,
+              ("VMXR0InvVPID %x %x %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hwaccm.s.uCurrentASID : 0, GCPtr, rc));
 }