Changeset 42663 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Aug 7, 2012 2:16:30 PM (12 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/src/VBox/Devices/PC/DevHPET.cpp
r42635 r42663 46 46 47 47 /** Base address for MMIO. */ 48 /* On ICH9, it is 0xFED0x000 where 'x' is 0-3, default 0. We do not support 49 * relocation as the platform firmware is responsible for configuring the 50 * HPET base address and the OS isn't expected to move it. 51 * WARNING: This has to match the ACPI tables! */ 48 52 #define HPET_BASE 0xfed00000 53 54 /* HPET reserves a 1K range. */ 55 #define HPET_BAR_SIZE 0x1000 49 56 50 57 /** The number of timers for PIIX4 / PIIX3. */ … … 515 522 { 516 523 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE); 524 uint64_t u64Mask = HPET_TN_CFG_WRITE_MASK; 525 517 526 Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue)); 518 uint64_t const iOldValue = (uint32_t)pHpetTimer->u64Config;519 520 uint64_t u64Mask = HPET_TN_CFG_WRITE_MASK;521 527 if (pHpetTimer->u64Config & HPET_TN_PERIODIC_CAP) 522 528 u64Mask |= HPET_TN_PERIODIC; … … 542 548 543 549 /* We only care about lower 32-bits so far */ 544 pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, iOldValue, u64Mask);550 pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, pHpetTimer->u64Config, u64Mask); 545 551 DEVHPET_UNLOCK(pThis); 546 552 break; 547 553 } 548 554 549 case HPET_TN_CFG + 4: /* Interrupt capabilities */555 case HPET_TN_CFG + 4: /* Interrupt capabilities - read only. */ 550 556 { 551 557 Log(("write HPET_TN_CFG + 4, useless\n")); … … 1432 1438 * addresses and sizes. 1433 1439 */ 1434 rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, 0x1000, pThis,1440 rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, HPET_BAR_SIZE, pThis, 1435 1441 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU, 1436 1442 hpetMMIOWrite, hpetMMIORead, "HPET Memory"); … … 1439 1445 if (fRCEnabled) 1440 1446 { 1441 rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, 0x1000, NIL_RTRCPTR /*pvUser*/, "hpetMMIOWrite", "hpetMMIORead");1447 rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, HPET_BAR_SIZE, NIL_RTRCPTR /*pvUser*/, "hpetMMIOWrite", "hpetMMIORead"); 1442 1448 AssertRCReturn(rc, rc); 1443 1449 … … 1448 1454 if (fR0Enabled) 1449 1455 { 1450 rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, 0x1000, NIL_RTR0PTR /*pvUser*/,1456 rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, HPET_BAR_SIZE, NIL_RTR0PTR /*pvUser*/, 1451 1457 "hpetMMIOWrite", "hpetMMIORead"); 1452 1458 AssertRCReturn(rc, rc);
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