- Timestamp:
- Nov 2, 2012 1:24:21 PM (12 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r43771 r43798 580 580 /** @todo make sure they don't conflict with the above requirements. */ 581 581 val &= pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1; 582 pVCpu->hm.s.vmx. proc_ctls = val;582 pVCpu->hm.s.vmx.u64ProcCtls = val; 583 583 584 584 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, val); … … 612 612 /** @todo make sure they don't conflict with the above requirements. */ 613 613 val &= pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1; 614 pVCpu->hm.s.vmx. proc_ctls2 = val;614 pVCpu->hm.s.vmx.u64ProcCtls2 = val; 615 615 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2, val); 616 616 AssertRC(rc); … … 676 676 hmR0VmxSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true); 677 677 hmR0VmxSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true); 678 if (pVCpu->hm.s.vmx. proc_ctls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)678 if (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) 679 679 hmR0VmxSetMSRPermission(pVCpu, MSR_K8_TSC_AUX, true, true); 680 680 } … … 1040 1040 if (!(pCtx->eflags.u32 & X86_EFL_IF)) 1041 1041 { 1042 if (!(pVCpu->hm.s.vmx. proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))1042 if (!(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)) 1043 1043 { 1044 1044 LogFlow(("Enable irq window exit!\n")); 1045 pVCpu->hm.s.vmx. proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;1046 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);1045 pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT; 1046 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 1047 1047 AssertRC(rc); 1048 1048 } … … 1448 1448 # endif 1449 1449 1450 if (pVCpu->hm.s.vmx. proc_ctls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)1450 if (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) 1451 1451 { 1452 1452 pMsr->u32IndexMSR = MSR_K8_TSC_AUX; … … 1912 1912 { 1913 1913 /* Disable CR3 read/write monitoring as we don't need it for EPT. */ 1914 pVCpu->hm.s.vmx. proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT1914 pVCpu->hm.s.vmx.u64ProcCtls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT 1915 1915 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT); 1916 1916 } … … 1918 1918 { 1919 1919 /* Reenable CR3 read/write monitoring as our identity mapped page table is active. */ 1920 pVCpu->hm.s.vmx. proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT1920 pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT 1921 1921 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT; 1922 1922 } 1923 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);1923 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 1924 1924 AssertRC(rc); 1925 1925 } … … 2037 2037 if (DBGFIsStepping(pVCpu)) 2038 2038 { 2039 pVCpu->hm.s.vmx. proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG;2040 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);2039 pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG; 2040 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 2041 2041 AssertRC(rc); 2042 2042 } … … 2134 2134 2135 2135 /* Disable DRx move intercepts. */ 2136 pVCpu->hm.s.vmx. proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;2137 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);2136 pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; 2137 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 2138 2138 AssertRC(rc); 2139 2139 … … 2231 2231 } 2232 2232 2233 if ( pVCpu->hm.s.vmx. proc_ctls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP2233 if ( pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP 2234 2234 && (u32GstExtFeatures & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)) 2235 2235 { … … 2278 2278 AssertRC(rc); 2279 2279 2280 pVCpu->hm.s.vmx. proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;2281 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);2280 pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT; 2281 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 2282 2282 AssertRC(rc); 2283 2283 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset); … … 2290 2290 TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVCpu->hm.s.vmx.u64TSCOffset, 2291 2291 TMCpuTickGet(pVCpu))); 2292 pVCpu->hm.s.vmx. proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;2293 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);2292 pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT; 2293 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 2294 2294 AssertRC(rc); 2295 2295 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow); … … 2298 2298 else 2299 2299 { 2300 pVCpu->hm.s.vmx. proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;2301 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);2300 pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT; 2301 rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 2302 2302 AssertRC(rc); 2303 2303 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept); … … 3226 3226 * RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}. 3227 3227 */ 3228 if ( (pVCpu->hm.s.vmx. proc_ctls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)3229 && !(pVCpu->hm.s.vmx. proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT))3228 if ( (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) 3229 && !(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)) 3230 3230 { 3231 3231 pVCpu->hm.s.u64HostTSCAux = ASMRdMsr(MSR_K8_TSC_AUX); … … 3246 3246 3247 3247 /* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */ 3248 if (!(pVCpu->hm.s.vmx. proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT))3248 if (!(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)) 3249 3249 { 3250 3250 #ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 3251 3251 /* Restore host's TSC_AUX. */ 3252 if (pVCpu->hm.s.vmx. proc_ctls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)3252 if (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP) 3253 3253 ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTSCAux); 3254 3254 #endif … … 4134 4134 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, 4135 4135 VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF)); 4136 pVCpu->hm.s.vmx. proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;4137 rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);4136 pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT; 4137 rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 4138 4138 AssertRC(rc2); 4139 4139 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIrqWindow); … … 4389 4389 { 4390 4390 /* Disable DRx move intercepts. */ 4391 pVCpu->hm.s.vmx. proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;4392 rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);4391 pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; 4392 rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 4393 4393 AssertRC(rc2); 4394 4394 … … 4755 4755 case VMX_EXIT_MTF: /* 37 Exit due to Monitor Trap Flag. */ 4756 4756 LogFlow(("VMX_EXIT_MTF at %RGv\n", (RTGCPTR)pCtx->rip)); 4757 pVCpu->hm.s.vmx. proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG;4758 rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);4757 pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG; 4758 rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 4759 4759 AssertRC(rc2); 4760 4760 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf); … … 4977 4977 { 4978 4978 CPUMR0LoadHostDebugState(pVM, pVCpu); 4979 Assert(pVCpu->hm.s.vmx. proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);4979 Assert(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT); 4980 4980 } 4981 4981 else … … 4990 4990 4991 4991 /* Enable DRx move intercepts again. */ 4992 pVCpu->hm.s.vmx. proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;4993 int rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx. proc_ctls);4992 pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; 4993 int rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls); 4994 4994 AssertRC(rc); 4995 4995 … … 4998 4998 } 4999 4999 else 5000 Assert(pVCpu->hm.s.vmx. proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);5000 Assert(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT); 5001 5001 5002 5002 /* -
trunk/src/VBox/VMM/include/HMInternal.h
r43747 r43798 542 542 543 543 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */ 544 uint64_t proc_ctls;544 uint64_t u64ProcCtls; 545 545 /** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */ 546 uint64_t proc_ctls2;546 uint64_t u64ProcCtls2; 547 547 /** Current VMX_VMCS_CTRL_EXIT_CONTROLS. */ 548 548 uint64_t u64ExitCtls; -
trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp
r43511 r43798 401 401 CHECK_MEMBER_ALIGNMENT(HMCPU, StatEntry, 8); 402 402 CHECK_MEMBER_ALIGNMENT(HMCPU, vmx.HCPhysVMCS, sizeof(RTHCPHYS)); 403 CHECK_MEMBER_ALIGNMENT(HMCPU, vmx. proc_ctls, 8);403 CHECK_MEMBER_ALIGNMENT(HMCPU, vmx.u64ProcCtls, 8); 404 404 CHECK_MEMBER_ALIGNMENT(HMCPU, Event.intInfo, 8); 405 405
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