Changeset 43803 in vbox for trunk/include/VBox/vmm

Timestamp:

Nov 5, 2012 1:50:57 PM (12 years ago)

Author:

vboxsync

Message:

VMM/VMMR0: bits.

File:

• trunk/include/VBox/vmm/hm_vmx.h (modified) (1 diff)

trunk/include/VBox/vmm/hm_vmx.h

@@ -659 +659 @@
 
 
-/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
- * @{
- */
-#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY                                    RT_BIT_64(0)
-#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY                                    RT_BIT_64(1)
-#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY                                   RT_BIT_64(2)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS                                   RT_BIT_64(3)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS                                   RT_BIT_64(4)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS                                   RT_BIT_64(5)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS                                   RT_BIT_64(6)
-#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS                                   RT_BIT_64(7)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_UC                                        RT_BIT_64(8)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WC                                        RT_BIT_64(9)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WT                                        RT_BIT_64(12)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WP                                        RT_BIT_64(13)
-#define MSR_IA32_VMX_EPT_CAPS_EMT_WB                                        RT_BIT_64(14)
-#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS                                    RT_BIT_64(16)
-#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS                                    RT_BIT_64(17)
-#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS                                    RT_BIT_64(18)
-#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS                                    RT_BIT_64(19)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT                                        RT_BIT_64(20)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT                    RT_BIT_64(25)
-#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS                      RT_BIT_64(26)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID                                       RT_BIT_64(32)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR                       RT_BIT_64(40)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT                   RT_BIT_64(41)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS                     RT_BIT_64(42)
-#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS    RT_BIT_64(43)
+/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
+ * @{
+ */
+#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY                                RT_BIT_64(0)
+#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY                                RT_BIT_64(1)
+#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY                               RT_BIT_64(2)
+#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS                               RT_BIT_64(3)
+#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS                               RT_BIT_64(4)
+#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS                               RT_BIT_64(5)
+#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS                               RT_BIT_64(6)
+#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS                               RT_BIT_64(7)
+#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC                                    RT_BIT_64(8)
+#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC                                    RT_BIT_64(9)
+#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT                                    RT_BIT_64(12)
+#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP                                    RT_BIT_64(13)
+#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB                                    RT_BIT_64(14)
+#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS                                RT_BIT_64(16)
+#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS                                RT_BIT_64(17)
+#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS                                RT_BIT_64(18)
+#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS                                RT_BIT_64(19)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT                                    RT_BIT_64(20)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT                     RT_BIT_64(25)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS                       RT_BIT_64(26)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID                                   RT_BIT_64(32)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR                        RT_BIT_64(40)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT                    RT_BIT_64(41)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS                      RT_BIT_64(42)
+#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS     RT_BIT_64(43)
 
 /** @} */