VirtualBox

Changeset 43930 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Nov 21, 2012 3:36:39 PM (12 years ago)
Author:
vboxsync
Message:

VMM/VMMR0: Camel case.

Location:
trunk/src/VBox/VMM/VMMR0
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMR0A.asm

    r43737 r43930  
    280280; */
    281281ALIGNCODE(16)
    282 BEGINPROC VMXWriteVMCS64
     282BEGINPROC VMXWriteVmcs64
    283283%ifdef RT_ARCH_AMD64
    284284 %ifdef ASM_CALL64_GCC
    … …  
    335335BITS 32
    336336%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
    337 ENDPROC VMXWriteVMCS64
     337ENDPROC VMXWriteVmcs64
    338338
    339339
    … …  
    345345; * @param   pData           Ptr to store VM field value
    346346; */
    347 ;DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
    348 ALIGNCODE(16)
    349 BEGINPROC VMXReadVMCS64
     347;DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
     348ALIGNCODE(16)
     349BEGINPROC VMXReadVmcs64
    350350%ifdef RT_ARCH_AMD64
    351351 %ifdef ASM_CALL64_GCC
    … …  
    402402BITS 32
    403403%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
    404 ENDPROC VMXReadVMCS64
     404ENDPROC VMXReadVmcs64
    405405
    406406
    … …  
    412412; * @param   pu32Data        Ptr to store VM field value
    413413; */
    414 ;DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pu32Data);
    415 ALIGNCODE(16)
    416 BEGINPROC VMXReadVMCS32
     414;DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pu32Data);
     415ALIGNCODE(16)
     416BEGINPROC VMXReadVmcs32
    417417%ifdef RT_ARCH_AMD64
    418418 %ifdef ASM_CALL64_GCC
    … …  
    467467BITS 32
    468468%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
    469 ENDPROC VMXReadVMCS32
     469ENDPROC VMXReadVmcs32
    470470
    471471
    … …  
    477477; * @param   u32Data         Ptr to store VM field value
    478478; */
    479 ;DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Data);
    480 ALIGNCODE(16)
    481 BEGINPROC VMXWriteVMCS32
     479;DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Data);
     480ALIGNCODE(16)
     481BEGINPROC VMXWriteVmcs32
    482482%ifdef RT_ARCH_AMD64
    483483 %ifdef ASM_CALL64_GCC
    … …  
    531531BITS 32
    532532%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
    533 ENDPROC VMXWriteVMCS32
     533ENDPROC VMXWriteVmcs32
    534534
    535535

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r43849 r43930  
    102102        RTCCUINTREG instrError;
    103103
    104         VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
     104        VMXReadVmcs(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
    105105        pVCpu->hm.s.vmx.lasterror.ulInstrError = instrError;
    106106    }
    … …  
    528528        val &= pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
    529529
    530         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, val);
     530        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, val);
    531531        AssertRC(rc);
    532532
    … …  
    582582        pVCpu->hm.s.vmx.u64ProcCtls = val;
    583583
    584         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, val);
     584        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, val);
    585585        AssertRC(rc);
    586586
    … …  
    613613            val &= pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
    614614            pVCpu->hm.s.vmx.u64ProcCtls2 = val;
    615             rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2, val);
     615            rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2, val);
    616616            AssertRC(rc);
    617617        }
    … …  
    621621         * Set required bits to one and zero according to the MSR capabilities.
    622622         */
    623         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
     623        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
    624624        AssertRC(rc);
    625625
    … …  
    641641         * Don't filter page faults, all of them should cause a world switch.
    642642         */
    643         rc  = VMXWriteVMCS(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
     643        rc  = VMXWriteVmcs(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
    644644        AssertRC(rc);
    645         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
     645        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
    646646        AssertRC(rc);
    647647
    648         rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
     648        rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
    649649        AssertRC(rc);
    650         rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
     650        rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
    651651        AssertRC(rc);
    652         rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
     652        rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
    653653        AssertRC(rc);
    654654
    … …  
    660660            Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
    661661
    662             rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
     662            rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
    663663            AssertRC(rc);
    664664
    … …  
    685685         */
    686686        Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
    687         rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
     687        rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
    688688        AssertRC(rc);
    689         rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
     689        rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
    690690        AssertRC(rc);
    691691        Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
    692         rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL,  pVCpu->hm.s.vmx.HCPhysHostMsr);
     692        rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL,  pVCpu->hm.s.vmx.HCPhysHostMsr);
    693693        AssertRC(rc);
    694694#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
    695695
    696         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
     696        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
    697697        AssertRC(rc);
    698         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
     698        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
    699699        AssertRC(rc);
    700         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
     700        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
    701701        AssertRC(rc);
    702702
    … …  
    705705            Assert(pVM->hm.s.vmx.hMemObjApicAccess);
    706706            /* Optional */
    707             rc  = VMXWriteVMCS(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
    708             rc |= VMXWriteVMCS64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVAPIC);
     707            rc  = VMXWriteVmcs(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
     708            rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVAPIC);
    709709
    710710            if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
    711                 rc |= VMXWriteVMCS64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
     711                rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
    712712
    713713            AssertRC(rc);
    … …  
    715715
    716716        /* Set link pointer to -1. Not currently used. */
    717         rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
     717        rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
    718718        AssertRC(rc);
    719719
    … …  
    730730        PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
    731731
    732         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RIP);
    733         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RSP);
    734         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
    735         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
    736         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
    737         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_CR0);
    738         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
    739         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_CR4);
    740         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_DR7);
    741         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
    742         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
    743         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
    744         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
    745         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_GDTR_BASE);
    746         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
    747         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_IDTR_BASE);
     732        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_RIP);
     733        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_RSP);
     734        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_RFLAGS);
     735        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
     736        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
     737        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_CR0);
     738        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
     739        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_CR4);
     740        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_DR7);
     741        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
     742        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
     743        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
     744        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
     745        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_GDTR_BASE);
     746        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
     747        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_IDTR_BASE);
    748748
    749749        VMX_SETUP_SELREG(ES,   pCache);
    … …  
    759759         * Status code VMCS reads.
    760760         */
    761         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
    762         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
    763         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
    764         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
    765         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
    766         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
    767         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
    768         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
    769         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
     761        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_REASON);
     762        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
     763        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
     764        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
     765        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
     766        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
     767        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
     768        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_IDT_INFO);
     769        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
    770770
    771771        if (pVM->hm.s.fNestedPaging)
    772772        {
    773             VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_CR3);
    774             VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL);
     773            VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_CR3);
     774            VMXSetupCachedReadVmcs(pCache, VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL);
    775775            pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
    776776        }
    … …  
    974974     * Set event injection state.
    975975     */
    976     rc  = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
    977     rc |= VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
    978     rc |= VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
     976    rc  = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
     977    rc |= VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
     978    rc |= VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
    979979
    980980    AssertRC(rc);
    … …  
    10441044                    LogFlow(("Enable irq window exit!\n"));
    10451045                    pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
    1046                     rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     1046                    rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    10471047                    AssertRC(rc);
    10481048                }
    … …  
    12261226         * Control registers.
    12271227         */
    1228         rc  = VMXWriteVMCS(VMX_VMCS_HOST_CR0,           ASMGetCR0());
     1228        rc  = VMXWriteVmcs(VMX_VMCS_HOST_CR0,           ASMGetCR0());
    12291229        Log2(("VMX_VMCS_HOST_CR0 %08x\n",               ASMGetCR0()));
    12301230#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
    … …  
    12321232        {
    12331233            cr3 = hmR0Get64bitCR3();
    1234             rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3,     cr3);
     1234            rc |= VMXWriteVmcs64(VMX_VMCS_HOST_CR3,     cr3);
    12351235        }
    12361236        else
    … …  
    12381238        {
    12391239            cr3 = ASMGetCR3();
    1240             rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3,       cr3);
     1240            rc |= VMXWriteVmcs(VMX_VMCS_HOST_CR3,       cr3);
    12411241        }
    12421242        Log2(("VMX_VMCS_HOST_CR3 %08RX64\n",            cr3));
    1243         rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4,           ASMGetCR4());
     1243        rc |= VMXWriteVmcs(VMX_VMCS_HOST_CR4,           ASMGetCR4());
    12441244        Log2(("VMX_VMCS_HOST_CR4 %08x\n",               ASMGetCR4()));
    12451245        AssertRC(rc);
    … …  
    12661266        Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
    12671267        Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
    1268         rc  = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS,          cs);
     1268        rc  = VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_CS,          cs);
    12691269        /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
    1270         rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS,          0);
    1271         rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES,          0);
     1270        rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_DS,          0);
     1271        rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_ES,          0);
    12721272#if HC_ARCH_BITS == 32
    12731273        if (!VMX_IS_64BIT_HOST_MODE())
    12741274        {
    1275             rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS,      0);
    1276             rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS,      0);
    1277         }
    1278 #endif
    1279         rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS,          ss);
     1275            rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_FS,      0);
     1276            rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_GS,      0);
     1277        }
     1278#endif
     1279        rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_SS,          ss);
    12801280        SelTR = ASMGetTR();
    1281         rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR,          SelTR);
     1281        rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_TR,          SelTR);
    12821282        AssertRC(rc);
    12831283        Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
    … …  
    12971297            X86XDTR64 gdtr64, idtr64;
    12981298            hmR0Get64bitGdtrAndIdtr(&gdtr64, &idtr64);
    1299             rc  = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
    1300             rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, idtr64.uAddr);
     1299            rc  = VMXWriteVmcs64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
     1300            rc |= VMXWriteVmcs64(VMX_VMCS_HOST_IDTR_BASE, idtr64.uAddr);
    13011301            AssertRC(rc);
    13021302            Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
    … …  
    13091309        {
    13101310            ASMGetGDTR(&gdtr);
    1311             rc  = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
     1311            rc  = VMXWriteVmcs(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
    13121312            ASMGetIDTR(&idtr);
    1313             rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
     1313            rc |= VMXWriteVmcs(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
    13141314            AssertRC(rc);
    13151315            Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
    … …  
    13311331        {
    13321332            uint64_t trBase64 = X86DESC64_BASE((PX86DESC64)pDesc);
    1333             rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
     1333            rc = VMXWriteVmcs64(VMX_VMCS_HOST_TR_BASE, trBase64);
    13341334            Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
    13351335            AssertRC(rc);
    … …  
    13431343            trBase = X86DESC_BASE(pDesc);
    13441344#endif
    1345             rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
     1345            rc = VMXWriteVmcs(VMX_VMCS_HOST_TR_BASE, trBase);
    13461346            AssertRC(rc);
    13471347            Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
    … …  
    13561356            Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
    13571357            Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
    1358             rc  = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE,         ASMRdMsr(MSR_K8_FS_BASE));
    1359             rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE,         ASMRdMsr(MSR_K8_GS_BASE));
     1358            rc  = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE,         ASMRdMsr(MSR_K8_FS_BASE));
     1359            rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE,         ASMRdMsr(MSR_K8_GS_BASE));
    13601360        }
    13611361#endif
    … …  
    13661366         */
    13671367        /** @todo expensive!! */
    1368         rc  = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS,         ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
     1368        rc  = VMXWriteVmcs(VMX_VMCS32_HOST_SYSENTER_CS,         ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
    13691369        Log2(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n",              ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
    13701370#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
    … …  
    13731373            Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n",         ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
    13741374            Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n",         ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
    1375             rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP,    ASMRdMsr(MSR_IA32_SYSENTER_ESP));
    1376             rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP,    ASMRdMsr(MSR_IA32_SYSENTER_EIP));
     1375            rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP,    ASMRdMsr(MSR_IA32_SYSENTER_ESP));
     1376            rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP,    ASMRdMsr(MSR_IA32_SYSENTER_EIP));
    13771377        }
    13781378        else
    13791379        {
    1380             rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
    1381             rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
     1380            rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_ESP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
     1381            rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_EIP,      ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
    13821382            Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n",         ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
    13831383            Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n",         ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
    13841384        }
    13851385#elif HC_ARCH_BITS == 32
    1386         rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP,          ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
    1387         rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP,          ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
     1386        rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_ESP,          ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
     1387        rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_EIP,          ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
    13881388        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n",             ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
    13891389        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n",             ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
    … …  
    13911391        Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n",             ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
    13921392        Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n",             ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
    1393             rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP,    ASMRdMsr(MSR_IA32_SYSENTER_ESP));
    1394         rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP,        ASMRdMsr(MSR_IA32_SYSENTER_EIP));
     1393            rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP,    ASMRdMsr(MSR_IA32_SYSENTER_ESP));
     1394        rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP,        ASMRdMsr(MSR_IA32_SYSENTER_EIP));
    13951395#endif
    13961396        AssertRC(rc);
    … …  
    14581458        /** @todo r=ramshankar: check IA32_VMX_MISC bits 27:25 for valid idxMsr
    14591459         *        range. */
    1460         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr);
     1460        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr);
    14611461        AssertRC(rc);
    14621462#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
    … …  
    14841484        AssertRCReturn(rc, rc);
    14851485
    1486         rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE0_FULL, aPdpes[0].u); AssertRCReturn(rc, rc);
    1487         rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE1_FULL, aPdpes[1].u); AssertRCReturn(rc, rc);
    1488         rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE2_FULL, aPdpes[2].u); AssertRCReturn(rc, rc);
    1489         rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE3_FULL, aPdpes[3].u); AssertRCReturn(rc, rc);
     1486        rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, aPdpes[0].u); AssertRCReturn(rc, rc);
     1487        rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, aPdpes[1].u); AssertRCReturn(rc, rc);
     1488        rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, aPdpes[2].u); AssertRCReturn(rc, rc);
     1489        rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, aPdpes[3].u); AssertRCReturn(rc, rc);
    14901490    }
    14911491    return VINF_SUCCESS;
    … …  
    15091509        int rc;
    15101510        X86PDPE aPdpes[4];
    1511         rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE0_FULL, &aPdpes[0].u); AssertRCReturn(rc, rc);
    1512         rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE1_FULL, &aPdpes[1].u); AssertRCReturn(rc, rc);
    1513         rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE2_FULL, &aPdpes[2].u); AssertRCReturn(rc, rc);
    1514         rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE3_FULL, &aPdpes[3].u); AssertRCReturn(rc, rc);
     1511        rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &aPdpes[0].u); AssertRCReturn(rc, rc);
     1512        rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &aPdpes[1].u); AssertRCReturn(rc, rc);
     1513        rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &aPdpes[2].u); AssertRCReturn(rc, rc);
     1514        rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &aPdpes[3].u); AssertRCReturn(rc, rc);
    15151515
    15161516        rc = PGMGstUpdatePaePdpes(pVCpu, &aPdpes[0]);
    … …  
    15971597    }
    15981598
    1599     int rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32TrapMask);
     1599    int rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32TrapMask);
    16001600    AssertRC(rc);
    16011601}
    … …  
    16211621     * Load EIP, ESP and EFLAGS.
    16221622     */
    1623     rc  = VMXWriteVMCS64(VMX_VMCS_GUEST_RIP, pCtx->rip);
    1624     rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_RSP, pCtx->rsp);
     1623    rc  = VMXWriteVmcs64(VMX_VMCS_GUEST_RIP, pCtx->rip);
     1624    rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_RSP, pCtx->rsp);
    16251625    AssertRC(rc);
    16261626
    … …  
    16431643        eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
    16441644    }
    1645     rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
     1645    rc = VMXWriteVmcs(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
    16461646    AssertRC(rc);
    16471647}
    … …  
    16831683     */
    16841684    val &= pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
    1685     rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_CONTROLS, val);
     1685    rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_CONTROLS, val);
    16861686    AssertRC(rc);
    16871687
    … …  
    17131713     * Don't acknowledge external interrupts on VM-exit.
    17141714     */
    1715     rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_CONTROLS, val);
     1715    rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_CONTROLS, val);
    17161716    AssertRC(rc);
    17171717
    … …  
    17821782        if (pCtx->ldtr.Sel == 0)
    17831783        {
    1784             rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR,         0);
    1785             rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT,         0);
    1786             rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_LDTR_BASE,          0); /* @todo removing "64" in the function should be the same. */
     1784            rc =  VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_LDTR,         0);
     1785            rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_LIMIT,         0);
     1786            rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_LDTR_BASE,          0); /* @todo removing "64" in the function should be the same. */
    17871787            /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
    1788             rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
     1788            rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
    17891789        }
    17901790        else
    17911791        {
    1792             rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR,         pCtx->ldtr.Sel);
    1793             rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT,         pCtx->ldtr.u32Limit);
    1794             rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_LDTR_BASE,          pCtx->ldtr.u64Base);    /* @todo removing "64" and it should be the same */
    1795             rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr.Attr.u);
     1792            rc =  VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_LDTR,         pCtx->ldtr.Sel);
     1793            rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_LIMIT,         pCtx->ldtr.u32Limit);
     1794            rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_LDTR_BASE,          pCtx->ldtr.u64Base);    /* @todo removing "64" and it should be the same */
     1795            rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr.Attr.u);
    17961796        }
    17971797        AssertRC(rc);
    … …  
    18161816            AssertRC(rc);
    18171817
    1818             rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR,         0);
    1819             rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT,         HM_VTX_TSS_SIZE);
    1820             rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_TR_BASE,          GCPhys /* phys = virt in this mode */);
     1818            rc =  VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_TR,         0);
     1819            rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_TR_LIMIT,         HM_VTX_TSS_SIZE);
     1820            rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_TR_BASE,          GCPhys /* phys = virt in this mode */);
    18211821
    18221822            X86DESCATTR attr;
    … …  
    18291829        else
    18301830        {
    1831             rc =  VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR,         pCtx->tr.Sel);
    1832             rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT,         pCtx->tr.u32Limit);
    1833             rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_TR_BASE,        pCtx->tr.u64Base);
     1831            rc =  VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_TR,         pCtx->tr.Sel);
     1832            rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_TR_LIMIT,         pCtx->tr.u32Limit);
     1833            rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_TR_BASE,        pCtx->tr.u64Base);
    18341834
    18351835            val = pCtx->tr.Attr.u;
    … …  
    18471847                      ("%#x\n", val));
    18481848        }
    1849         rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
     1849        rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
    18501850        AssertRC(rc);
    18511851    }
    … …  
    18561856    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
    18571857    {
    1858         rc  = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT,       pCtx->gdtr.cbGdt);
    1859         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_GDTR_BASE,      pCtx->gdtr.pGdt);
     1858        rc  = VMXWriteVmcs(VMX_VMCS32_GUEST_GDTR_LIMIT,       pCtx->gdtr.cbGdt);
     1859        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_GDTR_BASE,      pCtx->gdtr.pGdt);
    18601860        AssertRC(rc);
    18611861    }
    … …  
    18661866    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
    18671867    {
    1868         rc  = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT,       pCtx->idtr.cbIdt);
    1869         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_IDTR_BASE,      pCtx->idtr.pIdt);
     1868        rc  = VMXWriteVmcs(VMX_VMCS32_GUEST_IDTR_LIMIT,       pCtx->idtr.cbIdt);
     1869        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_IDTR_BASE,      pCtx->idtr.pIdt);
    18701870        AssertRC(rc);
    18711871    }
    … …  
    18761876    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_MSR)
    18771877    {
    1878         rc  = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS,    pCtx->SysEnter.cs);
    1879         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
    1880         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
     1878        rc  = VMXWriteVmcs(VMX_VMCS32_GUEST_SYSENTER_CS,    pCtx->SysEnter.cs);
     1879        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
     1880        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
    18811881        AssertRC(rc);
    18821882    }
    … …  
    18881888    {
    18891889        val = pCtx->cr0;
    1890         rc  = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW,   val);
     1890        rc  = VMXWriteVmcs(VMX_VMCS_CTRL_CR0_READ_SHADOW,   val);
    18911891        Log2(("Guest CR0-shadow %08x\n", val));
    18921892        if (CPUMIsGuestFPUStateActive(pVCpu) == false)
    … …  
    19211921                                                 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
    19221922            }
    1923             rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     1923            rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    19241924            AssertRC(rc);
    19251925        }
    … …  
    19331933        val &= ~(X86_CR0_CD|X86_CR0_NW);
    19341934
    1935         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_CR0,            val);
     1935        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_CR0,            val);
    19361936        Log2(("Guest CR0 %08x\n", val));
    19371937
    … …  
    19541954        pVCpu->hm.s.vmx.cr0_mask = val;
    19551955
    1956         rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
     1956        rc |= VMXWriteVmcs(VMX_VMCS_CTRL_CR0_MASK, val);
    19571957        Log2(("Guest CR0-mask %08x\n", val));
    19581958        AssertRC(rc);
    … …  
    19611961    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
    19621962    {
    1963         rc  = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW,   pCtx->cr4);
     1963        rc  = VMXWriteVmcs(VMX_VMCS_CTRL_CR4_READ_SHADOW,   pCtx->cr4);
    19641964        Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
    19651965        /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
    … …  
    20132013        }
    20142014
    2015         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_CR4,            val);
     2015        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_CR4,            val);
    20162016        Log2(("Guest CR4 %08x\n", val));
    20172017
    … …  
    20272027        pVCpu->hm.s.vmx.cr4_mask = val;
    20282028
    2029         rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
     2029        rc |= VMXWriteVmcs(VMX_VMCS_CTRL_CR4_MASK, val);
    20302030        Log2(("Guest CR4-mask %08x\n", val));
    20312031        AssertRC(rc);
    … …  
    20382038        {
    20392039            pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG;
    2040             rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     2040            rc = VMXWriteVmcs(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    20412041            AssertRC(rc);
    20422042        }
    … …  
    20552055                                             | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
    20562056
    2057             rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.GCPhysEPTP);
     2057            rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.GCPhysEPTP);
    20582058            AssertRC(rc);
    20592059
    … …  
    20882088
    20892089        /* Save our shadow CR3 register. */
    2090         rc = VMXWriteVMCS64(VMX_VMCS_GUEST_CR3, val);
     2090        rc = VMXWriteVmcs64(VMX_VMCS_GUEST_CR3, val);
    20912091        AssertRC(rc);
    20922092    }
    … …  
    21052105
    21062106        /* Resync DR7 */
    2107         rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
     2107        rc = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
    21082108        AssertRC(rc);
    21092109
    … …  
    21212121
    21222122            /* Override dr7 with the hypervisor value. */
    2123             rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, CPUMGetHyperDR7(pVCpu));
     2123            rc = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, CPUMGetHyperDR7(pVCpu));
    21242124            AssertRC(rc);
    21252125        }
    … …  
    21352135            /* Disable DRx move intercepts. */
    21362136            pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
    2137             rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     2137            rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    21382138            AssertRC(rc);
    21392139
    … …  
    21442144
    21452145        /* IA32_DEBUGCTL MSR. */
    2146         rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DEBUGCTL_FULL,    0);
     2146        rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL,    0);
    21472147        AssertRC(rc);
    21482148
    21492149        /** @todo do we really ever need this? */
    2150         rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS,  0);
     2150        rc |= VMXWriteVmcs(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS,  0);
    21512151        AssertRC(rc);
    21522152    }
    … …  
    21712171        {
    21722172            /* Update these as wrmsr might have changed them. */
    2173             rc = VMXWriteVMCS64(VMX_VMCS_GUEST_FS_BASE, pCtx->fs.u64Base);
     2173            rc = VMXWriteVmcs64(VMX_VMCS_GUEST_FS_BASE, pCtx->fs.u64Base);
    21742174            AssertRC(rc);
    2175             rc = VMXWriteVMCS64(VMX_VMCS_GUEST_GS_BASE, pCtx->gs.u64Base);
     2175            rc = VMXWriteVmcs64(VMX_VMCS_GUEST_GS_BASE, pCtx->gs.u64Base);
    21762176            AssertRC(rc);
    21772177        }
    … …  
    22432243    pVCpu->hm.s.vmx.cGuestMsrs = idxMsr;
    22442244
    2245     rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, idxMsr);
     2245    rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, idxMsr);
    22462246    AssertRC(rc);
    22472247
    2248     rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, idxMsr);
     2248    rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, idxMsr);
    22492249    AssertRC(rc);
    22502250#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
    … …  
    22632263        cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
    22642264        uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
    2265         rc = VMXWriteVMCS(VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE, cPreemptionTickCount);
     2265        rc = VMXWriteVmcs(VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE, cPreemptionTickCount);
    22662266        AssertRC(rc);
    22672267    }
    … …  
    22752275        {
    22762276            /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
    2277             rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset);
     2277            rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset);
    22782278            AssertRC(rc);
    22792279
    22802280            pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
    2281             rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     2281            rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    22822282            AssertRC(rc);
    22832283            STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
    … …  
    22912291                     TMCpuTickGet(pVCpu)));
    22922292            pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
    2293             rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     2293            rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    22942294            AssertRC(rc);
    22952295            STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
    … …  
    22992299    {
    23002300        pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
    2301         rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     2301        rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    23022302        AssertRC(rc);
    23032303        STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
    … …  
    23282328
    23292329    /* First sync back EIP, ESP, and EFLAGS. */
    2330     rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RIP,            &val);
     2330    rc = VMXReadCachedVmcs(VMX_VMCS_GUEST_RIP,            &val);
    23312331    AssertRC(rc);
    23322332    pCtx->rip               = val;
    2333     rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RSP,            &val);
     2333    rc = VMXReadCachedVmcs(VMX_VMCS_GUEST_RSP,            &val);
    23342334    AssertRC(rc);
    23352335    pCtx->rsp               = val;
    2336     rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS,           &val);
     2336    rc = VMXReadCachedVmcs(VMX_VMCS_GUEST_RFLAGS,           &val);
    23372337    AssertRC(rc);
    23382338    pCtx->eflags.u32        = val;
    23392339
    23402340    /* Take care of instruction fusing (sti, mov ss) */
    2341     rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
     2341    rc |= VMXReadCachedVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
    23422342    uInterruptState = val;
    23432343    if (uInterruptState != 0)
    … …  
    23512351
    23522352    /* Control registers. */
    2353     VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW,     &valShadow);
    2354     VMXReadCachedVMCS(VMX_VMCS_GUEST_CR0,                &val);
     2353    VMXReadCachedVmcs(VMX_VMCS_CTRL_CR0_READ_SHADOW,     &valShadow);
     2354    VMXReadCachedVmcs(VMX_VMCS_GUEST_CR0,                &val);
    23552355    val = (valShadow & pVCpu->hm.s.vmx.cr0_mask) | (val & ~pVCpu->hm.s.vmx.cr0_mask);
    23562356    CPUMSetGuestCR0(pVCpu, val);
    23572357
    2358     VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW,     &valShadow);
    2359     VMXReadCachedVMCS(VMX_VMCS_GUEST_CR4,                &val);
     2358    VMXReadCachedVmcs(VMX_VMCS_CTRL_CR4_READ_SHADOW,     &valShadow);
     2359    VMXReadCachedVmcs(VMX_VMCS_GUEST_CR4,                &val);
    23602360    val = (valShadow & pVCpu->hm.s.vmx.cr4_mask) | (val & ~pVCpu->hm.s.vmx.cr4_mask);
    23612361    CPUMSetGuestCR4(pVCpu, val);
    … …  
    23732373        CPUMSetGuestCR2(pVCpu, pCache->cr2);
    23742374
    2375         VMXReadCachedVMCS(VMX_VMCS_GUEST_CR3, &val);
     2375        VMXReadCachedVmcs(VMX_VMCS_GUEST_CR3, &val);
    23762376
    23772377        if (val != pCtx->cr3)
    … …  
    23852385
    23862386    /* Sync back DR7. */
    2387     VMXReadCachedVMCS(VMX_VMCS_GUEST_DR7, &val);
     2387    VMXReadCachedVmcs(VMX_VMCS_GUEST_DR7, &val);
    23882388    pCtx->dr[7] = val;
    23892389
    … …  
    23972397
    23982398    /* System MSRs */
    2399     VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS,      &val);
     2399    VMXReadCachedVmcs(VMX_VMCS32_GUEST_SYSENTER_CS,      &val);
    24002400    pCtx->SysEnter.cs       = val;
    2401     VMXReadCachedVMCS(VMX_VMCS_GUEST_SYSENTER_EIP,     &val);
     2401    VMXReadCachedVmcs(VMX_VMCS_GUEST_SYSENTER_EIP,     &val);
    24022402    pCtx->SysEnter.eip      = val;
    2403     VMXReadCachedVMCS(VMX_VMCS_GUEST_SYSENTER_ESP,     &val);
     2403    VMXReadCachedVmcs(VMX_VMCS_GUEST_SYSENTER_ESP,     &val);
    24042404    pCtx->SysEnter.esp      = val;
    24052405
    … …  
    24072407    VMX_READ_SELREG(LDTR, ldtr);
    24082408
    2409     VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT,       &val);
     2409    VMXReadCachedVmcs(VMX_VMCS32_GUEST_GDTR_LIMIT,       &val);
    24102410    pCtx->gdtr.cbGdt        = val;
    2411     VMXReadCachedVMCS(VMX_VMCS_GUEST_GDTR_BASE,        &val);
     2411    VMXReadCachedVmcs(VMX_VMCS_GUEST_GDTR_BASE,        &val);
    24122412    pCtx->gdtr.pGdt         = val;
    24132413
    2414     VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT,       &val);
     2414    VMXReadCachedVmcs(VMX_VMCS32_GUEST_IDTR_LIMIT,       &val);
    24152415    pCtx->idtr.cbIdt        = val;
    2416     VMXReadCachedVMCS(VMX_VMCS_GUEST_IDTR_BASE,        &val);
     2416    VMXReadCachedVmcs(VMX_VMCS_GUEST_IDTR_BASE,        &val);
    24172417    pCtx->idtr.pIdt         = val;
    24182418
    … …  
    26022602
    26032603    /* Update VMCS with the VPID. */
    2604     int rc  = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
     2604    int rc  = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
    26052605    AssertRC(rc);
    26062606}
    … …  
    27612761              ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
    27622762
    2763     int rc  = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
     2763    int rc  = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
    27642764    AssertRC(rc);
    27652765
    … …  
    28312831     * originated before a VM reset *after* the VM has been reset. See @bugref{6220}.
    28322832     */
    2833     VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, 0);
     2833    VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, 0);
    28342834
    28352835#ifdef VBOX_STRICT
    … …  
    28372837        RTCCUINTREG val2;
    28382838
    2839         rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, &val2);
     2839        rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, &val2);
    28402840        AssertRC(rc2);
    28412841        Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n",  val2));
    … …  
    28492849            Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
    28502850
    2851         rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, &val2);
     2851        rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, &val2);
    28522852        AssertRC(rc2);
    28532853        Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n",  val2));
    … …  
    28712871            Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
    28722872
    2873         rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_ENTRY_CONTROLS, &val2);
     2873        rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_ENTRY_CONTROLS, &val2);
    28742874        AssertRC(rc2);
    28752875        Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n",  val2));
    … …  
    28832883            Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
    28842884
    2885         rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_EXIT_CONTROLS, &val2);
     2885        rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_EXIT_CONTROLS, &val2);
    28862886        AssertRC(rc2);
    28872887        Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n",  val2));
    … …  
    29412941            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
    29422942            /* Irq inhibition is no longer active; clear the corresponding VMX state. */
    2943             rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,   0);
     2943            rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,   0);
    29442944            AssertRC(rc2);
    29452945        }
    … …  
    29482948    {
    29492949        /* Irq inhibition is no longer active; clear the corresponding VMX state. */
    2950         rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,   0);
     2950        rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,   0);
    29512951        AssertRC(rc2);
    29522952    }
    … …  
    30773077
    30783078        /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
    3079         rc  = VMXWriteVMCS(VMX_VMCS32_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0);
     3079        rc  = VMXWriteVmcs(VMX_VMCS32_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0);
    30803080        AssertRC(VBOXSTRICTRC_VAL(rc));
    30813081
    … …  
    31803180    /* Non-register state Guest Context */
    31813181    /** @todo change me according to cpu state */
    3182     rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE,           VMX_CMS_GUEST_ACTIVITY_ACTIVE);
     3182    rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_ACTIVITY_STATE,           VMX_CMS_GUEST_ACTIVITY_ACTIVE);
    31833183    AssertRC(rc2);
    31843184
    … …  
    33013301
    33023302    /* Investigate why there was a VM-exit. */
    3303     rc2  = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
     3303    rc2  = VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
    33043304    STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
    33053305
    33063306    exitReason &= 0xffff;   /* bit 0-15 contain the exit code. */
    3307     rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
    3308     rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
    3309     rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
     3307    rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
     3308    rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
     3309    rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
    33103310    /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
    3311     rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
    3312     rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
    3313     rc2 |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
     3311    rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
     3312    rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
     3313    rc2 |= VMXReadCachedVmcs(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
    33143314    AssertRC(rc2);
    33153315
    … …  
    33303330     * Check if an injected event was interrupted prematurely.
    33313331     */
    3332     rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO,            &val);
     3332    rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_IDT_INFO,            &val);
    33333333    AssertRC(rc2);
    33343334    pVCpu->hm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
    … …  
    33443344        if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo))
    33453345        {
    3346             rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
     3346            rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_IDT_ERRCODE, &val);
    33473347            AssertRC(rc2);
    33483348            pVCpu->hm.s.Event.errCode  = val;
    … …  
    36463646
    36473647                    /* Resync DR7 */
    3648                     rc2 = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
     3648                    rc2 = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
    36493649                    AssertRC(rc2);
    36503650
    … …  
    37253725                            EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->cbInstr);
    37263726                            Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
    3727                             rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,
     3727                            rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,
    37283728                                               VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
    37293729                            AssertRC(rc2);
    … …  
    40154015        Assert(pVM->hm.s.fNestedPaging);
    40164016
    4017         rc2 = VMXReadVMCS64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
     4017        rc2 = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
    40184018        AssertRC(rc2);
    40194019        Assert(((exitQualification >> 7) & 3) != 2);
    … …  
    40894089        Assert(pVM->hm.s.fNestedPaging);
    40904090
    4091         rc2 = VMXReadVMCS64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
     4091        rc2 = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
    40924092        AssertRC(rc2);
    40934093        Log(("VMX_EXIT_EPT_MISCONFIG for %RGp\n", GCPhys));
    … …  
    41354135                 VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
    41364136        pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
    4137         rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     4137        rc2 = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    41384138        AssertRC(rc2);
    41394139        STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIrqWindow);
    … …  
    43904390            /* Disable DRx move intercepts. */
    43914391            pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
    4392             rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     4392            rc2 = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    43934393            AssertRC(rc2);
    43944394
    … …  
    45804580
    45814581                            /* Resync DR7 */
    4582                             rc2 = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
     4582                            rc2 = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
    45834583                            AssertRC(rc2);
    45844584
    … …  
    47564756        LogFlow(("VMX_EXIT_MTF at %RGv\n", (RTGCPTR)pCtx->rip));
    47574757        pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG;
    4758         rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     4758        rc2 = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    47594759        AssertRC(rc2);
    47604760        STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
    … …  
    48274827        Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
    48284828
    4829         VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val2);
     4829        VMXReadVmcs(VMX_VMCS_GUEST_RIP, &val2);
    48304830        Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val2));
    48314831
    4832         VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val2);
     4832        VMXReadVmcs(VMX_VMCS_GUEST_CR0, &val2);
    48334833        Log(("VMX_VMCS_GUEST_CR0        %RX64\n", (uint64_t)val2));
    48344834
    4835         VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val2);
     4835        VMXReadVmcs(VMX_VMCS_GUEST_CR3, &val2);
    48364836        Log(("VMX_VMCS_GUEST_CR3        %RX64\n", (uint64_t)val2));
    48374837
    4838         VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val2);
     4838        VMXReadVmcs(VMX_VMCS_GUEST_CR4, &val2);
    48394839        Log(("VMX_VMCS_GUEST_CR4        %RX64\n", (uint64_t)val2));
    48404840
    4841         VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val2);
     4841        VMXReadVmcs(VMX_VMCS_GUEST_RFLAGS, &val2);
    48424842        Log(("VMX_VMCS_GUEST_RFLAGS     %08x\n", val2));
    48434843
    … …  
    48514851        VMX_LOG_SELREG(LDTR, "LDTR", val2);
    48524852
    4853         VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val2);
     4853        VMXReadVmcs(VMX_VMCS_GUEST_GDTR_BASE, &val2);
    48544854        Log(("VMX_VMCS_GUEST_GDTR_BASE    %RX64\n", (uint64_t)val2));
    4855         VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val2);
     4855        VMXReadVmcs(VMX_VMCS_GUEST_IDTR_BASE, &val2);
    48564856        Log(("VMX_VMCS_GUEST_IDTR_BASE    %RX64\n", (uint64_t)val2));
    48574857#endif /* VBOX_STRICT */
    … …  
    49914991        /* Enable DRx move intercepts again. */
    49924992        pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
    4993         int rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
     4993        int rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
    49944994        AssertRC(rc);
    49954995
    … …  
    51635163            RTCCUINTREG exitReason, instrError;
    51645164
    5165             rc2  = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
    5166             rc2 |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
     5165            rc2  = VMXReadVmcs(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
     5166            rc2 |= VMXReadVmcs(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
    51675167            AssertRC(rc2);
    51685168            if (rc2 == VINF_SUCCESS)
    … …  
    51825182                ASMGetGDTR(&gdtr);
    51835183
    5184                 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
     5184                VMXReadVmcs(VMX_VMCS_GUEST_RIP, &val);
    51855185                Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
    5186                 VMXReadVMCS(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS,   &val);
     5186                VMXReadVmcs(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS,   &val);
    51875187                Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS   %08x\n", val));
    5188                 VMXReadVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS,   &val);
     5188                VMXReadVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS,   &val);
    51895189                Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS  %08x\n", val));
    5190                 VMXReadVMCS(VMX_VMCS32_CTRL_ENTRY_CONTROLS,       &val);
     5190                VMXReadVmcs(VMX_VMCS32_CTRL_ENTRY_CONTROLS,       &val);
    51915191                Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS      %08x\n", val));
    5192                 VMXReadVMCS(VMX_VMCS32_CTRL_EXIT_CONTROLS,        &val);
     5192                VMXReadVmcs(VMX_VMCS32_CTRL_EXIT_CONTROLS,        &val);
    51935193                Log(("VMX_VMCS_CTRL_EXIT_CONTROLS       %08x\n", val));
    51945194
    5195                 VMXReadVMCS(VMX_VMCS_HOST_CR0,  &val);
     5195                VMXReadVmcs(VMX_VMCS_HOST_CR0,  &val);
    51965196                Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
    5197                 VMXReadVMCS(VMX_VMCS_HOST_CR3,  &val);
     5197                VMXReadVmcs(VMX_VMCS_HOST_CR3,  &val);
    51985198                Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
    5199                 VMXReadVMCS(VMX_VMCS_HOST_CR4,  &val);
     5199                VMXReadVmcs(VMX_VMCS_HOST_CR4,  &val);
    52005200                Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
    52015201
    5202                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
     5202                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_CS, &val);
    52035203                Log(("VMX_VMCS_HOST_FIELD_CS %08x\n",  val));
    5204                 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS,  &val);
     5204                VMXReadVmcs(VMX_VMCS_GUEST_RFLAGS,  &val);
    52055205                Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
    52065206
    … …  
    52115211                }
    52125212
    5213                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
     5213                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_DS, &val);
    52145214                Log(("VMX_VMCS_HOST_FIELD_DS %08x\n",  val));
    52155215                if (val < gdtr.cbGdt)
    … …  
    52195219                }
    52205220
    5221                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
     5221                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_ES, &val);
    52225222                Log(("VMX_VMCS_HOST_FIELD_ES %08x\n",  val));
    52235223                if (val < gdtr.cbGdt)
    … …  
    52275227                }
    52285228
    5229                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
     5229                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_FS, &val);
    52305230                Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
    52315231                if (val < gdtr.cbGdt)
    … …  
    52355235                }
    52365236
    5237                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS,  &val);
     5237                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_GS,  &val);
    52385238                Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
    52395239                if (val < gdtr.cbGdt)
    … …  
    52435243                }
    52445244
    5245                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS,  &val);
     5245                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_SS,  &val);
    52465246                Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
    52475247                if (val < gdtr.cbGdt)
    … …  
    52515251                }
    52525252
    5253                 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR,  &val);
     5253                VMXReadVmcs(VMX_VMCS16_HOST_FIELD_TR,  &val);
    52545254                Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
    52555255                if (val < gdtr.cbGdt)
    … …  
    52595259                }
    52605260
    5261                 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE,         &val);
     5261                VMXReadVmcs(VMX_VMCS_HOST_TR_BASE,         &val);
    52625262                Log(("VMX_VMCS_HOST_TR_BASE %RHv\n",        val));
    5263                 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE,       &val);
     5263                VMXReadVmcs(VMX_VMCS_HOST_GDTR_BASE,       &val);
    52645264                Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n",      val));
    5265                 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE,       &val);
     5265                VMXReadVmcs(VMX_VMCS_HOST_IDTR_BASE,       &val);
    52665266                Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n",      val));
    5267                 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS,   &val);
     5267                VMXReadVmcs(VMX_VMCS32_HOST_SYSENTER_CS,   &val);
    52685268                Log(("VMX_VMCS_HOST_SYSENTER_CS  %08x\n",   val));
    5269                 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP,    &val);
     5269                VMXReadVmcs(VMX_VMCS_HOST_SYSENTER_EIP,    &val);
    52705270                Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n",   val));
    5271                 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP,    &val);
     5271                VMXReadVmcs(VMX_VMCS_HOST_SYSENTER_ESP,    &val);
    52725272                Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n",   val));
    5273                 VMXReadVMCS(VMX_VMCS_HOST_RSP,             &val);
     5273                VMXReadVmcs(VMX_VMCS_HOST_RSP,             &val);
    52745274                Log(("VMX_VMCS_HOST_RSP %RHv\n",            val));
    5275                 VMXReadVMCS(VMX_VMCS_HOST_RIP,             &val);
     5275                VMXReadVmcs(VMX_VMCS_HOST_RIP,             &val);
    52765276                Log(("VMX_VMCS_HOST_RIP %RHv\n",            val));
    52775277# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
    … …  
    55645564 * @param   u64Val          16, 32 or 64 bits value.
    55655565 */
    5566 VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
     5566VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
    55675567{
    55685568    int rc;
    … …  
    55875587        case VMX_VMCS64_CTRL_EPTP_FULL:
    55885588            /* These fields consist of two parts, which are both writable in 32 bits mode. */
    5589             rc  = VMXWriteVMCS32(idxField, u64Val);
    5590             rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
     5589            rc  = VMXWriteVmcs32(idxField, u64Val);
     5590            rc |= VMXWriteVmcs32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
    55915591            AssertRC(rc);
    55925592            return rc;
    … …  
    56125612            /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
    56135613            if (u64Val >> 32ULL)
    5614                 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
     5614                rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
    56155615            else
    5616                 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
     5616                rc = VMXWriteVmcs32(idxField, (uint32_t)u64Val);
    56175617
    56185618            return rc;
    … …  
    56325632 * @param   u64Val      16, 32 or 64 bits value.
    56335633 */
    5634 VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
     5634VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
    56355635{
    56365636    PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.h

    r43769 r43930  
    9494#define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX                                    55
    9595#define VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX                                 56
    96 #define VMX_VMCS_MAX_CACHE_IDX                                              (VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX+1)
     96#define VMX_VMCS_MAX_CACHE_IDX                                              (VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX + 1)
    9797#define VMX_VMCS_GUEST_CR3_CACHE_IDX                                        57
    9898#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX                      58
    99 #define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX                                (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX+1)
     99#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX                                (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
    100100
    101101
    … …  
    209209    do \
    210210    { \
    211         rc  = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG,        pCtx->reg.Sel);                 \
    212         rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,      pCtx->reg.u32Limit);            \
    213         rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_##REG##_BASE,       pCtx->reg.u64Base);             \
     211        rc  = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_##REG,        pCtx->reg.Sel);                 \
     212        rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_##REG##_LIMIT,      pCtx->reg.u32Limit);            \
     213        rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_##REG##_BASE,       pCtx->reg.u64Base);             \
    214214        if ((pCtx->eflags.u32 & X86_EFL_VM))                                                    \
    215215        {                                                                                       \
    … …  
    241241            val = 0x10000;  /* Invalid guest state error otherwise. (BIT(16) = Unusable) */     \
    242242                                                                                                \
    243         rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, val);                        \
     243        rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, val);                        \
    244244    } while (0)
    245245
    … …  
    247247    do \
    248248    { \
    249         VMXReadCachedVMCS(VMX_VMCS16_GUEST_FIELD_##REG,           &val); \
     249        VMXReadCachedVmcs(VMX_VMCS16_GUEST_FIELD_##REG,           &val); \
    250250        pCtx->reg.Sel       = val; \
    251251        pCtx->reg.ValidSel  = val; \
    252252        pCtx->reg.fFlags    = CPUMSELREG_FLAGS_VALID; \
    253         VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,         &val); \
     253        VMXReadCachedVmcs(VMX_VMCS32_GUEST_##REG##_LIMIT,         &val); \
    254254        pCtx->reg.u32Limit  = val; \
    255         VMXReadCachedVMCS(VMX_VMCS_GUEST_##REG##_BASE,            &val); \
     255        VMXReadCachedVmcs(VMX_VMCS_GUEST_##REG##_BASE,            &val); \
    256256        pCtx->reg.u64Base   = val; \
    257         VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \
     257        VMXReadCachedVmcs(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \
    258258        pCtx->reg.Attr.u    = val; \
    259259    } while (0)
    … …  
    263263    do \
    264264    { \
    265         VMXReadVMCS(VMX_VMCS16_GUEST_FIELD_##REG,           &(val)); \
     265        VMXReadVmcs(VMX_VMCS16_GUEST_FIELD_##REG,           &(val)); \
    266266        Log(("%s Selector     %x\n", szSelReg, (val))); \
    267         VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT,         &(val)); \
     267        VMXReadVmcs(VMX_VMCS32_GUEST_##REG##_LIMIT,         &(val)); \
    268268        Log(("%s Limit        %x\n", szSelReg, (val))); \
    269         VMXReadVMCS(VMX_VMCS_GUEST_##REG##_BASE,            &(val)); \
     269        VMXReadVmcs(VMX_VMCS_GUEST_##REG##_BASE,            &(val)); \
    270270        Log(("%s Base         %RX64\n", szSelReg, (uint64_t)(val))); \
    271         VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val)); \
     271        VMXReadVmcs(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val)); \
    272272        Log(("%s Attributes   %x\n", szSelReg, (val))); \
    273273    } while (0)
    … …  
    281281 * @param   u64Val      16, 32 or 64 bits value.
    282282 */
    283 VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
     283VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
    284284
    285285#ifdef VMX_USE_CACHED_VMCS_ACCESSES
    … …  
    291291 * @param   pVal        16, 32 or 64 bits value.
    292292 */
    293 DECLINLINE(int) VMXReadCachedVMCSEx(PVMCPU pVCpu, uint32_t idxCache, RTGCUINTREG *pVal)
     293DECLINLINE(int) VMXReadCachedVmcsEx(PVMCPU pVCpu, uint32_t idxCache, RTGCUINTREG *pVal)
    294294{
    295295    Assert(idxCache <= VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX);
    … …  
    307307 */
    308308#ifdef VMX_USE_CACHED_VMCS_ACCESSES
    309 # define VMXReadCachedVMCS(idxField, pVal)              VMXReadCachedVMCSEx(pVCpu, idxField##_CACHE_IDX, pVal)
     309# define VMXReadCachedVmcs(idxField, pVal)              VMXReadCachedVmcsEx(pVCpu, idxField##_CACHE_IDX, pVal)
    310310#else
    311 # define VMXReadCachedVMCS(idxField, pVal)              VMXReadVMCS(idxField, pVal)
     311# define VMXReadCachedVmcs(idxField, pVal)              VMXReadVmcs(idxField, pVal)
    312312#endif
    313313
    … …  
    319319 * @param   idxField    VMCS field index.
    320320 */
    321 #define VMXSetupCachedReadVMCS(pCache, idxField)                                    \
     321#define VMXSetupCachedReadVmcs(pCache, idxField)                                    \
    322322{                                                                                   \
    323323    Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0);                         \
    … …  
    328328#define VMX_SETUP_SELREG(REG, pCache)                                               \
    329329{                                                                                   \
    330         VMXSetupCachedReadVMCS(pCache, VMX_VMCS16_GUEST_FIELD_##REG);               \
    331         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_##REG##_LIMIT);             \
    332         VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_##REG##_BASE);              \
    333         VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS);     \
     330        VMXSetupCachedReadVmcs(pCache, VMX_VMCS16_GUEST_FIELD_##REG);               \
     331        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_##REG##_LIMIT);             \
     332        VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_##REG##_BASE);              \
     333        VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS);     \
    334334}
    335335

  • trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

    r43394 r43930  
    15081508}
    15091509
     1510
     1511/**
     1512 * Checks if log flushing is disabled or not.
     1513 *
     1514 * @param   pVCpu       Pointer to the VMCPU.
     1515 */
     1516VMMR0DECL(bool) VMMR0IsLogFlushDisabled(PVMCPU pVCpu)
     1517{
     1518    if (pVCpu->vmm.s.pR0LoggerR0)
     1519        return pVCpu->vmm.s.pR0LoggerR0->fFlushingDisabled;
     1520    return true;
     1521}
    15101522#endif /* LOG_ENABLED */
    15111523
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