Changeset 44033 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Dec 4, 2012 6:25:40 PM (12 years ago)

Author:

vboxsync

Message:

VMM: hungarian.

File:

• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1000 +1000 @@
     if (pVCpu->hm.s.Event.fPending)
     {
-        Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hm.s.Event.intInfo,
-             pVCpu->hm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
+        Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hm.s.Event.uIntrInfo,
+             pVCpu->hm.s.Event.uErrCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
         STAM_COUNTER_INC(&pVCpu->hm.s.StatIntReinject);
-        rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, pVCpu->hm.s.Event.intInfo, 0, pVCpu->hm.s.Event.errCode);
+        rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, pVCpu->hm.s.Event.uIntrInfo, 0, pVCpu->hm.s.Event.uErrCode);
         AssertRC(rc);
 
@@ -1171 +1171 @@
          */
         pVCpu->hm.s.Event.fPending = false;
-        switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo))
+        switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.uIntrInfo))
         {
         case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT:
@@ -1189 +1189 @@
             AssertFailed();
         }
-        TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.intInfo), enmTrapType);
-        if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo))
-            TRPMSetErrorCode(pVCpu, pVCpu->hm.s.Event.errCode);
+        TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.uIntrInfo), enmTrapType);
+        if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.uIntrInfo))
+            TRPMSetErrorCode(pVCpu, pVCpu->hm.s.Event.uErrCode);
         //@todo: Is there any situation where we need to call TRPMSetFaultAddress()?
     }
@@ -3332 +3332 @@
     rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_IDT_INFO,            &val);
     AssertRC(rc2);
-    pVCpu->hm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
-    if (    VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hm.s.Event.intInfo)
+    pVCpu->hm.s.Event.uIntrInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
+    if (    VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hm.s.Event.uIntrInfo)
         /* Ignore 'int xx' as they'll be restarted anyway. */
-        &&  VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
+        &&  VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.uIntrInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
         /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
-        &&  VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
+        &&  VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.uIntrInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
     {
         Assert(!pVCpu->hm.s.Event.fPending);
         pVCpu->hm.s.Event.fPending = true;
         /* Error code present? */
-        if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo))
+        if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.uIntrInfo))
         {
             rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_IDT_ERRCODE, &val);
             AssertRC(rc2);
-            pVCpu->hm.s.Event.errCode  = val;
+            pVCpu->hm.s.Event.uErrCode  = val;
             Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n",
-                 pVCpu->hm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
+                 pVCpu->hm.s.Event.uIntrInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
         }
         else
         {
-            Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hm.s.Event.intInfo,
+            Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hm.s.Event.uIntrInfo,
                  (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
-            pVCpu->hm.s.Event.errCode  = 0;
+            pVCpu->hm.s.Event.uErrCode  = 0;
         }
     }
 #ifdef VBOX_STRICT
-    else if (   VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hm.s.Event.intInfo)
+    else if (   VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hm.s.Event.uIntrInfo)
                 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
-             && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
+             && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.uIntrInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
     {
         Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n",
-             pVCpu->hm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
+             pVCpu->hm.s.Event.uIntrInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
     }
 
@@ -4711 +4711 @@
             pVCpu->hm.s.Event.fPending = false;
 
-            Log(("VMX_EXIT_TASK_SWITCH: reassert trap %d\n", VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.intInfo)));
-            Assert(!VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo));
+            Log(("VMX_EXIT_TASK_SWITCH: reassert trap %d\n", VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.uIntrInfo)));
+            Assert(!VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.uIntrInfo));
             //@todo: Why do we assume this had to be a hardware interrupt? What about software interrupts or exceptions?
-            rc2 = TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.intInfo), TRPM_HARDWARE_INT);
+            rc2 = TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.uIntrInfo), TRPM_HARDWARE_INT);
             AssertRC(rc2);
         }