VirtualBox

Changeset 44373 in vbox for trunk/include/VBox


Ignore:
Timestamp:
Jan 25, 2013 12:19:29 PM (12 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
83343
Message:

HM,++: pVM -> pUVM for main, mark as many as possible interfaces module internal.

Location:
trunk/include/VBox
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/err.h

    r43746 r44373  
    8585 * should results in the particular service being disabled. */
    8686#define VERR_SERVICE_DISABLED               (-1020)
     87/** The requested feature is not supported in raw-mode. */
     88#define VERR_NOT_SUP_IN_RAW_MODE            (-1021)
    8789/** @} */
    8890

  • trunk/include/VBox/vmm/csam.h

    r41732 r44373  
    152152 */
    153153
    154 /**
    155  * Query CSAM state (enabled/disabled)
    156  *
    157  * @returns 0 - disabled, 1 - enabled
    158  * @param   pVM         The VM to operate on.
    159  */
    160 VMMR3DECL(int) CSAMR3IsEnabled(PVM pVM);
     154VMMR3DECL(bool) CSAMR3IsEnabled(PUVM pUVM);
    161155
    162156/**

  • trunk/include/VBox/vmm/dbgf.h

    r43394 r44373  
    300300VMMR3DECL(int)  DBGFR3Step(PVM pVM, VMCPUID idCpu);
    301301VMMR3DECL(int)  DBGFR3PrgStep(PVMCPU pVCpu);
     302VMMR3DECL(int)  DBGFR3InjectNMI(PUVM pUVM, VMCPUID idCpu);
    302303
    303304#endif /* IN_RING3 */

  • trunk/include/VBox/vmm/em.h

    r44340 r44373  
    225225 * @{
    226226 */
     227
     228VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM);
     229VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM);
     230
    227231VMMR3DECL(int)          EMR3Init(PVM pVM);
    228232VMMR3DECL(void)         EMR3Relocate(PVM pVM);

  • trunk/include/VBox/vmm/hm.h

    r44195 r44373  
    11/** @file
    2  * HM - Intel/AMD VM Hardware Support Manager (VMM)
     2 * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
    33 */
    44
    55/*
    6  * Copyright (C) 2006-2010 Oracle Corporation
     6 * Copyright (C) 2006-2013 Oracle Corporation
    77 *
    88 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    4343 *
    4444 * @returns 0 - disabled, 1 - enabled
    45  * @param   pVM         The VM to operate on.
     45 * @param   a_pVM       Pointer to the shared VM structure.
     46 * @internal
    4647 */
    47 #define HMIsEnabled(pVM)    ((pVM)->fHMEnabled)
     48#define HMIsEnabled(a_pVM)    ((a_pVM)->fHMEnabled)
    4849
    4950 /**
    … …  
    5152 *
    5253 * @returns boolean
    53  * @param   pCtx        CPU context
     54 * @param   a_pVCpu     Pointer to the shared virtual CPU structure.
     55 * @internal
    5456 */
    55 #define HMCanEmulateIoBlock(pVCpu)     (!CPUMIsGuestInPagedProtectedMode(pVCpu))
    56 #define HMCanEmulateIoBlockEx(pCtx)    (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
     57#define HMCanEmulateIoBlock(a_pVCpu)     (!CPUMIsGuestInPagedProtectedMode(a_pVCpu))
    5758
    58 VMMDECL(int)            HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
    59 VMMDECL(bool)           HMHasPendingIrq(PVM pVM);
    60 VMMDECL(PX86PDPE)       HMGetPaePdpes(PVMCPU pVCpu);
     59 /**
     60 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
     61 *
     62 * @returns boolean
     63 * @param   a_pCtx      Pointer to the CPU context (within PVM).
     64 * @internal
     65 */
     66#define HMCanEmulateIoBlockEx(a_pCtx)   (!CPUMIsGuestInPagedProtectedModeEx(a_pCtx))
     67
     68VMM_INT_DECL(int)               HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
     69VMM_INT_DECL(bool)              HMHasPendingIrq(PVM pVM);
     70VMM_INT_DECL(PX86PDPE)          HMGetPaePdpes(PVMCPU pVCpu);
    6171
    6272#ifndef IN_RC
    63 VMMDECL(int)            HMFlushTLB(PVMCPU pVCpu);
    64 VMMDECL(int)            HMFlushTLBOnAllVCpus(PVM pVM);
    65 VMMDECL(int)            HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
    66 VMMDECL(int)            HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
    67 VMMDECL(bool)           HMIsNestedPagingActive(PVM pVM);
    68 VMMDECL(PGMMODE)        HMGetShwPagingMode(PVM pVM);
    69 #else
    70 /* Nop in GC */
     73VMM_INT_DECL(int)               HMFlushTLB(PVMCPU pVCpu);
     74VMM_INT_DECL(int)               HMFlushTLBOnAllVCpus(PVM pVM);
     75VMM_INT_DECL(int)               HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
     76VMM_INT_DECL(int)               HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
     77VMM_INT_DECL(bool)              HMIsNestedPagingActive(PVM pVM);
     78VMM_INT_DECL(PGMMODE)           HMGetShwPagingMode(PVM pVM);
     79#else /* Nops in RC: */
    7180# define HMFlushTLB(pVCpu)                  do { } while (0)
    7281# define HMIsNestedPagingActive(pVM)        false
    … …  
    7988 * @{
    8089 */
    81 VMMR0DECL(int)          HMR0Init(void);
    82 VMMR0DECL(int)          HMR0Term(void);
    83 VMMR0DECL(int)          HMR0InitVM(PVM pVM);
    84 VMMR0DECL(int)          HMR0TermVM(PVM pVM);
    85 VMMR0DECL(int)          HMR0EnableAllCpus(PVM pVM);
    86 VMMR0DECL(int)          HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
    87 VMMR0DECL(void)         HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
     90VMMR0_INT_DECL(int)             HMR0Init(void);
     91VMMR0_INT_DECL(int)             HMR0Term(void);
     92VMMR0_INT_DECL(int)             HMR0InitVM(PVM pVM);
     93VMMR0_INT_DECL(int)             HMR0TermVM(PVM pVM);
     94VMMR0_INT_DECL(int)             HMR0EnableAllCpus(PVM pVM);
     95VMMR0_INT_DECL(int)             HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
     96VMMR0_INT_DECL(void)            HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
    8897
    89 VMMR0DECL(void)         HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize);
    90 VMMR0DECL(void)         HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize);
     98VMMR0_INT_DECL(void)            HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
     99                                                           unsigned uPort, unsigned uAndVal, unsigned cbSize);
     100VMMR0_INT_DECL(void)            HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
     101                                                          unsigned uPort, unsigned uAndVal, unsigned cbSize);
    91102
    92103/** @} */
    … …  
    99110 * @{
    100111 */
    101 VMMR3DECL(bool)         HMR3IsEventPending(PVMCPU pVCpu);
    102 VMMR3DECL(int)          HMR3Init(PVM pVM);
    103 VMMR3_INT_DECL(int)     HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
    104 VMMR3DECL(void)         HMR3Relocate(PVM pVM);
    105 VMMR3DECL(int)          HMR3Term(PVM pVM);
    106 VMMR3DECL(void)         HMR3Reset(PVM pVM);
    107 VMMR3DECL(void)         HMR3ResetCpu(PVMCPU pVCpu);
    108 VMMR3DECL(void)         HMR3CheckError(PVM pVM, int iStatusCode);
    109 VMMR3DECL(bool)         HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
    110 VMMR3DECL(void)         HMR3NotifyScheduled(PVMCPU pVCpu);
    111 VMMR3DECL(void)         HMR3NotifyEmulated(PVMCPU pVCpu);
    112 VMMR3DECL(bool)         HMR3IsActive(PVMCPU pVCpu);
    113 VMMR3DECL(bool)         HMR3IsNestedPagingActive(PVM pVM);
    114 VMMR3DECL(bool)         HMR3IsAllowed(PVM pVM);
    115 VMMR3DECL(void)         HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
    116 VMMR3DECL(bool)         HMR3IsVPIDActive(PVM pVM);
    117 VMMR3DECL(int)          HMR3InjectNMI(PVM pVM);
    118 VMMR3DECL(int)          HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
    119 VMMR3DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    120 VMMR3DECL(int)          HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
    121 VMMR3DECL(int)          HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
    122 VMMR3DECL(int)          HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    123 VMMR3DECL(bool)         HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
    124 VMMR3DECL(bool)         HMR3IsVmxPreemptionTimerUsed(PVM pVM);
     112VMMR3DECL(bool)                 HMR3IsEnabled(PUVM pUVM);
     113VMMR3DECL(bool)                 HMR3IsNestedPagingActive(PUVM pUVM);
     114VMMR3DECL(bool)                 HMR3IsVpidActive(PUVM pVUM);
     115
     116VMMR3_INT_DECL(bool)            HMR3IsEventPending(PVMCPU pVCpu);
     117VMMR3_INT_DECL(int)             HMR3Init(PVM pVM);
     118VMMR3_INT_DECL(int)             HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
     119VMMR3_INT_DECL(void)            HMR3Relocate(PVM pVM);
     120VMMR3_INT_DECL(int)             HMR3Term(PVM pVM);
     121VMMR3_INT_DECL(void)            HMR3Reset(PVM pVM);
     122VMMR3_INT_DECL(void)            HMR3ResetCpu(PVMCPU pVCpu);
     123VMMR3_INT_DECL(void)            HMR3CheckError(PVM pVM, int iStatusCode);
     124VMMR3DECL(bool)                 HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
     125VMMR3_INT_DECL(void)            HMR3NotifyScheduled(PVMCPU pVCpu);
     126VMMR3_INT_DECL(void)            HMR3NotifyEmulated(PVMCPU pVCpu);
     127VMMR3_INT_DECL(bool)            HMR3IsActive(PVMCPU pVCpu);
     128VMMR3_INT_DECL(bool)            HMR3IsAllowed(PVM pVM);
     129VMMR3_INT_DECL(void)            HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
     130VMMR3_INT_DECL(int)             HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
     131VMMR3_INT_DECL(VBOXSTRICTRC)    HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     132VMMR3_INT_DECL(int)             HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
     133VMMR3_INT_DECL(int)             HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
     134VMMR3_INT_DECL(int)             HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     135VMMR3_INT_DECL(bool)            HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
     136VMMR3_INT_DECL(bool)            HMR3IsVmxPreemptionTimerUsed(PVM pVM);
    125137
    126138/** @} */
    … …  
    131143 * @{
    132144 */
    133 VMMR0DECL(int)          HMR0SetupVM(PVM pVM);
    134 VMMR0DECL(int)          HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
    135 VMMR0DECL(int)          HMR0Enter(PVM pVM, PVMCPU pVCpu);
    136 VMMR0DECL(int)          HMR0Leave(PVM pVM, PVMCPU pVCpu);
    137 VMMR0DECL(int)          HMR0InvalidatePage(PVM pVM, PVMCPU pVCpu);
    138 VMMR0DECL(int)          HMR0FlushTLB(PVM pVM);
    139 VMMR0DECL(bool)         HMR0SuspendPending(void);
     145VMMR0_INT_DECL(int)             HMR0SetupVM(PVM pVM);
     146VMMR0_INT_DECL(int)             HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
     147VMMR0_INT_DECL(int)             HMR0Enter(PVM pVM, PVMCPU pVCpu);
     148VMMR0_INT_DECL(int)             HMR0Leave(PVM pVM, PVMCPU pVCpu);
     149VMMR0_INT_DECL(bool)            HMR0SuspendPending(void);
    140150
    141151# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
    142 VMMR0DECL(int)          HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    143 VMMR0DECL(int)          HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    144 VMMR0DECL(int)          HMR0TestSwitcher3264(PVM pVM);
     152VMMR0_INT_DECL(int)             HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     153VMMR0_INT_DECL(int)             HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     154VMMR0_INT_DECL(int)             HMR0TestSwitcher3264(PVM pVM);
    145155# endif
    146156
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