Index: trunk/include/VBox/vmm/csam.h
===================================================================
--- trunk/include/VBox/vmm/csam.h	(revision 44362)
+++ trunk/include/VBox/vmm/csam.h	(revision 44373)
@@ -152,11 +152,5 @@
  */
 
-/**
- * Query CSAM state (enabled/disabled)
- *
- * @returns 0 - disabled, 1 - enabled
- * @param   pVM         The VM to operate on.
- */
-VMMR3DECL(int) CSAMR3IsEnabled(PVM pVM);
+VMMR3DECL(bool) CSAMR3IsEnabled(PUVM pUVM);
 
 /**
Index: trunk/include/VBox/vmm/dbgf.h
===================================================================
--- trunk/include/VBox/vmm/dbgf.h	(revision 44362)
+++ trunk/include/VBox/vmm/dbgf.h	(revision 44373)
@@ -300,4 +300,5 @@
 VMMR3DECL(int)  DBGFR3Step(PVM pVM, VMCPUID idCpu);
 VMMR3DECL(int)  DBGFR3PrgStep(PVMCPU pVCpu);
+VMMR3DECL(int)  DBGFR3InjectNMI(PUVM pUVM, VMCPUID idCpu);
 
 #endif /* IN_RING3 */
Index: trunk/include/VBox/vmm/em.h
===================================================================
--- trunk/include/VBox/vmm/em.h	(revision 44362)
+++ trunk/include/VBox/vmm/em.h	(revision 44373)
@@ -225,4 +225,8 @@
  * @{
  */
+
+VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM);
+VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM);
+
 VMMR3DECL(int)          EMR3Init(PVM pVM);
 VMMR3DECL(void)         EMR3Relocate(PVM pVM);
Index: trunk/include/VBox/vmm/hm.h
===================================================================
--- trunk/include/VBox/vmm/hm.h	(revision 44362)
+++ trunk/include/VBox/vmm/hm.h	(revision 44373)
@@ -1,8 +1,8 @@
 /** @file
- * HM - Intel/AMD VM Hardware Support Manager (VMM)
+ * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
  */
 
 /*
- * Copyright (C) 2006-2010 Oracle Corporation
+ * Copyright (C) 2006-2013 Oracle Corporation
  *
  * This file is part of VirtualBox Open Source Edition (OSE), as
@@ -43,7 +43,8 @@
  *
  * @returns 0 - disabled, 1 - enabled
- * @param   pVM         The VM to operate on.
+ * @param   a_pVM       Pointer to the shared VM structure.
+ * @internal
  */
-#define HMIsEnabled(pVM)    ((pVM)->fHMEnabled)
+#define HMIsEnabled(a_pVM)    ((a_pVM)->fHMEnabled)
 
  /**
@@ -51,22 +52,30 @@
  *
  * @returns boolean
- * @param   pCtx        CPU context
+ * @param   a_pVCpu     Pointer to the shared virtual CPU structure.
+ * @internal
  */
-#define HMCanEmulateIoBlock(pVCpu)     (!CPUMIsGuestInPagedProtectedMode(pVCpu))
-#define HMCanEmulateIoBlockEx(pCtx)    (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
+#define HMCanEmulateIoBlock(a_pVCpu)     (!CPUMIsGuestInPagedProtectedMode(a_pVCpu))
 
-VMMDECL(int)            HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
-VMMDECL(bool)           HMHasPendingIrq(PVM pVM);
-VMMDECL(PX86PDPE)       HMGetPaePdpes(PVMCPU pVCpu);
+ /**
+ * Check if the current CPU state is valid for emulating IO blocks in the recompiler
+ *
+ * @returns boolean
+ * @param   a_pCtx      Pointer to the CPU context (within PVM).
+ * @internal
+ */
+#define HMCanEmulateIoBlockEx(a_pCtx)   (!CPUMIsGuestInPagedProtectedModeEx(a_pCtx))
+
+VMM_INT_DECL(int)               HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
+VMM_INT_DECL(bool)              HMHasPendingIrq(PVM pVM);
+VMM_INT_DECL(PX86PDPE)          HMGetPaePdpes(PVMCPU pVCpu);
 
 #ifndef IN_RC
-VMMDECL(int)            HMFlushTLB(PVMCPU pVCpu);
-VMMDECL(int)            HMFlushTLBOnAllVCpus(PVM pVM);
-VMMDECL(int)            HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
-VMMDECL(int)            HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
-VMMDECL(bool)           HMIsNestedPagingActive(PVM pVM);
-VMMDECL(PGMMODE)        HMGetShwPagingMode(PVM pVM);
-#else
-/* Nop in GC */
+VMM_INT_DECL(int)               HMFlushTLB(PVMCPU pVCpu);
+VMM_INT_DECL(int)               HMFlushTLBOnAllVCpus(PVM pVM);
+VMM_INT_DECL(int)               HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
+VMM_INT_DECL(int)               HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
+VMM_INT_DECL(bool)              HMIsNestedPagingActive(PVM pVM);
+VMM_INT_DECL(PGMMODE)           HMGetShwPagingMode(PVM pVM);
+#else /* Nops in RC: */
 # define HMFlushTLB(pVCpu)                  do { } while (0)
 # define HMIsNestedPagingActive(pVM)        false
@@ -79,14 +88,16 @@
  * @{
  */
-VMMR0DECL(int)          HMR0Init(void);
-VMMR0DECL(int)          HMR0Term(void);
-VMMR0DECL(int)          HMR0InitVM(PVM pVM);
-VMMR0DECL(int)          HMR0TermVM(PVM pVM);
-VMMR0DECL(int)          HMR0EnableAllCpus(PVM pVM);
-VMMR0DECL(int)          HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
-VMMR0DECL(void)         HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
+VMMR0_INT_DECL(int)             HMR0Init(void);
+VMMR0_INT_DECL(int)             HMR0Term(void);
+VMMR0_INT_DECL(int)             HMR0InitVM(PVM pVM);
+VMMR0_INT_DECL(int)             HMR0TermVM(PVM pVM);
+VMMR0_INT_DECL(int)             HMR0EnableAllCpus(PVM pVM);
+VMMR0_INT_DECL(int)             HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
+VMMR0_INT_DECL(void)            HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
 
-VMMR0DECL(void)         HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize);
-VMMR0DECL(void)         HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize);
+VMMR0_INT_DECL(void)            HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
+                                                           unsigned uPort, unsigned uAndVal, unsigned cbSize);
+VMMR0_INT_DECL(void)            HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
+                                                          unsigned uPort, unsigned uAndVal, unsigned cbSize);
 
 /** @} */
@@ -99,28 +110,29 @@
  * @{
  */
-VMMR3DECL(bool)         HMR3IsEventPending(PVMCPU pVCpu);
-VMMR3DECL(int)          HMR3Init(PVM pVM);
-VMMR3_INT_DECL(int)     HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
-VMMR3DECL(void)         HMR3Relocate(PVM pVM);
-VMMR3DECL(int)          HMR3Term(PVM pVM);
-VMMR3DECL(void)         HMR3Reset(PVM pVM);
-VMMR3DECL(void)         HMR3ResetCpu(PVMCPU pVCpu);
-VMMR3DECL(void)         HMR3CheckError(PVM pVM, int iStatusCode);
-VMMR3DECL(bool)         HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
-VMMR3DECL(void)         HMR3NotifyScheduled(PVMCPU pVCpu);
-VMMR3DECL(void)         HMR3NotifyEmulated(PVMCPU pVCpu);
-VMMR3DECL(bool)         HMR3IsActive(PVMCPU pVCpu);
-VMMR3DECL(bool)         HMR3IsNestedPagingActive(PVM pVM);
-VMMR3DECL(bool)         HMR3IsAllowed(PVM pVM);
-VMMR3DECL(void)         HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
-VMMR3DECL(bool)         HMR3IsVPIDActive(PVM pVM);
-VMMR3DECL(int)          HMR3InjectNMI(PVM pVM);
-VMMR3DECL(int)          HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
-VMMR3DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
-VMMR3DECL(int)          HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
-VMMR3DECL(int)          HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
-VMMR3DECL(int)          HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
-VMMR3DECL(bool)         HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
-VMMR3DECL(bool)         HMR3IsVmxPreemptionTimerUsed(PVM pVM);
+VMMR3DECL(bool)                 HMR3IsEnabled(PUVM pUVM);
+VMMR3DECL(bool)                 HMR3IsNestedPagingActive(PUVM pUVM);
+VMMR3DECL(bool)                 HMR3IsVpidActive(PUVM pVUM);
+
+VMMR3_INT_DECL(bool)            HMR3IsEventPending(PVMCPU pVCpu);
+VMMR3_INT_DECL(int)             HMR3Init(PVM pVM);
+VMMR3_INT_DECL(int)             HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
+VMMR3_INT_DECL(void)            HMR3Relocate(PVM pVM);
+VMMR3_INT_DECL(int)             HMR3Term(PVM pVM);
+VMMR3_INT_DECL(void)            HMR3Reset(PVM pVM);
+VMMR3_INT_DECL(void)            HMR3ResetCpu(PVMCPU pVCpu);
+VMMR3_INT_DECL(void)            HMR3CheckError(PVM pVM, int iStatusCode);
+VMMR3DECL(bool)                 HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
+VMMR3_INT_DECL(void)            HMR3NotifyScheduled(PVMCPU pVCpu);
+VMMR3_INT_DECL(void)            HMR3NotifyEmulated(PVMCPU pVCpu);
+VMMR3_INT_DECL(bool)            HMR3IsActive(PVMCPU pVCpu);
+VMMR3_INT_DECL(bool)            HMR3IsAllowed(PVM pVM);
+VMMR3_INT_DECL(void)            HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
+VMMR3_INT_DECL(int)             HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
+VMMR3_INT_DECL(VBOXSTRICTRC)    HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR3_INT_DECL(int)             HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
+VMMR3_INT_DECL(int)             HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
+VMMR3_INT_DECL(int)             HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR3_INT_DECL(bool)            HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
+VMMR3_INT_DECL(bool)            HMR3IsVmxPreemptionTimerUsed(PVM pVM);
 
 /** @} */
@@ -131,16 +143,14 @@
  * @{
  */
-VMMR0DECL(int)          HMR0SetupVM(PVM pVM);
-VMMR0DECL(int)          HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
-VMMR0DECL(int)          HMR0Enter(PVM pVM, PVMCPU pVCpu);
-VMMR0DECL(int)          HMR0Leave(PVM pVM, PVMCPU pVCpu);
-VMMR0DECL(int)          HMR0InvalidatePage(PVM pVM, PVMCPU pVCpu);
-VMMR0DECL(int)          HMR0FlushTLB(PVM pVM);
-VMMR0DECL(bool)         HMR0SuspendPending(void);
+VMMR0_INT_DECL(int)             HMR0SetupVM(PVM pVM);
+VMMR0_INT_DECL(int)             HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
+VMMR0_INT_DECL(int)             HMR0Enter(PVM pVM, PVMCPU pVCpu);
+VMMR0_INT_DECL(int)             HMR0Leave(PVM pVM, PVMCPU pVCpu);
+VMMR0_INT_DECL(bool)            HMR0SuspendPending(void);
 
 # if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
-VMMR0DECL(int)          HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
-VMMR0DECL(int)          HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
-VMMR0DECL(int)          HMR0TestSwitcher3264(PVM pVM);
+VMMR0_INT_DECL(int)             HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR0_INT_DECL(int)             HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMR0_INT_DECL(int)             HMR0TestSwitcher3264(PVM pVM);
 # endif
 
