VirtualBox

Changeset 44508 in vbox for trunk/src/VBox/Devices/Bus


Ignore:
Timestamp:
Feb 1, 2013 12:46:33 PM (12 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
83544
Message:

Drop the pfnSaveExecR3 and pfnLoadExecR3 interfaces of the PCI buses (never used). Synced pciR3CommonRestoreConfig between the two PCI buses, dropping the constants in the table as they make double checking sizes and offsets harder. Also removing the pfnIOCtl device registration structure member, putting a pfnReserved in it's place.

Location:
trunk/src/VBox/Devices/Bus
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r44506 r44508  
    4545*******************************************************************************/
    4646#define LOG_GROUP LOG_GROUP_DEV_PCI
    47 /* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
     47/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
    4848#define PCI_INCLUDE_PRIVATE
    4949#include <VBox/pci.h>
    … …  
    12421242
    12431243/**
    1244  * Saves a state of the PCI device.
    1245  *
    1246  * @returns VBox status code.
    1247  * @param   pDevIns         Device instance of the PCI Bus.
    1248  * @param   pPciDev         Pointer to PCI device.
    1249  * @param   pSSM            The handle to save the state to.
    1250  */
    1251 static DECLCALLBACK(int) pciR3GenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
    1252 {
    1253     NOREF(pDevIns);
    1254     return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
    1255 }
    1256 
    1257 
    1258 /**
    1259  * Loads a saved PCI device state.
    1260  *
    1261  * @returns VBox status code.
    1262  * @param   pDevIns         Device instance of the PCI Bus.
    1263  * @param   pPciDev         Pointer to PCI device.
    1264  * @param   pSSM            The handle to the saved state.
    1265  */
    1266 static DECLCALLBACK(int) pciR3GenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
    1267 {
    1268     NOREF(pDevIns);
    1269     return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
    1270 }
    1271 
    1272 
    1273 /**
    12741244 * Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
    12751245 *
    … …  
    13691339        { 0x0a, 1, 0, 3, "CLASS_SUB" },
    13701340        { 0x0b, 1, 0, 3, "CLASS_BASE" },
    1371         { 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" },   // fWritable = ??
    1372         { 0x0d, 1, 0, 3, "LATENCY_TIMER" },     // fWritable = ??
    1373         { 0x0e, 1, 0, 3, "HEADER_TYPE" },       // fWritable = ??
    1374         { 0x0f, 1, 0, 3, "BIST" },              // fWritable = ??
     1341        { 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },   
     1342        { 0x0d, 1, 1, 3, "LATENCY_TIMER" },     
     1343        { 0x0e, 1, 0, 3, "HEADER_TYPE" },
     1344        { 0x0f, 1, 1, 3, "BIST" },             
    13751345        { 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
    13761346        { 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
    … …  
    13991369        { 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" },  // fWritable = ?!
    14001370        { 0x34, 4, 0, 3, "CAPABILITY_LIST" },   // fWritable = !? cb=!?
    1401         { 0x38, 4, 1, 1, "???" },               // ???
     1371        { 0x38, 4, 1, 1, "RESERVED_38" },       // ???
    14021372        { 0x38, 4, 1, 2, "ROM_ADDRESS_BR" },    // fWritable = !? cb=!? fBridge=!?
    14031373        { 0x3c, 1, 1, 3, "INTERRUPT_LINE" },    // fBridge=??
    14041374        { 0x3d, 1, 0, 3, "INTERRUPT_PIN" },     // fBridge=??
    1405         { 0x3e, 1, 0, 1, "MIN_GNT" },           // fWritable = !?
    1406         { 0x3e, 1, 1, 2, "BRIDGE_CONTROL" },    // fWritable = !? cb=!?
    1407         { 0x3f, 1, 1, 3, "MAX_LAT" },           // fWritable = !? fBridge=!?
     1375        { 0x3e, 1, 0, 1, "MIN_GNT" },
     1376        { 0x3e, 2, 1, 2, "BRIDGE_CONTROL" },    // fWritable = !?
     1377        { 0x3f, 1, 0, 1, "MAX_LAT" },
    14081378        /* The COMMAND register must come last as it requires the *ADDRESS*
    14091379           registers to be restored before we pretent to change it from 0 to
    … …  
    22232193    PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
    22242194    PciBusReg.pfnSetIrqR3             = pciSetIrq;
    2225     PciBusReg.pfnSaveExecR3           = pciR3GenericSaveExec;
    2226     PciBusReg.pfnLoadExecR3           = pciR3GenericLoadExec;
    22272195    PciBusReg.pfnFakePCIBIOSR3        = pciR3FakePCIBIOS;
    22282196    PciBusReg.pszSetIrqRC             = fGCEnabled ? "pciSetIrq" : NULL;
    … …  
    26112579    PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
    26122580    PciBusReg.pfnSetIrqR3             = pcibridgeSetIrq;
    2613     PciBusReg.pfnSaveExecR3           = pciR3GenericSaveExec;
    2614     PciBusReg.pfnLoadExecR3           = pciR3GenericLoadExec;
    26152581    PciBusReg.pfnFakePCIBIOSR3        = NULL; /* Only needed for the first bus. */
    26162582    PciBusReg.pszSetIrqRC             = fGCEnabled ? "pcibridgeSetIrq" : NULL;

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r43441 r44508  
    55
    66/*
    7  * Copyright (C) 2010-2011 Oracle Corporation
     7 * Copyright (C) 2010-2013 Oracle Corporation
    88 *
    99 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    2020*******************************************************************************/
    2121#define LOG_GROUP LOG_GROUP_DEV_PCI
    22 /* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
     22/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
    2323#define PCI_INCLUDE_PRIVATE
    2424#define PCIBus ICH9PCIBus
    … …  
    3434
    3535#include "VBoxDD.h"
    36 
    3736#include "MsiCommon.h"
    3837
    … …  
    970969}
    971970
    972 /**
    973  * Saves a state of the PCI device.
    974  *
    975  * @returns VBox status code.
    976  * @param   pDevIns         Device instance of the PCI Bus.
    977  * @param   pPciDev         Pointer to PCI device.
    978  * @param   pSSM            The handle to save the state to.
    979  */
    980 static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
    981 {
    982     NOREF(pDevIns);
    983     Assert(!pciDevIsPassthrough(pPciDev));
    984     return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
    985 }
    986 
    987971static int ich9pciR3CommonSaveExec(PICH9PCIBUS pBus, PSSMHANDLE pSSM)
    988972{
    … …  
    11531137    {
    11541138        /* off,cb,fW,fB, pszName */
    1155         { VBOX_PCI_VENDOR_ID, 2, 0, 3, "VENDOR_ID" },
    1156         { VBOX_PCI_DEVICE_ID, 2, 0, 3, "DEVICE_ID" },
    1157         { VBOX_PCI_STATUS, 2, 1, 3, "STATUS" },
    1158         { VBOX_PCI_REVISION_ID, 1, 0, 3, "REVISION_ID" },
    1159         { VBOX_PCI_CLASS_PROG, 1, 0, 3, "CLASS_PROG" },
    1160         { VBOX_PCI_CLASS_SUB, 1, 0, 3, "CLASS_SUB" },
    1161         { VBOX_PCI_CLASS_BASE, 1, 0, 3, "CLASS_BASE" },
    1162         { VBOX_PCI_CACHE_LINE_SIZE, 1, 1, 3, "CACHE_LINE_SIZE" },
    1163         { VBOX_PCI_LATENCY_TIMER, 1, 1, 3, "LATENCY_TIMER" },
    1164         { VBOX_PCI_HEADER_TYPE, 1, 0, 3, "HEADER_TYPE" },
    1165         { VBOX_PCI_BIST, 1, 1, 3, "BIST" },
    1166         { VBOX_PCI_BASE_ADDRESS_0, 4, 1, 3, "BASE_ADDRESS_0" },
    1167         { VBOX_PCI_BASE_ADDRESS_1, 4, 1, 3, "BASE_ADDRESS_1" },
    1168         { VBOX_PCI_BASE_ADDRESS_2, 4, 1, 1, "BASE_ADDRESS_2" },
    1169         { VBOX_PCI_PRIMARY_BUS, 1, 1, 2, "PRIMARY_BUS" },       // fWritable = ??
    1170         { VBOX_PCI_SECONDARY_BUS, 1, 1, 2, "SECONDARY_BUS" },     // fWritable = ??
    1171         { VBOX_PCI_SUBORDINATE_BUS, 1, 1, 2, "SUBORDINATE_BUS" },   // fWritable = ??
    1172         { VBOX_PCI_SEC_LATENCY_TIMER, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
    1173         { VBOX_PCI_BASE_ADDRESS_3, 4, 1, 1, "BASE_ADDRESS_3" },
    1174         { VBOX_PCI_IO_BASE, 1, 1, 2, "IO_BASE" },           // fWritable = ??
    1175         { VBOX_PCI_IO_LIMIT, 1, 1, 2, "IO_LIMIT" },          // fWritable = ??
    1176         { VBOX_PCI_SEC_STATUS, 2, 1, 2, "SEC_STATUS" },        // fWritable = ??
    1177         { VBOX_PCI_BASE_ADDRESS_4, 4, 1, 1, "BASE_ADDRESS_4" },
    1178         { VBOX_PCI_MEMORY_BASE, 2, 1, 2, "MEMORY_BASE" },       // fWritable = ??
    1179         { VBOX_PCI_MEMORY_LIMIT, 2, 1, 2, "MEMORY_LIMIT" },      // fWritable = ??
    1180         { VBOX_PCI_BASE_ADDRESS_5, 4, 1, 1, "BASE_ADDRESS_5" },
    1181         { VBOX_PCI_PREF_MEMORY_BASE, 2, 1, 2, "PREF_MEMORY_BASE" },  // fWritable = ??
    1182         { VBOX_PCI_PREF_MEMORY_LIMIT, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
    1183         { VBOX_PCI_CARDBUS_CIS, 4, 1, 1, "CARDBUS_CIS" },       // fWritable = ??
    1184         { VBOX_PCI_PREF_BASE_UPPER32, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
    1185         { VBOX_PCI_SUBSYSTEM_VENDOR_ID, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
    1186         { VBOX_PCI_PREF_LIMIT_UPPER32, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
    1187         { VBOX_PCI_SUBSYSTEM_ID, 2, 0, 1, "SUBSYSTEM_ID" },      // fWritable = !?
    1188         { VBOX_PCI_ROM_ADDRESS, 4, 1, 1, "ROM_ADDRESS" },       // fWritable = ?!
    1189         { VBOX_PCI_IO_BASE_UPPER16, 2, 1, 2, "IO_BASE_UPPER16" },   // fWritable = ?!
    1190         { VBOX_PCI_IO_LIMIT_UPPER16, 2, 1, 2, "IO_LIMIT_UPPER16" },  // fWritable = ?!
    1191         { VBOX_PCI_CAPABILITY_LIST, 4, 0, 3, "CAPABILITY_LIST" },   // fWritable = !? cb=!?
    1192         { VBOX_PCI_RESERVED_38, 4, 1, 1, "RESERVED_38" },               // ???
    1193         { VBOX_PCI_ROM_ADDRESS_BR, 4, 1, 2, "ROM_ADDRESS_BR" },    // fWritable = !? cb=!? fBridge=!?
    1194         { VBOX_PCI_INTERRUPT_LINE, 1, 1, 3, "INTERRUPT_LINE" },    // fBridge=??
    1195         { VBOX_PCI_INTERRUPT_PIN, 1, 0, 3, "INTERRUPT_PIN" },     // fBridge=??
    1196         { VBOX_PCI_MIN_GNT, 1, 0, 1, "MIN_GNT" },
    1197         { VBOX_PCI_BRIDGE_CONTROL, 2, 1, 2, "BRIDGE_CONTROL" },    // fWritable = !?
    1198         { VBOX_PCI_MAX_LAT, 1, 0, 1, "MAX_LAT" },
     1139        { 0x00, 2, 0, 3, "VENDOR_ID" },
     1140        { 0x02, 2, 0, 3, "DEVICE_ID" },
     1141        { 0x06, 2, 1, 3, "STATUS" },
     1142        { 0x08, 1, 0, 3, "REVISION_ID" },
     1143        { 0x09, 1, 0, 3, "CLASS_PROG" },
     1144        { 0x0a, 1, 0, 3, "CLASS_SUB" },
     1145        { 0x0b, 1, 0, 3, "CLASS_BASE" },
     1146        { 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
     1147        { 0x0d, 1, 1, 3, "LATENCY_TIMER" },
     1148        { 0x0e, 1, 0, 3, "HEADER_TYPE" },
     1149        { 0x0f, 1, 1, 3, "BIST" },
     1150        { 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
     1151        { 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
     1152        { 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
     1153        { 0x18, 1, 1, 2, "PRIMARY_BUS" },       // fWritable = ??
     1154        { 0x19, 1, 1, 2, "SECONDARY_BUS" },     // fWritable = ??
     1155        { 0x1a, 1, 1, 2, "SUBORDINATE_BUS" },   // fWritable = ??
     1156        { 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
     1157        { 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
     1158        { 0x1c, 1, 1, 2, "IO_BASE" },           // fWritable = ??
     1159        { 0x1d, 1, 1, 2, "IO_LIMIT" },          // fWritable = ??
     1160        { 0x1e, 2, 1, 2, "SEC_STATUS" },        // fWritable = ??
     1161        { 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
     1162        { 0x20, 2, 1, 2, "MEMORY_BASE" },       // fWritable = ??
     1163        { 0x22, 2, 1, 2, "MEMORY_LIMIT" },      // fWritable = ??
     1164        { 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
     1165        { 0x24, 2, 1, 2, "PREF_MEMORY_BASE" },  // fWritable = ??
     1166        { 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
     1167        { 0x28, 4, 1, 1, "CARDBUS_CIS" },       // fWritable = ??
     1168        { 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
     1169        { 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
     1170        { 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
     1171        { 0x2e, 2, 0, 1, "SUBSYSTEM_ID" },      // fWritable = !?
     1172        { 0x30, 4, 1, 1, "ROM_ADDRESS" },       // fWritable = ?!
     1173        { 0x30, 2, 1, 2, "IO_BASE_UPPER16" },   // fWritable = ?!
     1174        { 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" },  // fWritable = ?!
     1175        { 0x34, 4, 0, 3, "CAPABILITY_LIST" },   // fWritable = !? cb=!?
     1176        { 0x38, 4, 1, 1, "RESERVED_38" },       // ???
     1177        { 0x38, 4, 1, 2, "ROM_ADDRESS_BR" },    // fWritable = !? cb=!? fBridge=!?
     1178        { 0x3c, 1, 1, 3, "INTERRUPT_LINE" },    // fBridge=??
     1179        { 0x3d, 1, 0, 3, "INTERRUPT_PIN" },     // fBridge=??
     1180        { 0x3e, 1, 0, 1, "MIN_GNT" },
     1181        { 0x3e, 2, 1, 2, "BRIDGE_CONTROL" },    // fWritable = !?
     1182        { 0x3f, 1, 0, 1, "MAX_LAT" },
    11991183        /* The COMMAND register must come last as it requires the *ADDRESS*
    12001184           registers to be restored before we pretent to change it from 0 to
    12011185           whatever value the guest assigned it. */
    1202         { VBOX_PCI_COMMAND, 2, 1, 3, "COMMAND" },
     1186        { 0x04, 2, 1, 3, "COMMAND" },
    12031187    };
    12041188
    … …  
    14431427
    14441428    return rc;
    1445 }
    1446 
    1447 /**
    1448  * Loads a saved PCI device state.
    1449  *
    1450  * @returns VBox status code.
    1451  * @param   pDevIns         Device instance of the PCI Bus.
    1452  * @param   pPciDev         Pointer to PCI device.
    1453  * @param   pSSM            The handle to the saved state.
    1454  */
    1455 static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
    1456 {
    1457     NOREF(pDevIns);
    1458     Assert(!pciDevIsPassthrough(pPciDev));
    1459     return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
    14601429}
    14611430
    … …  
    24632432    PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
    24642433    PciBusReg.pfnSetIrqR3             = ich9pciSetIrq;
    2465     PciBusReg.pfnSaveExecR3           = ich9pciGenericSaveExec;
    2466     PciBusReg.pfnLoadExecR3           = ich9pciGenericLoadExec;
    24672434    PciBusReg.pfnFakePCIBIOSR3        = ich9pciFakePCIBIOS;
    24682435    PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pciSetIrq" : NULL;
    … …  
    27062673    PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
    27072674    PciBusReg.pfnSetIrqR3             = ich9pcibridgeSetIrq;
    2708     PciBusReg.pfnSaveExecR3           = ich9pciGenericSaveExec;
    2709     PciBusReg.pfnLoadExecR3           = ich9pciGenericLoadExec;
    27102675    PciBusReg.pfnFakePCIBIOSR3        = NULL; /* Only needed for the first bus. */
    27112676    PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
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