Changeset 44540 in vbox
- Timestamp:
- Feb 5, 2013 1:02:18 PM (12 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Network/DevE1000.cpp (modified) (31 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Network/DevE1000.cpp
r44537 r44540 209 209 210 210 #ifdef E1K_INT_STATS 211 # define E1K_INC_ISTAT_CNT(cnt) ++cnt211 # define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0) 212 212 #else /* E1K_INT_STATS */ 213 # define E1K_INC_ISTAT_CNT(cnt) 213 # define E1K_INC_ISTAT_CNT(cnt) do { } while (0) 214 214 #endif /* E1K_INT_STATS */ 215 215 … … 263 263 #define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0) 264 264 265 #define CTRL_SLU 0x00000040266 #define CTRL_MDIO 0x00100000267 #define CTRL_MDC 0x00200000268 #define CTRL_MDIO_DIR 0x01000000269 #define CTRL_MDC_DIR 0x02000000270 #define CTRL_RESET 0x04000000271 #define CTRL_VME 0x40000000272 273 #define STATUS_LU 0x00000002274 #define STATUS_TXOFF 0x00000010275 276 #define EECD_EE_WIRES 0x0F277 #define EECD_EE_REQ 0x40278 #define EECD_EE_GNT 0x80279 280 #define EERD_START 0x00000001281 #define EERD_DONE 0x00000010282 #define EERD_DATA_MASK 0xFFFF0000283 #define EERD_DATA_SHIFT 16284 #define EERD_ADDR_MASK 0x0000FF00285 #define EERD_ADDR_SHIFT 8286 287 #define MDIC_DATA_MASK 0x0000FFFF288 #define MDIC_DATA_SHIFT 0289 #define MDIC_REG_MASK 0x001F0000290 #define MDIC_REG_SHIFT 16291 #define MDIC_PHY_MASK 0x03E00000292 #define MDIC_PHY_SHIFT 21293 #define MDIC_OP_WRITE 0x04000000294 #define MDIC_OP_READ 0x08000000295 #define MDIC_READY 0x10000000296 #define MDIC_INT_EN 0x20000000297 #define MDIC_ERROR 0x40000000298 299 #define TCTL_EN 0x00000002300 #define TCTL_PSP 0x00000008301 302 #define RCTL_EN 0x00000002303 #define RCTL_UPE 0x00000008304 #define RCTL_MPE 0x00000010305 #define RCTL_LPE 0x00000020306 #define RCTL_LBM_MASK 0x000000C0307 #define RCTL_LBM_SHIFT 6308 #define RCTL_RDMTS_MASK 0x00000300309 #define RCTL_RDMTS_SHIFT 8310 #define RCTL_LBM_TCVR 3/**< PHY or external SerDes loopback. */311 #define RCTL_MO_MASK 0x00003000312 #define RCTL_MO_SHIFT 12313 #define RCTL_BAM 0x00008000314 #define RCTL_BSIZE_MASK 0x00030000315 #define RCTL_BSIZE_SHIFT 16316 #define RCTL_VFE 0x00040000317 #define RCTL_CFIEN 0x00080000318 #define RCTL_CFI 0x00100000319 #define RCTL_BSEX 0x02000000320 #define RCTL_SECRC 0x04000000321 322 #define ICR_TXDW 0x00000001323 #define ICR_TXQE 0x00000002324 #define ICR_LSC 0x00000004325 #define ICR_RXDMT0 0x00000010326 #define ICR_RXT0 0x00000080327 #define ICR_TXD_LOW 0x00008000328 #define RDTR_FPD 0x80000000265 #define CTRL_SLU UINT32_C(0x00000040) 266 #define CTRL_MDIO UINT32_C(0x00100000) 267 #define CTRL_MDC UINT32_C(0x00200000) 268 #define CTRL_MDIO_DIR UINT32_C(0x01000000) 269 #define CTRL_MDC_DIR UINT32_C(0x02000000) 270 #define CTRL_RESET UINT32_C(0x04000000) 271 #define CTRL_VME UINT32_C(0x40000000) 272 273 #define STATUS_LU UINT32_C(0x00000002) 274 #define STATUS_TXOFF UINT32_C(0x00000010) 275 276 #define EECD_EE_WIRES UINT32_C(0x0F) 277 #define EECD_EE_REQ UINT32_C(0x40) 278 #define EECD_EE_GNT UINT32_C(0x80) 279 280 #define EERD_START UINT32_C(0x00000001) 281 #define EERD_DONE UINT32_C(0x00000010) 282 #define EERD_DATA_MASK UINT32_C(0xFFFF0000) 283 #define EERD_DATA_SHIFT 16 284 #define EERD_ADDR_MASK UINT32_C(0x0000FF00) 285 #define EERD_ADDR_SHIFT 8 286 287 #define MDIC_DATA_MASK UINT32_C(0x0000FFFF) 288 #define MDIC_DATA_SHIFT 0 289 #define MDIC_REG_MASK UINT32_C(0x001F0000) 290 #define MDIC_REG_SHIFT 16 291 #define MDIC_PHY_MASK UINT32_C(0x03E00000) 292 #define MDIC_PHY_SHIFT 21 293 #define MDIC_OP_WRITE UINT32_C(0x04000000) 294 #define MDIC_OP_READ UINT32_C(0x08000000) 295 #define MDIC_READY UINT32_C(0x10000000) 296 #define MDIC_INT_EN UINT32_C(0x20000000) 297 #define MDIC_ERROR UINT32_C(0x40000000) 298 299 #define TCTL_EN UINT32_C(0x00000002) 300 #define TCTL_PSP UINT32_C(0x00000008) 301 302 #define RCTL_EN UINT32_C(0x00000002) 303 #define RCTL_UPE UINT32_C(0x00000008) 304 #define RCTL_MPE UINT32_C(0x00000010) 305 #define RCTL_LPE UINT32_C(0x00000020) 306 #define RCTL_LBM_MASK UINT32_C(0x000000C0) 307 #define RCTL_LBM_SHIFT 6 308 #define RCTL_RDMTS_MASK UINT32_C(0x00000300) 309 #define RCTL_RDMTS_SHIFT 8 310 #define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */ 311 #define RCTL_MO_MASK UINT32_C(0x00003000) 312 #define RCTL_MO_SHIFT 12 313 #define RCTL_BAM UINT32_C(0x00008000) 314 #define RCTL_BSIZE_MASK UINT32_C(0x00030000) 315 #define RCTL_BSIZE_SHIFT 16 316 #define RCTL_VFE UINT32_C(0x00040000) 317 #define RCTL_CFIEN UINT32_C(0x00080000) 318 #define RCTL_CFI UINT32_C(0x00100000) 319 #define RCTL_BSEX UINT32_C(0x02000000) 320 #define RCTL_SECRC UINT32_C(0x04000000) 321 322 #define ICR_TXDW UINT32_C(0x00000001) 323 #define ICR_TXQE UINT32_C(0x00000002) 324 #define ICR_LSC UINT32_C(0x00000004) 325 #define ICR_RXDMT0 UINT32_C(0x00000010) 326 #define ICR_RXT0 UINT32_C(0x00000080) 327 #define ICR_TXD_LOW UINT32_C(0x00008000) 328 #define RDTR_FPD UINT32_C(0x80000000) 329 329 330 330 #define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX)) … … 342 342 #define TXDCTL_LWTHRESH_SHIFT 25 343 343 344 #define RXCSUM_PCSS_MASK 0x000000FF 345 #define RXCSUM_PCSS_SHIFT 0 346 347 /* Register access macros ****************************************************/ 344 #define RXCSUM_PCSS_MASK UINT32_C(0x000000FF) 345 #define RXCSUM_PCSS_SHIFT 0 346 347 /** @name Register access macros 348 * @{ */ 348 349 #define CTRL pState->auRegs[CTRL_IDX] 349 350 #define STATUS pState->auRegs[STATUS_IDX] … … 467 468 #define IPAV pState->auRegs[IPAV_IDX] 468 469 #define WUPL pState->auRegs[WUPL_IDX] 469 470 /** 471 * Indices of memory-mapped registers in register table 470 /** @} */ 471 472 /** 473 * Indices of memory-mapped registers in register table. 472 474 */ 473 475 typedef enum … … 616 618 * Define E1000-specific EEPROM layout. 617 619 */ 618 classE1kEEPROM620 struct E1kEEPROM 619 621 { 620 622 public: … … 922 924 AssertCompileSize(E1KRA, 8*16); 923 925 924 #define E1K_IP_RF 0x8000 /*reserved fragment flag */925 #define E1K_IP_DF 0x4000 /*dont fragment flag */926 #define E1K_IP_MF 0x2000 /*more fragments flag */927 #define E1K_IP_OFFMASK 0x1fff /*mask for fragmenting bits */926 #define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */ 927 #define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */ 928 #define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */ 929 #define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */ 928 930 929 931 /** @todo use+extend RTNETIPV4 */ … … 949 951 AssertCompileSize(struct E1kIpHeader, 20); 950 952 951 #define E1K_TCP_FIN 0x01U 952 #define E1K_TCP_SYN 0x02U 953 #define E1K_TCP_RST 0x04U 954 #define E1K_TCP_PSH 0x08U 955 #define E1K_TCP_ACK 0x10U 956 #define E1K_TCP_URG 0x20U 957 #define E1K_TCP_ECE 0x40U 958 #define E1K_TCP_CWR 0x80U 959 960 #define E1K_TCP_FLAGS 0x3fU 953 #define E1K_TCP_FIN UINT16_C(0x01) 954 #define E1K_TCP_SYN UINT16_C(0x02) 955 #define E1K_TCP_RST UINT16_C(0x04) 956 #define E1K_TCP_PSH UINT16_C(0x08) 957 #define E1K_TCP_ACK UINT16_C(0x10) 958 #define E1K_TCP_URG UINT16_C(0x20) 959 #define E1K_TCP_ECE UINT16_C(0x40) 960 #define E1K_TCP_CWR UINT16_C(0x80) 961 #define E1K_TCP_FLAGS UINT16_C(0x3f) 961 962 962 963 /** @todo use+extend RTNETTCP */ … … 977 978 #ifdef E1K_WITH_TXD_CACHE 978 979 /** The current Saved state version. */ 979 # define E1K_SAVEDSTATE_VERSION4980 # define E1K_SAVEDSTATE_VERSION 4 980 981 /** Saved state version for VirtualBox 4.2 with VLAN tag fields. */ 981 # define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3982 # define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3 982 983 #else /* !E1K_WITH_TXD_CACHE */ 983 984 /** The current Saved state version. */ 984 # define E1K_SAVEDSTATE_VERSION3985 # define E1K_SAVEDSTATE_VERSION 3 985 986 #endif /* !E1K_WITH_TXD_CACHE */ 986 987 /** Saved state version for VirtualBox 4.1 and earlier. … … 992 993 993 994 /** 994 * Device state structure. Holds the current state of device. 995 * Device state structure. 996 * 997 * Holds the current state of device. 995 998 * 996 999 * @implements PDMINETWORKDOWN … … 1229 1232 uint32_t uStatInt; 1230 1233 uint32_t uStatIntTry; 1231 int32_tuStatIntLower;1234 uint32_t uStatIntLower; 1232 1235 uint32_t uStatIntDly; 1233 1236 int32_t iStatIntLost; … … 1270 1273 }; 1271 1274 typedef struct E1kState_st E1KSTATE; 1275 /** Pointer to the E1000 device state. */ 1276 typedef E1KSTATE *PE1KSTATE; 1272 1277 1273 1278 #ifndef VBOX_DEVICE_STRUCT_TESTCASE … … 1567 1572 # define e1kCsTxEnter(ps, rc) VINF_SUCCESS 1568 1573 # define e1kCsTxLeave(ps) do { } while (0) 1569 # define e1kCsIsOwner(cs) true1570 1574 #else /* E1K_WITH_TX_CS */ 1571 1575 # define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc) 1572 1576 # define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx) 1573 # define e1kCsIsOwner(cs) PDMCritSectIsOwner(cs)1574 1577 #endif /* E1K_WITH_TX_CS */ 1575 1578 … … 3096 3099 { 3097 3100 E1KSTATE *pState = (E1KSTATE *)pvUser; 3098 Assert( e1kCsIsOwner(&pState->csTx));3101 Assert(PDMCritSectIsOwner(&pState->csTx)); 3099 3102 3100 3103 E1K_INC_ISTAT_CNT(pState->uStatTxDelayExp); … … 3103 3106 if (u64Elapsed > pState->uStatMaxTxDelay) 3104 3107 pState->uStatMaxTxDelay = u64Elapsed; 3105 #endif /* E1K_INT_STATS */3108 #endif 3106 3109 int rc = e1kXmitPending(pState, false /*fOnWorkerThread*/); 3107 3110 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc)); … … 5250 5253 #ifdef E1K_INT_STATS 5251 5254 pState->u64ArmedAt = RTTimeNanoTS(); 5252 #endif /* E1K_INT_STATS */5255 #endif 5253 5256 e1kArmTimer(pState, pState->CTX_SUFF(pTXDTimer), E1K_TX_DELAY); 5254 5257 } … … 5259 5262 /* We failed to enter the TX critical section -- transmit as usual. */ 5260 5263 #endif /* E1K_TX_DELAY */ 5261 # 5264 #ifndef IN_RING3 5262 5265 if (!pState->CTX_SUFF(pDrv)) 5263 5266 { … … 5267 5270 } 5268 5271 else 5269 # 5272 #endif 5270 5273 { 5271 5274 rc = e1kXmitPending(pState, false /*fOnWorkerThread*/); … … 5628 5631 * 5629 5632 * @param pState The device state structure. 5630 * @param uOffsetRegister offset in memory-mapped frame.5633 * @param offReg Register offset in memory-mapped frame. 5631 5634 * @param pv Where to fetch the value. 5632 5635 * @param cb Number of bytes to write. 5633 5636 * @thread EMT 5634 5637 */ 5635 static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void const *pv, unsigned cb)5638 static int e1kRegWrite(E1KSTATE *pState, uint32_t offReg, void const *pv, unsigned cb) 5636 5639 { 5637 5640 int rc = VINF_SUCCESS; 5638 int index = e1kRegLookup(pState, uOffset);5641 int index = e1kRegLookup(pState, offReg); 5639 5642 uint32_t u32; 5640 5643 … … 5648 5651 { 5649 5652 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n", 5650 INSTANCE(pState), uOffset, cb));5653 INSTANCE(pState), offReg, cb)); 5651 5654 return VINF_SUCCESS; 5652 5655 } 5653 if ( uOffset& 3)5656 if (offReg & 3) 5654 5657 { 5655 5658 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n", 5656 INSTANCE(pState), uOffset, cb));5659 INSTANCE(pState), offReg, cb)); 5657 5660 return VINF_SUCCESS; 5658 5661 } … … 5667 5670 */ 5668 5671 E1kLog2(("%s At %08X write %08X to %s (%s)\n", 5669 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));5672 INSTANCE(pState), offReg, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name)); 5670 5673 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS); 5671 5674 if (RT_UNLIKELY(rc != VINF_SUCCESS)) … … 5674 5677 //pState->iStatIntLost += pState->iStatIntLostOne; 5675 5678 //pState->iStatIntLostOne = 0; 5676 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);5679 rc = s_e1kRegMap[index].pfnWrite(pState, offReg, index, u32); 5677 5680 //e1kCsLeave(pState); 5678 5681 } … … 5680 5683 { 5681 5684 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n", 5682 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));5685 INSTANCE(pState), offReg, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name)); 5683 5686 } 5684 5687 } … … 5686 5689 { 5687 5690 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n", 5688 INSTANCE(pState), uOffset, u32));5691 INSTANCE(pState), offReg, u32)); 5689 5692 } 5690 5693 return rc; … … 5710 5713 NOREF(pvUser); 5711 5714 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *); 5712 uint32_t uOffset= GCPhysAddr - pState->addrMMReg;5715 uint32_t offReg = GCPhysAddr - pState->addrMMReg; 5713 5716 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIORead), a); 5714 5717 5715 Assert( uOffset< E1K_MM_SIZE);5716 5717 int rc = e1kRegRead(pState, uOffset, pv, cb);5718 Assert(offReg < E1K_MM_SIZE); 5719 5720 int rc = e1kRegRead(pState, offReg, pv, cb); 5718 5721 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIORead), a); 5719 5722 return rc; … … 5736 5739 NOREF(pvUser); 5737 5740 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *); 5738 uint32_t uOffset= GCPhysAddr - pState->addrMMReg;5741 uint32_t offReg = GCPhysAddr - pState->addrMMReg; 5739 5742 int rc; 5740 5743 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIOWrite), a); 5741 5744 5742 Assert( uOffset< E1K_MM_SIZE);5745 Assert(offReg < E1K_MM_SIZE); 5743 5746 if (cb != 4) 5744 5747 { 5745 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));5746 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);5748 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, offReg, cb)); 5749 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", offReg, cb); 5747 5750 } 5748 5751 else 5749 rc = e1kRegWrite(pState, uOffset, pv, cb);5752 rc = e1kRegWrite(pState, offReg, pv, cb); 5750 5753 5751 5754 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIOWrite), a); … … 7212 7215 7213 7216 /** 7214 * Sets 8-bit register in PCI configuration space.7215 * @param refPciDev The PCI device.7216 * @param uOffset The register offset.7217 * @param u16Value The value to store in the register.7218 * @thread EMT7219 */7220 DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)7221 {7222 Assert(uOffset < sizeof(refPciDev.config));7223 refPciDev.config[uOffset] = u8Value;7224 }7225 7226 /**7227 * Sets 16-bit register in PCI configuration space.7228 * @param refPciDev The PCI device.7229 * @param uOffset The register offset.7230 * @param u16Value The value to store in the register.7231 * @thread EMT7232 */7233 DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)7234 {7235 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));7236 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;7237 }7238 7239 /**7240 * Sets 32-bit register in PCI configuration space.7241 * @param refPciDev The PCI device.7242 * @param uOffset The register offset.7243 * @param u32Value The value to store in the register.7244 * @thread EMT7245 */7246 DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)7247 {7248 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));7249 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;7250 }7251 7252 /**7253 7217 * Set PCI configuration space registers. 7254 7218 * … … 7256 7220 * @thread EMT 7257 7221 */ 7258 static DECLCALLBACK(void) e1kConfigureP CI(PCIDEVICE& pci, E1KCHIP eChip)7222 static DECLCALLBACK(void) e1kConfigurePciDev(PPCIDEVICE pPciDev, E1KCHIP eChip) 7259 7223 { 7260 7224 Assert(eChip < RT_ELEMENTS(g_Chips)); 7261 7225 /* Configure PCI Device, assume 32-bit mode ******************************/ 7262 PCIDevSetVendorId( &pci, g_Chips[eChip].uPCIVendorId);7263 PCIDevSetDeviceId( &pci, g_Chips[eChip].uPCIDeviceId);7264 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);7265 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);7266 7267 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);7226 PCIDevSetVendorId(pPciDev, g_Chips[eChip].uPCIVendorId); 7227 PCIDevSetDeviceId(pPciDev, g_Chips[eChip].uPCIDeviceId); 7228 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId); 7229 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId); 7230 7231 PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000); 7268 7232 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */ 7269 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS,7270 7233 PCIDevSetWord( pPciDev, VBOX_PCI_STATUS, 7234 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ); 7271 7235 /* Stepping A2 */ 7272 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);7236 PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02); 7273 7237 /* Ethernet adapter */ 7274 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);7275 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);7238 PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00); 7239 PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200); 7276 7240 /* normal single function Ethernet controller */ 7277 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);7241 PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00); 7278 7242 /* Memory Register Base Address */ 7279 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);7243 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000); 7280 7244 /* Memory Flash Base Address */ 7281 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);7245 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000); 7282 7246 /* IO Register Base Address */ 7283 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);7247 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001); 7284 7248 /* Expansion ROM Base Address */ 7285 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);7249 PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000); 7286 7250 /* Capabilities Pointer */ 7287 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);7251 PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC); 7288 7252 /* Interrupt Pin: INTA# */ 7289 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);7253 PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01); 7290 7254 /* Max_Lat/Min_Gnt: very high priority and time slice */ 7291 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);7292 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);7255 PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF); 7256 PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00); 7293 7257 7294 7258 /* PCI Power Management Registers ****************************************/ 7295 7259 /* Capability ID: PCI Power Management Registers */ 7296 e1kPCICfgSetU8( pci, 0xDC,VBOX_PCI_CAP_ID_PM);7260 PCIDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM); 7297 7261 /* Next Item Pointer: PCI-X */ 7298 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);7262 PCIDevSetByte( pPciDev, 0xDC + 1, 0xE4); 7299 7263 /* Power Management Capabilities: PM disabled, DSI */ 7300 e1kPCICfgSetU16(pci, 0xDC + 2,7264 PCIDevSetWord( pPciDev, 0xDC + 2, 7301 7265 0x0002 | VBOX_PCI_PM_CAP_DSI); 7302 7266 /* Power Management Control / Status Register: PM disabled */ 7303 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);7267 PCIDevSetWord( pPciDev, 0xDC + 4, 0x0000); 7304 7268 /* PMCSR_BSE Bridge Support Extensions: Not supported */ 7305 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);7269 PCIDevSetByte( pPciDev, 0xDC + 6, 0x00); 7306 7270 /* Data Register: PM disabled, always 0 */ 7307 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);7271 PCIDevSetByte( pPciDev, 0xDC + 7, 0x00); 7308 7272 7309 7273 /* PCI-X Configuration Registers *****************************************/ 7310 7274 /* Capability ID: PCI-X Configuration Registers */ 7311 e1kPCICfgSetU8( pci, 0xE4,VBOX_PCI_CAP_ID_PCIX);7275 PCIDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX); 7312 7276 #ifdef E1K_WITH_MSI 7313 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x80);7277 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x80); 7314 7278 #else 7315 7279 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */ 7316 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);7280 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x00); 7317 7281 #endif 7318 7282 /* PCI-X Command: Enable Relaxed Ordering */ 7319 e1kPCICfgSetU16(pci, 0xE4 + 2,VBOX_PCI_X_CMD_ERO);7283 PCIDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO); 7320 7284 /* PCI-X Status: 32-bit, 66MHz*/ 7321 7285 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */ 7322 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);7286 PCIDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8); 7323 7287 } 7324 7288 … … 7334 7298 /* 7335 7299 * Initialize the instance data (state). 7300 * Note! Caller has initialized it to ZERO already. 7336 7301 */ 7337 7302 RTStrPrintf(pThis->szInstance, sizeof(pThis->szInstance), "E1000#%d", iInstance); … … 7350 7315 pThis->led.u32Magic = PDMLED_MAGIC; 7351 7316 pThis->u32PktNo = 1; 7352 7353 #ifdef E1K_INT_STATS7354 pThis->uStatInt = 0;7355 pThis->uStatIntTry = 0;7356 pThis->uStatIntLower = 0;7357 pThis->uStatIntDly = 0;7358 pThis->uStatDisDly = 0;7359 pThis->iStatIntLost = 0;7360 pThis->iStatIntLostOne = 0;7361 pThis->uStatIntLate = 0;7362 pThis->uStatIntMasked = 0;7363 pThis->uStatIntEarly = 0;7364 pThis->uStatIntRx = 0;7365 pThis->uStatIntTx = 0;7366 pThis->uStatIntICS = 0;7367 pThis->uStatIntRDTR = 0;7368 pThis->uStatIntRXDMT0 = 0;7369 pThis->uStatIntTXQE = 0;7370 pThis->uStatTxNoRS = 0;7371 pThis->uStatTxIDE = 0;7372 pThis->uStatTxDelayed = 0;7373 pThis->uStatTxDelayExp = 0;7374 pThis->uStatTAD = 0;7375 pThis->uStatTID = 0;7376 pThis->uStatRAD = 0;7377 pThis->uStatRID = 0;7378 pThis->uStatRxFrm = 0;7379 pThis->uStatTxFrm = 0;7380 pThis->uStatDescCtx = 0;7381 pThis->uStatDescDat = 0;7382 pThis->uStatDescLeg = 0;7383 pThis->uStatTx1514 = 0;7384 pThis->uStatTx2962 = 0;7385 pThis->uStatTx4410 = 0;7386 pThis->uStatTx5858 = 0;7387 pThis->uStatTx7306 = 0;7388 pThis->uStatTx8754 = 0;7389 pThis->uStatTx16384 = 0;7390 pThis->uStatTx32768 = 0;7391 pThis->uStatTxLarge = 0;7392 pThis->uStatMaxTxDelay = 0;7393 #endif /* E1K_INT_STATS */7394 7317 7395 7318 /* Interfaces */ … … 7503 7426 return rc; 7504 7427 7505 /* Set PCI config registers */ 7506 e1kConfigurePCI(pThis->pciDevice, pThis->eChip); 7507 7508 /* Register PCI device */ 7428 /* Set PCI config registers and register ourselves with the PCI bus. */ 7429 e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip); 7509 7430 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice); 7510 7431 if (RT_FAILURE(rc)) … … 7708 7629 #endif /* VBOX_WITH_STATISTICS */ 7709 7630 7631 #ifdef E1K_INT_STATS 7632 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "u64ArmedAt", "/Devices/E1k%d/u64ArmedAt", iInstance); 7633 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatMaxTxDelay", "/Devices/E1k%d/uStatMaxTxDelay", iInstance); 7634 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatInt, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatInt", "/Devices/E1k%d/uStatInt", iInstance); 7635 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTry", "/Devices/E1k%d/uStatIntTry", iInstance); 7636 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLower", "/Devices/E1k%d/uStatIntLower", iInstance); 7637 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntDly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntDly", "/Devices/E1k%d/uStatIntDly", iInstance); 7638 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLost", "/Devices/E1k%d/iStatIntLost", iInstance); 7639 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLostOne", "/Devices/E1k%d/iStatIntLostOne", iInstance); 7640 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDisDly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDisDly", "/Devices/E1k%d/uStatDisDly", iInstance); 7641 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntSkip", "/Devices/E1k%d/uStatIntSkip", iInstance); 7642 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLate", "/Devices/E1k%d/uStatIntLate", iInstance); 7643 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntMasked", "/Devices/E1k%d/uStatIntMasked", iInstance); 7644 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntEarly", "/Devices/E1k%d/uStatIntEarly", iInstance); 7645 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRx", "/Devices/E1k%d/uStatIntRx", iInstance); 7646 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTx", "/Devices/E1k%d/uStatIntTx", iInstance); 7647 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntICS", "/Devices/E1k%d/uStatIntICS", iInstance); 7648 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRDTR", "/Devices/E1k%d/uStatIntRDTR", iInstance); 7649 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRXDMT0", "/Devices/E1k%d/uStatIntRXDMT0", iInstance); 7650 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTXQE", "/Devices/E1k%d/uStatIntTXQE", iInstance); 7651 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxNoRS", "/Devices/E1k%d/uStatTxNoRS", iInstance); 7652 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxIDE", "/Devices/E1k%d/uStatTxIDE", iInstance); 7653 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayed", "/Devices/E1k%d/uStatTxDelayed", iInstance); 7654 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayExp", "/Devices/E1k%d/uStatTxDelayExp", iInstance); 7655 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTAD", "/Devices/E1k%d/uStatTAD", iInstance); 7656 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTID", "/Devices/E1k%d/uStatTID", iInstance); 7657 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRAD", "/Devices/E1k%d/uStatRAD", iInstance); 7658 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRID", "/Devices/E1k%d/uStatRID", iInstance); 7659 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRxFrm", "/Devices/E1k%d/uStatRxFrm", iInstance); 7660 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxFrm", "/Devices/E1k%d/uStatTxFrm", iInstance); 7661 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescCtx", "/Devices/E1k%d/uStatDescCtx", iInstance); 7662 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescDat", "/Devices/E1k%d/uStatDescDat", iInstance); 7663 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescLeg", "/Devices/E1k%d/uStatDescLeg", iInstance); 7664 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx1514", "/Devices/E1k%d/uStatTx1514", iInstance); 7665 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx2962", "/Devices/E1k%d/uStatTx2962", iInstance); 7666 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx4410", "/Devices/E1k%d/uStatTx4410", iInstance); 7667 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx5858", "/Devices/E1k%d/uStatTx5858", iInstance); 7668 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx7306", "/Devices/E1k%d/uStatTx7306", iInstance); 7669 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx8754", "/Devices/E1k%d/uStatTx8754", iInstance); 7670 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx16384", "/Devices/E1k%d/uStatTx16384", iInstance); 7671 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx32768", "/Devices/E1k%d/uStatTx32768", iInstance); 7672 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxLarge", "/Devices/E1k%d/uStatTxLarge", iInstance); 7673 #endif /* E1K_INT_STATS */ 7674 7710 7675 return VINF_SUCCESS; 7711 7676 }
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