VirtualBox

Changeset 44542 in vbox for trunk/src


Ignore:
Timestamp:
Feb 5, 2013 1:16:16 PM (12 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
83594
Message:

DevE1000: More cleanups, changing it to use pThis instead of pState as we do in most other devices and drivers.

Location:
trunk/src/VBox/Devices/Network
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Network/DevE1000.cpp

    r44541 r44542  
    187187//#undef DEBUG
    188188
    189 #define STATE_TO_DEVINS(pState)           (((E1KSTATE *)pState)->CTX_SUFF(pDevIns))
     189#define STATE_TO_DEVINS(pThis)           (((PE1KSTATE )pThis)->CTX_SUFF(pDevIns))
    190190#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
    191191
    … …  
    327327#define RDTR_FPD            UINT32_C(0x80000000)
    328328
    329 #define PBA_st  ((PBAST*)(pState->auRegs + PBA_IDX))
     329#define PBA_st  ((PBAST*)(pThis->auRegs + PBA_IDX))
    330330typedef struct
    331331{
    … …  
    345345
    346346/** @name Register access macros
     347 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
    347348 * @{ */
    348 #define CTRL     pState->auRegs[CTRL_IDX]
    349 #define STATUS   pState->auRegs[STATUS_IDX]
    350 #define EECD     pState->auRegs[EECD_IDX]
    351 #define EERD     pState->auRegs[EERD_IDX]
    352 #define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
    353 #define FLA      pState->auRegs[FLA_IDX]
    354 #define MDIC     pState->auRegs[MDIC_IDX]
    355 #define FCAL     pState->auRegs[FCAL_IDX]
    356 #define FCAH     pState->auRegs[FCAH_IDX]
    357 #define FCT      pState->auRegs[FCT_IDX]
    358 #define VET      pState->auRegs[VET_IDX]
    359 #define ICR      pState->auRegs[ICR_IDX]
    360 #define ITR      pState->auRegs[ITR_IDX]
    361 #define ICS      pState->auRegs[ICS_IDX]
    362 #define IMS      pState->auRegs[IMS_IDX]
    363 #define IMC      pState->auRegs[IMC_IDX]
    364 #define RCTL     pState->auRegs[RCTL_IDX]
    365 #define FCTTV    pState->auRegs[FCTTV_IDX]
    366 #define TXCW     pState->auRegs[TXCW_IDX]
    367 #define RXCW     pState->auRegs[RXCW_IDX]
    368 #define TCTL     pState->auRegs[TCTL_IDX]
    369 #define TIPG     pState->auRegs[TIPG_IDX]
    370 #define AIFS     pState->auRegs[AIFS_IDX]
    371 #define LEDCTL   pState->auRegs[LEDCTL_IDX]
    372 #define PBA      pState->auRegs[PBA_IDX]
    373 #define FCRTL    pState->auRegs[FCRTL_IDX]
    374 #define FCRTH    pState->auRegs[FCRTH_IDX]
    375 #define RDFH     pState->auRegs[RDFH_IDX]
    376 #define RDFT     pState->auRegs[RDFT_IDX]
    377 #define RDFHS    pState->auRegs[RDFHS_IDX]
    378 #define RDFTS    pState->auRegs[RDFTS_IDX]
    379 #define RDFPC    pState->auRegs[RDFPC_IDX]
    380 #define RDBAL    pState->auRegs[RDBAL_IDX]
    381 #define RDBAH    pState->auRegs[RDBAH_IDX]
    382 #define RDLEN    pState->auRegs[RDLEN_IDX]
    383 #define RDH      pState->auRegs[RDH_IDX]
    384 #define RDT      pState->auRegs[RDT_IDX]
    385 #define RDTR     pState->auRegs[RDTR_IDX]
    386 #define RXDCTL   pState->auRegs[RXDCTL_IDX]
    387 #define RADV     pState->auRegs[RADV_IDX]
    388 #define RSRPD    pState->auRegs[RSRPD_IDX]
    389 #define TXDMAC   pState->auRegs[TXDMAC_IDX]
    390 #define TDFH     pState->auRegs[TDFH_IDX]
    391 #define TDFT     pState->auRegs[TDFT_IDX]
    392 #define TDFHS    pState->auRegs[TDFHS_IDX]
    393 #define TDFTS    pState->auRegs[TDFTS_IDX]
    394 #define TDFPC    pState->auRegs[TDFPC_IDX]
    395 #define TDBAL    pState->auRegs[TDBAL_IDX]
    396 #define TDBAH    pState->auRegs[TDBAH_IDX]
    397 #define TDLEN    pState->auRegs[TDLEN_IDX]
    398 #define TDH      pState->auRegs[TDH_IDX]
    399 #define TDT      pState->auRegs[TDT_IDX]
    400 #define TIDV     pState->auRegs[TIDV_IDX]
    401 #define TXDCTL   pState->auRegs[TXDCTL_IDX]
    402 #define TADV     pState->auRegs[TADV_IDX]
    403 #define TSPMT    pState->auRegs[TSPMT_IDX]
    404 #define CRCERRS  pState->auRegs[CRCERRS_IDX]
    405 #define ALGNERRC pState->auRegs[ALGNERRC_IDX]
    406 #define SYMERRS  pState->auRegs[SYMERRS_IDX]
    407 #define RXERRC   pState->auRegs[RXERRC_IDX]
    408 #define MPC      pState->auRegs[MPC_IDX]
    409 #define SCC      pState->auRegs[SCC_IDX]
    410 #define ECOL     pState->auRegs[ECOL_IDX]
    411 #define MCC      pState->auRegs[MCC_IDX]
    412 #define LATECOL  pState->auRegs[LATECOL_IDX]
    413 #define COLC     pState->auRegs[COLC_IDX]
    414 #define DC       pState->auRegs[DC_IDX]
    415 #define TNCRS    pState->auRegs[TNCRS_IDX]
    416 #define SEC      pState->auRegs[SEC_IDX]
    417 #define CEXTERR  pState->auRegs[CEXTERR_IDX]
    418 #define RLEC     pState->auRegs[RLEC_IDX]
    419 #define XONRXC   pState->auRegs[XONRXC_IDX]
    420 #define XONTXC   pState->auRegs[XONTXC_IDX]
    421 #define XOFFRXC  pState->auRegs[XOFFRXC_IDX]
    422 #define XOFFTXC  pState->auRegs[XOFFTXC_IDX]
    423 #define FCRUC    pState->auRegs[FCRUC_IDX]
    424 #define PRC64    pState->auRegs[PRC64_IDX]
    425 #define PRC127   pState->auRegs[PRC127_IDX]
    426 #define PRC255   pState->auRegs[PRC255_IDX]
    427 #define PRC511   pState->auRegs[PRC511_IDX]
    428 #define PRC1023  pState->auRegs[PRC1023_IDX]
    429 #define PRC1522  pState->auRegs[PRC1522_IDX]
    430 #define GPRC     pState->auRegs[GPRC_IDX]
    431 #define BPRC     pState->auRegs[BPRC_IDX]
    432 #define MPRC     pState->auRegs[MPRC_IDX]
    433 #define GPTC     pState->auRegs[GPTC_IDX]
    434 #define GORCL    pState->auRegs[GORCL_IDX]
    435 #define GORCH    pState->auRegs[GORCH_IDX]
    436 #define GOTCL    pState->auRegs[GOTCL_IDX]
    437 #define GOTCH    pState->auRegs[GOTCH_IDX]
    438 #define RNBC     pState->auRegs[RNBC_IDX]
    439 #define RUC      pState->auRegs[RUC_IDX]
    440 #define RFC      pState->auRegs[RFC_IDX]
    441 #define ROC      pState->auRegs[ROC_IDX]
    442 #define RJC      pState->auRegs[RJC_IDX]
    443 #define MGTPRC   pState->auRegs[MGTPRC_IDX]
    444 #define MGTPDC   pState->auRegs[MGTPDC_IDX]
    445 #define MGTPTC   pState->auRegs[MGTPTC_IDX]
    446 #define TORL     pState->auRegs[TORL_IDX]
    447 #define TORH     pState->auRegs[TORH_IDX]
    448 #define TOTL     pState->auRegs[TOTL_IDX]
    449 #define TOTH     pState->auRegs[TOTH_IDX]
    450 #define TPR      pState->auRegs[TPR_IDX]
    451 #define TPT      pState->auRegs[TPT_IDX]
    452 #define PTC64    pState->auRegs[PTC64_IDX]
    453 #define PTC127   pState->auRegs[PTC127_IDX]
    454 #define PTC255   pState->auRegs[PTC255_IDX]
    455 #define PTC511   pState->auRegs[PTC511_IDX]
    456 #define PTC1023  pState->auRegs[PTC1023_IDX]
    457 #define PTC1522  pState->auRegs[PTC1522_IDX]
    458 #define MPTC     pState->auRegs[MPTC_IDX]
    459 #define BPTC     pState->auRegs[BPTC_IDX]
    460 #define TSCTC    pState->auRegs[TSCTC_IDX]
    461 #define TSCTFC   pState->auRegs[TSCTFC_IDX]
    462 #define RXCSUM   pState->auRegs[RXCSUM_IDX]
    463 #define WUC      pState->auRegs[WUC_IDX]
    464 #define WUFC     pState->auRegs[WUFC_IDX]
    465 #define WUS      pState->auRegs[WUS_IDX]
    466 #define MANC     pState->auRegs[MANC_IDX]
    467 #define IPAV     pState->auRegs[IPAV_IDX]
    468 #define WUPL     pState->auRegs[WUPL_IDX]
     349#define CTRL     pThis->auRegs[CTRL_IDX]
     350#define STATUS   pThis->auRegs[STATUS_IDX]
     351#define EECD     pThis->auRegs[EECD_IDX]
     352#define EERD     pThis->auRegs[EERD_IDX]
     353#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
     354#define FLA      pThis->auRegs[FLA_IDX]
     355#define MDIC     pThis->auRegs[MDIC_IDX]
     356#define FCAL     pThis->auRegs[FCAL_IDX]
     357#define FCAH     pThis->auRegs[FCAH_IDX]
     358#define FCT      pThis->auRegs[FCT_IDX]
     359#define VET      pThis->auRegs[VET_IDX]
     360#define ICR      pThis->auRegs[ICR_IDX]
     361#define ITR      pThis->auRegs[ITR_IDX]
     362#define ICS      pThis->auRegs[ICS_IDX]
     363#define IMS      pThis->auRegs[IMS_IDX]
     364#define IMC      pThis->auRegs[IMC_IDX]
     365#define RCTL     pThis->auRegs[RCTL_IDX]
     366#define FCTTV    pThis->auRegs[FCTTV_IDX]
     367#define TXCW     pThis->auRegs[TXCW_IDX]
     368#define RXCW     pThis->auRegs[RXCW_IDX]
     369#define TCTL     pThis->auRegs[TCTL_IDX]
     370#define TIPG     pThis->auRegs[TIPG_IDX]
     371#define AIFS     pThis->auRegs[AIFS_IDX]
     372#define LEDCTL   pThis->auRegs[LEDCTL_IDX]
     373#define PBA      pThis->auRegs[PBA_IDX]
     374#define FCRTL    pThis->auRegs[FCRTL_IDX]
     375#define FCRTH    pThis->auRegs[FCRTH_IDX]
     376#define RDFH     pThis->auRegs[RDFH_IDX]
     377#define RDFT     pThis->auRegs[RDFT_IDX]
     378#define RDFHS    pThis->auRegs[RDFHS_IDX]
     379#define RDFTS    pThis->auRegs[RDFTS_IDX]
     380#define RDFPC    pThis->auRegs[RDFPC_IDX]
     381#define RDBAL    pThis->auRegs[RDBAL_IDX]
     382#define RDBAH    pThis->auRegs[RDBAH_IDX]
     383#define RDLEN    pThis->auRegs[RDLEN_IDX]
     384#define RDH      pThis->auRegs[RDH_IDX]
     385#define RDT      pThis->auRegs[RDT_IDX]
     386#define RDTR     pThis->auRegs[RDTR_IDX]
     387#define RXDCTL   pThis->auRegs[RXDCTL_IDX]
     388#define RADV     pThis->auRegs[RADV_IDX]
     389#define RSRPD    pThis->auRegs[RSRPD_IDX]
     390#define TXDMAC   pThis->auRegs[TXDMAC_IDX]
     391#define TDFH     pThis->auRegs[TDFH_IDX]
     392#define TDFT     pThis->auRegs[TDFT_IDX]
     393#define TDFHS    pThis->auRegs[TDFHS_IDX]
     394#define TDFTS    pThis->auRegs[TDFTS_IDX]
     395#define TDFPC    pThis->auRegs[TDFPC_IDX]
     396#define TDBAL    pThis->auRegs[TDBAL_IDX]
     397#define TDBAH    pThis->auRegs[TDBAH_IDX]
     398#define TDLEN    pThis->auRegs[TDLEN_IDX]
     399#define TDH      pThis->auRegs[TDH_IDX]
     400#define TDT      pThis->auRegs[TDT_IDX]
     401#define TIDV     pThis->auRegs[TIDV_IDX]
     402#define TXDCTL   pThis->auRegs[TXDCTL_IDX]
     403#define TADV     pThis->auRegs[TADV_IDX]
     404#define TSPMT    pThis->auRegs[TSPMT_IDX]
     405#define CRCERRS  pThis->auRegs[CRCERRS_IDX]
     406#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
     407#define SYMERRS  pThis->auRegs[SYMERRS_IDX]
     408#define RXERRC   pThis->auRegs[RXERRC_IDX]
     409#define MPC      pThis->auRegs[MPC_IDX]
     410#define SCC      pThis->auRegs[SCC_IDX]
     411#define ECOL     pThis->auRegs[ECOL_IDX]
     412#define MCC      pThis->auRegs[MCC_IDX]
     413#define LATECOL  pThis->auRegs[LATECOL_IDX]
     414#define COLC     pThis->auRegs[COLC_IDX]
     415#define DC       pThis->auRegs[DC_IDX]
     416#define TNCRS    pThis->auRegs[TNCRS_IDX]
     417#define SEC      pThis->auRegs[SEC_IDX]
     418#define CEXTERR  pThis->auRegs[CEXTERR_IDX]
     419#define RLEC     pThis->auRegs[RLEC_IDX]
     420#define XONRXC   pThis->auRegs[XONRXC_IDX]
     421#define XONTXC   pThis->auRegs[XONTXC_IDX]
     422#define XOFFRXC  pThis->auRegs[XOFFRXC_IDX]
     423#define XOFFTXC  pThis->auRegs[XOFFTXC_IDX]
     424#define FCRUC    pThis->auRegs[FCRUC_IDX]
     425#define PRC64    pThis->auRegs[PRC64_IDX]
     426#define PRC127   pThis->auRegs[PRC127_IDX]
     427#define PRC255   pThis->auRegs[PRC255_IDX]
     428#define PRC511   pThis->auRegs[PRC511_IDX]
     429#define PRC1023  pThis->auRegs[PRC1023_IDX]
     430#define PRC1522  pThis->auRegs[PRC1522_IDX]
     431#define GPRC     pThis->auRegs[GPRC_IDX]
     432#define BPRC     pThis->auRegs[BPRC_IDX]
     433#define MPRC     pThis->auRegs[MPRC_IDX]
     434#define GPTC     pThis->auRegs[GPTC_IDX]
     435#define GORCL    pThis->auRegs[GORCL_IDX]
     436#define GORCH    pThis->auRegs[GORCH_IDX]
     437#define GOTCL    pThis->auRegs[GOTCL_IDX]
     438#define GOTCH    pThis->auRegs[GOTCH_IDX]
     439#define RNBC     pThis->auRegs[RNBC_IDX]
     440#define RUC      pThis->auRegs[RUC_IDX]
     441#define RFC      pThis->auRegs[RFC_IDX]
     442#define ROC      pThis->auRegs[ROC_IDX]
     443#define RJC      pThis->auRegs[RJC_IDX]
     444#define MGTPRC   pThis->auRegs[MGTPRC_IDX]
     445#define MGTPDC   pThis->auRegs[MGTPDC_IDX]
     446#define MGTPTC   pThis->auRegs[MGTPTC_IDX]
     447#define TORL     pThis->auRegs[TORL_IDX]
     448#define TORH     pThis->auRegs[TORH_IDX]
     449#define TOTL     pThis->auRegs[TOTL_IDX]
     450#define TOTH     pThis->auRegs[TOTH_IDX]
     451#define TPR      pThis->auRegs[TPR_IDX]
     452#define TPT      pThis->auRegs[TPT_IDX]
     453#define PTC64    pThis->auRegs[PTC64_IDX]
     454#define PTC127   pThis->auRegs[PTC127_IDX]
     455#define PTC255   pThis->auRegs[PTC255_IDX]
     456#define PTC511   pThis->auRegs[PTC511_IDX]
     457#define PTC1023  pThis->auRegs[PTC1023_IDX]
     458#define PTC1522  pThis->auRegs[PTC1522_IDX]
     459#define MPTC     pThis->auRegs[MPTC_IDX]
     460#define BPTC     pThis->auRegs[BPTC_IDX]
     461#define TSCTC    pThis->auRegs[TSCTC_IDX]
     462#define TSCTFC   pThis->auRegs[TSCTFC_IDX]
     463#define RXCSUM   pThis->auRegs[RXCSUM_IDX]
     464#define WUC      pThis->auRegs[WUC_IDX]
     465#define WUFC     pThis->auRegs[WUFC_IDX]
     466#define WUS      pThis->auRegs[WUS_IDX]
     467#define MANC     pThis->auRegs[MANC_IDX]
     468#define IPAV     pThis->auRegs[IPAV_IDX]
     469#define WUPL     pThis->auRegs[WUPL_IDX]
    469470/** @} */
    470471
    … …  
    12781279
    12791280/* Forward declarations ******************************************************/
    1280 static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread);
    1281 
    1282 static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1283 static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1284 static int e1kRegReadAutoClear     (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1285 static int e1kRegReadDefault       (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1286 static int e1kRegWriteDefault      (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
     1281static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread);
     1282
     1283static int e1kRegReadUnimplemented (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1284static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1285static int e1kRegReadAutoClear     (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1286static int e1kRegReadDefault       (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1287static int e1kRegWriteDefault      (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
    12871288#if 0 /* unused */
    1288 static int e1kRegReadCTRL          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1289static int e1kRegReadCTRL          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    12891290#endif
    1290 static int e1kRegWriteCTRL         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1291 static int e1kRegReadEECD          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1292 static int e1kRegWriteEECD         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1293 static int e1kRegWriteEERD         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1294 static int e1kRegWriteMDIC         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1295 static int e1kRegReadICR           (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1296 static int e1kRegWriteICR          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1297 static int e1kRegWriteICS          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1298 static int e1kRegWriteIMS          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1299 static int e1kRegWriteIMC          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1300 static int e1kRegWriteRCTL         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1301 static int e1kRegWritePBA          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1302 static int e1kRegWriteRDT          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1303 static int e1kRegWriteRDTR         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1304 static int e1kRegWriteTDT          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1305 static int e1kRegReadMTA           (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1306 static int e1kRegWriteMTA          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1307 static int e1kRegReadRA            (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1308 static int e1kRegWriteRA           (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    1309 static int e1kRegReadVFTA          (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    1310 static int e1kRegWriteVFTA         (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
     1291static int e1kRegWriteCTRL         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1292static int e1kRegReadEECD          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1293static int e1kRegWriteEECD         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1294static int e1kRegWriteEERD         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1295static int e1kRegWriteMDIC         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1296static int e1kRegReadICR           (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1297static int e1kRegWriteICR          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1298static int e1kRegWriteICS          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1299static int e1kRegWriteIMS          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1300static int e1kRegWriteIMC          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1301static int e1kRegWriteRCTL         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1302static int e1kRegWritePBA          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1303static int e1kRegWriteRDT          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1304static int e1kRegWriteRDTR         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1305static int e1kRegWriteTDT          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1306static int e1kRegReadMTA           (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1307static int e1kRegWriteMTA          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1308static int e1kRegReadRA            (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1309static int e1kRegWriteRA           (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     1310static int e1kRegReadVFTA          (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1311static int e1kRegWriteVFTA         (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
    13111312
    13121313/**
    … …  
    13261327    uint32_t   writable;
    13271328    /** Read callback. */
    1328     int       (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     1329    int       (*pfnRead)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    13291330    /** Write callback. */
    1330     int       (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
     1331    int       (*pfnWrite)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
    13311332    /** Abbreviated name. */
    13321333    const char *abbrev;
    … …  
    15041505 * @returns The timer name.
    15051506 *
    1506  * @param   pState      The device state structure.
     1507 * @param   pThis       The device state structure.
    15071508 * @param   pTimer      The timer to get the name for.
    15081509 */
    1509 DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
    1510 {
    1511     if (pTimer == pState->CTX_SUFF(pTIDTimer))
     1510DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, PTMTIMER pTimer)
     1511{
     1512    if (pTimer == pThis->CTX_SUFF(pTIDTimer))
    15121513        return "TID";
    1513     if (pTimer == pState->CTX_SUFF(pTADTimer))
     1514    if (pTimer == pThis->CTX_SUFF(pTADTimer))
    15141515        return "TAD";
    1515     if (pTimer == pState->CTX_SUFF(pRIDTimer))
     1516    if (pTimer == pThis->CTX_SUFF(pRIDTimer))
    15161517        return "RID";
    1517     if (pTimer == pState->CTX_SUFF(pRADTimer))
     1518    if (pTimer == pThis->CTX_SUFF(pRADTimer))
    15181519        return "RAD";
    1519     if (pTimer == pState->CTX_SUFF(pIntTimer))
     1520    if (pTimer == pThis->CTX_SUFF(pIntTimer))
    15201521        return "Int";
    1521     if (pTimer == pState->CTX_SUFF(pTXDTimer))
     1522    if (pTimer == pThis->CTX_SUFF(pTXDTimer))
    15221523        return "TXD";
    15231524    return "unknown";
    … …  
    15291530 * Arm a timer.
    15301531 *
    1531  * @param   pState      Pointer to the device state structure.
     1532 * @param   pThis      Pointer to the device state structure.
    15321533 * @param   pTimer      Pointer to the timer.
    15331534 * @param   uExpireIn   Expiration interval in microseconds.
    15341535 */
    1535 DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
    1536 {
    1537     if (pState->fLocked)
     1536DECLINLINE(void) e1kArmTimer(PE1KSTATE pThis, PTMTIMER pTimer, uint32_t uExpireIn)
     1537{
     1538    if (pThis->fLocked)
    15381539        return;
    15391540
    15401541    E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
    1541              pState->szPrf, e1kGetTimerName(pState, pTimer), uExpireIn));
     1542             pThis->szPrf, e1kGetTimerName(pThis, pTimer), uExpireIn));
    15421543    TMTimerSetMicro(pTimer, uExpireIn);
    15431544}
    … …  
    15461547 * Cancel a timer.
    15471548 *
    1548  * @param   pState      Pointer to the device state structure.
     1549 * @param   pThis      Pointer to the device state structure.
    15491550 * @param   pTimer      Pointer to the timer.
    15501551 */
    1551 DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
     1552DECLINLINE(void) e1kCancelTimer(PE1KSTATE pThis, PTMTIMER pTimer)
    15521553{
    15531554    E1kLog2(("%s Stopping %s timer...\n",
    1554             pState->szPrf, e1kGetTimerName(pState, pTimer)));
     1555            pThis->szPrf, e1kGetTimerName(pThis, pTimer)));
    15551556    int rc = TMTimerStop(pTimer);
    15561557    if (RT_FAILURE(rc))
    15571558    {
    15581559        E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
    1559                 pState->szPrf, rc));
     1560                pThis->szPrf, rc));
    15601561    }
    15611562}
    … …  
    15831584static void e1kWakeupReceive(PPDMDEVINS pDevIns)
    15841585{
    1585     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    1586     if (    pState->fMaybeOutOfSpace
    1587         &&  pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
    1588     {
    1589         STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
    1590         E1kLog(("%s Waking up Out-of-RX-space semaphore\n",  pState->szPrf));
    1591         RTSemEventSignal(pState->hEventMoreRxDescAvail);
     1586    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     1587    if (    pThis->fMaybeOutOfSpace
     1588        &&  pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
     1589    {
     1590        STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
     1591        E1kLog(("%s Waking up Out-of-RX-space semaphore\n",  pThis->szPrf));
     1592        RTSemEventSignal(pThis->hEventMoreRxDescAvail);
    15921593    }
    15931594}
    … …  
    15961597 * Hardware reset. Revert all registers to initial values.
    15971598 *
    1598  * @param   pState      The device state structure.
    1599  */
    1600 static void e1kHardReset(E1KSTATE *pState)
    1601 {
    1602     E1kLog(("%s Hard reset triggered\n", pState->szPrf));
    1603     memset(pState->auRegs,        0, sizeof(pState->auRegs));
    1604     memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
     1599 * @param   pThis       The device state structure.
     1600 */
     1601static void e1kHardReset(PE1KSTATE pThis)
     1602{
     1603    E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
     1604    memset(pThis->auRegs,        0, sizeof(pThis->auRegs));
     1605    memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
    16051606#ifdef E1K_INIT_RA0
    1606     memcpy(pState->aRecAddr.au32, pState->macConfigured.au8,
    1607            sizeof(pState->macConfigured.au8));
    1608     pState->aRecAddr.array[0].ctl |= RA_CTL_AV;
     1607    memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
     1608           sizeof(pThis->macConfigured.au8));
     1609    pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
    16091610#endif /* E1K_INIT_RA0 */
    16101611    STATUS = 0x0081;    /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
    … …  
    16131614    TSPMT  = 0x01000400;/* TSMT=0400h TSPBP=0100h */
    16141615    Assert(GET_BITS(RCTL, BSIZE) == 0);
    1615     pState->u16RxBSize = 2048;
     1616    pThis->u16RxBSize = 2048;
    16161617
    16171618    /* Reset promiscuous mode */
    1618     if (pState->pDrvR3)
    1619         pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3, false);
     1619    if (pThis->pDrvR3)
     1620        pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, false);
    16201621
    16211622#ifdef E1K_WITH_TXD_CACHE
    1622     int rc = e1kCsTxEnter(pState, VERR_SEM_BUSY);
     1623    int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
    16231624    if (RT_LIKELY(rc == VINF_SUCCESS))
    16241625    {
    1625         pState->nTxDFetched  = 0;
    1626         pState->iTxDCurrent  = 0;
    1627         pState->fGSO         = false;
    1628         pState->cbTxAlloc    = 0;
    1629         e1kCsTxLeave(pState);
     1626        pThis->nTxDFetched  = 0;
     1627        pThis->iTxDCurrent  = 0;
     1628        pThis->fGSO         = false;
     1629        pThis->cbTxAlloc    = 0;
     1630        e1kCsTxLeave(pThis);
    16301631    }
    16311632#endif /* E1K_WITH_TXD_CACHE */
    16321633#ifdef E1K_WITH_RXD_CACHE
    1633     if (RT_LIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
    1634     {
    1635         pState->iRxDCurrent = pState->nRxDFetched = 0;
    1636         e1kCsRxLeave(pState);
     1634    if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
     1635    {
     1636        pThis->iRxDCurrent = pThis->nRxDFetched = 0;
     1637        e1kCsRxLeave(pThis);
    16371638    }
    16381639#endif /* E1K_WITH_RXD_CACHE */
    … …  
    16461647 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
    16471648 *
    1648  * @param   pState      The device state structure.
     1649 * @param   pThis       The device state structure.
    16491650 * @param   cpPacket    The packet.
    16501651 * @param   cb          The size of the packet.
    … …  
    16751676 * Dump a packet to debug log.
    16761677 *
    1677  * @param   pState      The device state structure.
     1678 * @param   pThis       The device state structure.
    16781679 * @param   cpPacket    The packet.
    16791680 * @param   cb          The size of the packet.
    … …  
    16811682 * @thread  E1000_TX
    16821683 */
    1683 DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
     1684DECLINLINE(void) e1kPacketDump(PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *cszText)
    16841685{
    16851686#ifdef DEBUG
    1686     if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
     1687    if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
    16871688    {
    16881689        E1kLog(("%s --- %s packet #%d: ---\n",
    1689                 pState->szPrf, cszText, ++pState->u32PktNo));
     1690                pThis->szPrf, cszText, ++pThis->u32PktNo));
    16901691        E1kLog3(("%.*Rhxd\n", cb, cpPacket));
    1691         e1kCsLeave(pState);
     1692        e1kCsLeave(pThis);
    16921693    }
    16931694#else
    1694     if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
    1695     {
    1696         E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
    1697         e1kCsLeave(pState);
     1695    if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
     1696    {
     1697        E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pThis->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
     1698        e1kCsLeave(pThis);
    16981699    }
    16991700#endif
    … …  
    17181719 * Dump receive descriptor to debug log.
    17191720 *
    1720  * @param   pState      The device state structure.
     1721 * @param   pThis       The device state structure.
    17211722 * @param   pDesc       Pointer to the descriptor.
    17221723 * @thread  E1000_RX
    17231724 */
    1724 static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
    1725 {
    1726     E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pState->szPrf, pDesc->u16Length));
     1725static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC* pDesc)
     1726{
     1727    E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
    17271728    E1kLog2(("        Address=%16LX Length=%04X Csum=%04X\n",
    17281729             pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
    … …  
    17471748 * Dump transmit descriptor to debug log.
    17481749 *
    1749  * @param   pState      The device state structure.
     1750 * @param   pThis       The device state structure.
    17501751 * @param   pDesc       Pointer to descriptor union.
    17511752 * @param   cszDir      A string denoting direction of descriptor transfer
    17521753 * @thread  E1000_TX
    17531754 */
    1754 static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir,
     1755static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, const char* cszDir,
    17551756                          unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
    17561757{
    … …  
    17631764        case E1K_DTYP_CONTEXT:
    17641765            E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
    1765                     pState->szPrf, cszDir, cszDir));
     1766                    pThis->szPrf, cszDir, cszDir));
    17661767            E1kLogX(uLevel, ("        IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
    17671768                    pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
    … …  
    17801781        case E1K_DTYP_DATA:
    17811782            E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
    1782                     pState->szPrf, cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
     1783                    pThis->szPrf, cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
    17831784            E1kLogX(uLevel, ("        Address=%16LX DTALEN=%05X\n",
    17841785                    pDesc->data.u64BufAddr,
    … …  
    18031804        case E1K_DTYP_LEGACY:
    18041805            E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
    1805                     pState->szPrf, cszDir, pDesc->legacy.cmd.u16Length, cszDir));
     1806                    pThis->szPrf, cszDir, pDesc->legacy.cmd.u16Length, cszDir));
    18061807            E1kLogX(uLevel, ("        Address=%16LX DTALEN=%05X\n",
    18071808                    pDesc->data.u64BufAddr,
    … …  
    18261827        default:
    18271828            E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
    1828                     pState->szPrf, cszDir, cszDir));
     1829                    pThis->szPrf, cszDir, cszDir));
    18291830            break;
    18301831    }
    … …  
    18341835 * Raise interrupt if not masked.
    18351836 *
    1836  * @param   pState      The device state structure.
    1837  */
    1838 static int e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
    1839 {
    1840     int rc = e1kCsEnter(pState, rcBusy);
     1837 * @param   pThis       The device state structure.
     1838 */
     1839static int e1kRaiseInterrupt(PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
     1840{
     1841    int rc = e1kCsEnter(pThis, rcBusy);
    18411842    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    18421843        return rc;
    18431844
    1844     E1K_INC_ISTAT_CNT(pState->uStatIntTry);
     1845    E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
    18451846    ICR |= u32IntCause;
    18461847    if (ICR & IMS)
    18471848    {
    18481849#if 0
    1849         if (pState->fDelayInts)
    1850         {
    1851             E1K_INC_ISTAT_CNT(pState->uStatIntDly);
    1852             pState->iStatIntLostOne = 1;
     1850        if (pThis->fDelayInts)
     1851        {
     1852            E1K_INC_ISTAT_CNT(pThis->uStatIntDly);
     1853            pThis->iStatIntLostOne = 1;
    18531854            E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
    1854                     pState->szPrf, ICR));
     1855                    pThis->szPrf, ICR));
    18551856#define E1K_LOST_IRQ_THRSLD 20
    18561857//#define E1K_LOST_IRQ_THRSLD 200000000
    1857             if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
     1858            if (pThis->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
    18581859            {
    18591860                E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
    1860                         pState->szPrf, pState->uStatIntDly, pState->uStatIntLate));
    1861                 pState->fIntMaskUsed = false;
    1862                 pState->uStatDisDly++;
     1861                        pThis->szPrf, pThis->uStatIntDly, pThis->uStatIntLate));
     1862                pThis->fIntMaskUsed = false;
     1863                pThis->uStatDisDly++;
    18631864            }
    18641865        }
    18651866        else
    18661867#endif
    1867         if (pState->fIntRaised)
    1868         {
    1869             E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
     1868        if (pThis->fIntRaised)
     1869        {
     1870            E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
    18701871            E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
    1871                     pState->szPrf, ICR & IMS));
     1872                    pThis->szPrf, ICR & IMS));
    18721873        }
    18731874        else
    18741875        {
    18751876#ifdef E1K_ITR_ENABLED
    1876             uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
     1877            uint64_t tstamp = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
    18771878            /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
    1878             E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
    1879                         pState->szPrf, (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
    1880             //if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
    1881             if (!!ITR && tstamp - pState->u64AckedAt < ITR * 256 && !(ICR & ICR_RXT0))
     1879            E1kLog2(("%s e1kRaiseInterrupt: tstamp - pThis->u64AckedAt = %d, ITR * 256 = %d\n",
     1880                        pThis->szPrf, (uint32_t)(tstamp - pThis->u64AckedAt), ITR * 256));
     1881            //if (!!ITR && pThis->fIntMaskUsed && tstamp - pThis->u64AckedAt < ITR * 256)
     1882            if (!!ITR && tstamp - pThis->u64AckedAt < ITR * 256 && !(ICR & ICR_RXT0))
    18821883            {
    1883                 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
     1884                E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
    18841885                E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
    1885                         pState->szPrf, (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
     1886                        pThis->szPrf, (uint32_t)(tstamp - pThis->u64AckedAt), ITR * 256));
    18861887            }
    18871888            else
    … …  
    18921893                 * there is no need to do it later -- stop the timer.
    18931894                 */
    1894                 TMTimerStop(pState->CTX_SUFF(pIntTimer));
    1895                 E1K_INC_ISTAT_CNT(pState->uStatInt);
    1896                 STAM_COUNTER_INC(&pState->StatIntsRaised);
     1895                TMTimerStop(pThis->CTX_SUFF(pIntTimer));
     1896                E1K_INC_ISTAT_CNT(pThis->uStatInt);
     1897                STAM_COUNTER_INC(&pThis->StatIntsRaised);
    18971898                /* Got at least one unmasked interrupt cause */
    1898                 pState->fIntRaised = true;
     1899                pThis->fIntRaised = true;
    18991900                /* Raise(1) INTA(0) */
    19001901                E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
    1901                 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
     1902                PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
    19021903                E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
    1903                         pState->szPrf, ICR & IMS));
     1904                        pThis->szPrf, ICR & IMS));
    19041905            }
    19051906        }
    … …  
    19071908    else
    19081909    {
    1909         E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
     1910        E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
    19101911        E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
    1911                 pState->szPrf, ICR, IMS));
    1912     }
    1913     e1kCsLeave(pState);
     1912                pThis->szPrf, ICR, IMS));
     1913    }
     1914    e1kCsLeave(pThis);
    19141915    return VINF_SUCCESS;
    19151916}
    … …  
    19351936 * @remarks RDH always points to the next available RX descriptor.
    19361937 *
    1937  * @param   pState      The device state structure.
    1938  */
    1939 DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
    1940 {
    1941     Assert(e1kCsRxIsOwner(pState));
    1942     //e1kCsEnter(pState, RT_SRC_POS);
     1938 * @param   pThis       The device state structure.
     1939 */
     1940DECLINLINE(void) e1kAdvanceRDH(PE1KSTATE pThis)
     1941{
     1942    Assert(e1kCsRxIsOwner(pThis));
     1943    //e1kCsEnter(pThis, RT_SRC_POS);
    19431944    if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
    19441945        RDH = 0;
    … …  
    19601961        E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
    19611962        E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
    1962                  pState->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
    1963         E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
    1964         e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
     1963                 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
     1964        E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
     1965        e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXDMT0);
    19651966    }
    19661967    E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
    1967              pState->szPrf, RDH, RDT, uRQueueLen));
    1968     //e1kCsLeave(pState);
     1968             pThis->szPrf, RDH, RDT, uRQueueLen));
     1969    //e1kCsLeave(pThis);
    19691970}
    19701971
    … …  
    19741975 *
    19751976 * @returns the number of available descriptors in RX ring.
    1976  * @param   pState      The device state structure.
     1977 * @param   pThis       The device state structure.
    19771978 * @thread  ???
    19781979 */
    1979 DECLINLINE(uint32_t) e1kGetRxLen(E1KSTATE* pState)
     1980DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
    19801981{
    19811982    /**
    … …  
    19871988}
    19881989
    1989 DECLINLINE(unsigned) e1kRxDInCache(E1KSTATE* pState)
    1990 {
    1991     return pState->nRxDFetched > pState->iRxDCurrent ?
    1992         pState->nRxDFetched - pState->iRxDCurrent : 0;
    1993 }
    1994 
    1995 DECLINLINE(unsigned) e1kRxDIsCacheEmpty(E1KSTATE* pState)
    1996 {
    1997     return pState->iRxDCurrent >= pState->nRxDFetched;
     1990DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
     1991{
     1992    return pThis->nRxDFetched > pThis->iRxDCurrent ?
     1993        pThis->nRxDFetched - pThis->iRxDCurrent : 0;
     1994}
     1995
     1996DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
     1997{
     1998    return pThis->iRxDCurrent >= pThis->nRxDFetched;
    19981999}
    19992000
    … …  
    20062007 *
    20072008 * @returns the actual number of descriptors fetched.
    2008  * @param   pState      The device state structure.
     2009 * @param   pThis       The device state structure.
    20092010 * @param   pDesc       Pointer to descriptor union.
    20102011 * @param   addr        Physical address in guest context.
    20112012 * @thread  EMT, RX
    20122013 */
    2013 DECLINLINE(unsigned) e1kRxDPrefetch(E1KSTATE* pState)
    2014 {
    2015     /* We've already loaded pState->nRxDFetched descriptors past RDH. */
    2016     unsigned nDescsAvailable    = e1kGetRxLen(pState) - e1kRxDInCache(pState);
    2017     unsigned nDescsToFetch      = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pState->nRxDFetched);
     2014DECLINLINE(unsigned) e1kRxDPrefetch(PE1KSTATE pThis)
     2015{
     2016    /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
     2017    unsigned nDescsAvailable    = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
     2018    unsigned nDescsToFetch      = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
    20182019    unsigned nDescsTotal        = RDLEN / sizeof(E1KRXDESC);
    20192020    Assert(nDescsTotal != 0);
    20202021    if (nDescsTotal == 0)
    20212022        return 0;
    2022     unsigned nFirstNotLoaded    = (RDH + e1kRxDInCache(pState)) % nDescsTotal;
     2023    unsigned nFirstNotLoaded    = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
    20232024    unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
    20242025    E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
    20252026             "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
    2026              pState->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
     2027             pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
    20272028             nFirstNotLoaded, nDescsInSingleRead));
    20282029    if (nDescsToFetch == 0)
    20292030        return 0;
    2030     E1KRXDESC* pFirstEmptyDesc = &pState->aRxDescriptors[pState->nRxDFetched];
    2031     PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
     2031    E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
     2032    PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
    20322033                      ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
    20332034                      pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
    20342035    // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
    20352036    // unsigned i, j;
    2036     // for (i = pState->nRxDFetched; i < pState->nRxDFetched + nDescsInSingleRead; ++i)
     2037    // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
    20372038    // {
    2038     //     pState->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pState->nRxDFetched) * sizeof(E1KRXDESC);
    2039     //     E1kLog3(("%s aRxDescAddr[%d] = %p\n", pState->szPrf, i, pState->aRxDescAddr[i]));
     2039    //     pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
     2040    //     E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
    20402041    // }
    20412042    E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
    2042              pState->szPrf, nDescsInSingleRead,
     2043             pThis->szPrf, nDescsInSingleRead,
    20432044             RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
    20442045             nFirstNotLoaded, RDLEN, RDH, RDT));
    20452046    if (nDescsToFetch > nDescsInSingleRead)
    20462047    {
    2047         PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
     2048        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
    20482049                          ((uint64_t)RDBAH << 32) + RDBAL,
    20492050                          pFirstEmptyDesc + nDescsInSingleRead,
    20502051                          (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
    2051         // Assert(i == pState->nRxDFetched  + nDescsInSingleRead);
    2052         // for (j = 0; i < pState->nRxDFetched + nDescsToFetch; ++i, ++j)
     2052        // Assert(i == pThis->nRxDFetched  + nDescsInSingleRead);
     2053        // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
    20532054        // {
    2054         //     pState->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
    2055         //     E1kLog3(("%s aRxDescAddr[%d] = %p\n", pState->szPrf, i, pState->aRxDescAddr[i]));
     2055        //     pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
     2056        //     E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
    20562057        // }
    20572058        E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
    2058                  pState->szPrf, nDescsToFetch - nDescsInSingleRead,
     2059                 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
    20592060                 RDBAH, RDBAL));
    20602061    }
    2061     pState->nRxDFetched += nDescsToFetch;
     2062    pThis->nRxDFetched += nDescsToFetch;
    20622063    return nDescsToFetch;
    20632064}
    … …  
    20712072 * cache is empty to do pre-fetch @bugref(6217).
    20722073 *
    2073  * @param   pState      The device state structure.
     2074 * @param   pThis       The device state structure.
    20742075 * @thread  RX
    20752076 */
    2076 DECLINLINE(E1KRXDESC*) e1kRxDGet(E1KSTATE* pState)
    2077 {
    2078     Assert(e1kCsRxIsOwner(pState));
     2077DECLINLINE(E1KRXDESC*) e1kRxDGet(PE1KSTATE pThis)
     2078{
     2079    Assert(e1kCsRxIsOwner(pThis));
    20792080    /* Check the cache first. */
    2080     if (pState->iRxDCurrent < pState->nRxDFetched)
    2081         return &pState->aRxDescriptors[pState->iRxDCurrent];
     2081    if (pThis->iRxDCurrent < pThis->nRxDFetched)
     2082        return &pThis->aRxDescriptors[pThis->iRxDCurrent];
    20822083    /* Cache is empty, reset it and check if we can fetch more. */
    2083     pState->iRxDCurrent = pState->nRxDFetched = 0;
    2084     if (e1kRxDPrefetch(pState))
    2085         return &pState->aRxDescriptors[pState->iRxDCurrent];
     2084    pThis->iRxDCurrent = pThis->nRxDFetched = 0;
     2085    if (e1kRxDPrefetch(pThis))
     2086        return &pThis->aRxDescriptors[pThis->iRxDCurrent];
    20862087    /* Out of Rx descriptors. */
    20872088    return NULL;
    … …  
    20922093 * pointer. The descriptor gets written back to the RXD ring.
    20932094 *
    2094  * @param   pState      The device state structure.
     2095 * @param   pThis       The device state structure.
    20952096 * @param   pDesc       The descriptor being "returned" to the RX ring.
    20962097 * @thread  RX
    20972098 */
    2098 DECLINLINE(void) e1kRxDPut(E1KSTATE* pState, E1KRXDESC* pDesc)
    2099 {
    2100     Assert(e1kCsRxIsOwner(pState));
    2101     pState->iRxDCurrent++;
    2102     // Assert(pDesc >= pState->aRxDescriptors);
    2103     // Assert(pDesc < pState->aRxDescriptors + E1K_RXD_CACHE_SIZE);
     2099DECLINLINE(void) e1kRxDPut(PE1KSTATE pThis, E1KRXDESC* pDesc)
     2100{
     2101    Assert(e1kCsRxIsOwner(pThis));
     2102    pThis->iRxDCurrent++;
     2103    // Assert(pDesc >= pThis->aRxDescriptors);
     2104    // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
    21042105    // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
    21052106    // uint32_t rdh = RDH;
    2106     // Assert(pState->aRxDescAddr[pDesc - pState->aRxDescriptors] == addr);
    2107     PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
     2107    // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
     2108    PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns),
    21082109                       e1kDescAddr(RDBAH, RDBAL, RDH),
    21092110                       pDesc, sizeof(E1KRXDESC));
    2110     e1kAdvanceRDH(pState);
    2111     e1kPrintRDesc(pState, pDesc);
     2111    e1kAdvanceRDH(pThis);
     2112    e1kPrintRDesc(pThis, pDesc);
    21122113}
    21132114
    … …  
    21152116 * Store a fragment of received packet at the specifed address.
    21162117 *
    2117  * @param   pState          The device state structure.
     2118 * @param   pThis          The device state structure.
    21182119 * @param   pDesc           The next available RX descriptor.
    21192120 * @param   pvBuf           The fragment.
    21202121 * @param   cb              The size of the fragment.
    21212122 */
    2122 static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
    2123 {
    2124     STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
     2123static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
     2124{
     2125    STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
    21252126    E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
    2126              pState->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
    2127     PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
     2127             pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
     2128    PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
    21282129    pDesc->u16Length = (uint16_t)cb;                        Assert(pDesc->u16Length == cb);
    2129     STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
     2130    STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
    21302131}
    21312132
    … …  
    21382139 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
    21392140 *
    2140  * @param   pState          The device state structure.
     2141 * @param   pThis          The device state structure.
    21412142 * @param   pDesc           The next available RX descriptor.
    21422143 * @param   pvBuf           The fragment.
    21432144 * @param   cb              The size of the fragment.
    21442145 */
    2145 static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
    2146 {
    2147     STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
    2148     E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
    2149     PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
     2146static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
     2147{
     2148    STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
     2149    E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
     2150    PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
    21502151    pDesc->u16Length = (uint16_t)cb;                        Assert(pDesc->u16Length == cb);
    21512152    /* Write back the descriptor */
    2152     PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
    2153     e1kPrintRDesc(pState, pDesc);
     2153    PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
     2154    e1kPrintRDesc(pThis, pDesc);
    21542155    E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
    21552156    /* Advance head */
    2156     e1kAdvanceRDH(pState);
    2157     //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pState->szPrf, pDesc->fEOP, RDTR, RADV));
     2157    e1kAdvanceRDH(pThis);
     2158    //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
    21582159    if (pDesc->status.fEOP)
    21592160    {
    … …  
    21632164        {
    21642165            /* Arm the timer to fire in RDTR usec (discard .024) */
    2165             e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
     2166            e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
    21662167            /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
    2167             if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
    2168                 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
     2168            if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
     2169                e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
    21692170        }
    21702171        else
    … …  
    21722173#endif
    21732174            /* 0 delay means immediate interrupt */
    2174             E1K_INC_ISTAT_CNT(pState->uStatIntRx);
    2175             e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
     2175            E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
     2176            e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
    21762177#ifdef E1K_USE_RX_TIMERS
    21772178        }
    21782179#endif
    21792180    }
    2180     STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
     2181    STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
    21812182}
    21822183#endif /* !E1K_WITH_RXD_CACHE */
    … …  
    22122213 *
    22132214 * @returns VBox status code.
    2214  * @param   pState          The device state structure.
     2215 * @param   pThis          The device state structure.
    22152216 * @param   pFrame          The available data.
    22162217 * @param   cb              Number of bytes available in the buffer.
    22172218 * @param   status          Bit fields containing status info.
    22182219 */
    2219 static int e1kRxChecksumOffload(E1KSTATE* pState, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
     2220static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
    22202221{
    22212222    /** @todo
    … …  
    22282229    uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
    22292230
    2230     E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pState->szPrf, uEtherType));
     2231    E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
    22312232
    22322233    switch (uEtherType)
    … …  
    22632264 *
    22642265 * @returns VBox status code.
    2265  * @param   pState          The device state structure.
     2266 * @param   pThis          The device state structure.
    22662267 * @param   pvBuf           The available data.
    22672268 * @param   cb              Number of bytes available in the buffer.
    22682269 * @param   status          Bit fields containing status info.
    22692270 */
    2270 static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
     2271static int e1kHandleRxPacket(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
    22712272{
    22722273#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
    … …  
    22742275    uint8_t  *ptr = rxPacket;
    22752276
    2276     int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
     2277    int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
    22772278    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    22782279        return rc;
    22792280
    22802281    if (cb > 70) /* unqualified guess */
    2281         pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
     2282        pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
    22822283
    22832284    Assert(cb <= E1K_MAX_RX_PKT_SIZE);
    22842285    Assert(cb > 16);
    22852286    size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
    2286     E1kLog3(("%s Max RX packet size is %u\n", pState->szPrf, cbMax));
     2287    E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
    22872288    if (status.fVP)
    22882289    {
    … …  
    22962297            cb -= 4;
    22972298            E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
    2298                      pState->szPrf, status.u16Special, cb));
     2299                     pThis->szPrf, status.u16Special, cb));
    22992300        }
    23002301        else
    … …  
    23112312    if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
    23122313    {
    2313         STAM_PROFILE_ADV_START(&pState->StatReceiveCRC, a);
     2314        STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
    23142315        /*
    23152316         * Add FCS if CRC stripping is not enabled. Since the value of CRC
    … …  
    23172318         * of calculating it (see EthernetCRC CFGM parameter).
    23182319         */
    2319         if (pState->fEthernetCRC)
     2320        if (pThis->fEthernetCRC)
    23202321            *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
    23212322        cb += sizeof(uint32_t);
    2322         STAM_PROFILE_ADV_STOP(&pState->StatReceiveCRC, a);
    2323         E1kLog3(("%s Added FCS (cb=%u)\n", pState->szPrf, cb));
     2323        STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
     2324        E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
    23242325    }
    23252326    /* Compute checksum of complete packet */
    23262327    uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
    2327     e1kRxChecksumOffload(pState, rxPacket, cb, &status);
     2328    e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
    23282329
    23292330    /* Update stats */
    … …  
    23352336    /* Update octet receive counter */
    23362337    E1K_ADD_CNT64(GORCL, GORCH, cb);
    2337     STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
     2338    STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
    23382339    if (cb == 64)
    23392340        E1K_INC_CNT32(PRC64);
    … …  
    23492350        E1K_INC_CNT32(PRC1522);
    23502351
    2351     E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
     2352    E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
    23522353
    23532354#ifdef E1K_WITH_RXD_CACHE
    23542355    while (cb > 0)
    23552356    {
    2356         E1KRXDESC *pDesc = e1kRxDGet(pState);
     2357        E1KRXDESC *pDesc = e1kRxDGet(pThis);
    23572358
    23582359        if (pDesc == NULL)
    … …  
    23602361            E1kLog(("%s Out of receive buffers, dropping the packet "
    23612362                    "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
    2362                     pState->szPrf, cb, e1kRxDInCache(pState), RDH, RDT));
     2363                    pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
    23632364            break;
    23642365        }
    … …  
    23672368    {
    23682369        E1kLog(("%s Out of receive buffers, dropping the packet\n",
    2369                 pState->szPrf));
     2370                pThis->szPrf));
    23702371    }
    23712372    /* Store the packet to receive buffers */
    … …  
    23742375        /* Load the descriptor pointed by head */
    23752376        E1KRXDESC desc, *pDesc = &desc;
    2376         PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
     2377        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
    23772378                          &desc, sizeof(desc));
    23782379#endif /* !E1K_WITH_RXD_CACHE */
    … …  
    23922393             * fetched RxD cache entries either.
    23932394             */
    2394             if (cb > pState->u16RxBSize)
     2395            if (cb > pThis->u16RxBSize)
    23952396            {
    23962397                pDesc->status.fEOP = false;
    2397                 e1kCsRxLeave(pState);
    2398                 e1kStoreRxFragment(pState, pDesc, ptr, pState->u16RxBSize);
    2399                 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
     2398                e1kCsRxLeave(pThis);
     2399                e1kStoreRxFragment(pThis, pDesc, ptr, pThis->u16RxBSize);
     2400                rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
    24002401                if (RT_UNLIKELY(rc != VINF_SUCCESS))
    24012402                    return rc;
    2402                 ptr += pState->u16RxBSize;
    2403                 cb -= pState->u16RxBSize;
     2403                ptr += pThis->u16RxBSize;
     2404                cb -= pThis->u16RxBSize;
    24042405            }
    24052406            else
    24062407            {
    24072408                pDesc->status.fEOP = true;
    2408                 e1kCsRxLeave(pState);
    2409                 e1kStoreRxFragment(pState, pDesc, ptr, cb);
     2409                e1kCsRxLeave(pThis);
     2410                e1kStoreRxFragment(pThis, pDesc, ptr, cb);
    24102411#ifdef E1K_WITH_RXD_CACHE
    2411                 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
     2412                rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
    24122413                if (RT_UNLIKELY(rc != VINF_SUCCESS))
    24132414                    return rc;
    24142415                cb = 0;
    24152416#else /* !E1K_WITH_RXD_CACHE */
    2416                 pState->led.Actual.s.fReading = 0;
     2417                pThis->led.Actual.s.fReading = 0;
    24172418                return VINF_SUCCESS;
    24182419#endif /* !E1K_WITH_RXD_CACHE */
    … …  
    24292430        /* Write back the descriptor. */
    24302431        pDesc->status.fDD = true;
    2431         e1kRxDPut(pState, pDesc);
     2432        e1kRxDPut(pThis, pDesc);
    24322433#ifndef E1K_WITH_RXD_CACHE
    24332434        }
    … …  
    24362437
    24372438    if (cb > 0)
    2438         E1kLog(("%s Out of receive buffers, dropping %u bytes", pState->szPrf, cb));
    2439 
    2440     pState->led.Actual.s.fReading = 0;
    2441 
    2442     e1kCsRxLeave(pState);
     2439        E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
     2440
     2441    pThis->led.Actual.s.fReading = 0;
     2442
     2443    e1kCsRxLeave(pThis);
    24432444#ifdef E1K_WITH_RXD_CACHE
    24442445    /* Complete packet has been stored -- it is time to let the guest know. */
    … …  
    24472448    {
    24482449        /* Arm the timer to fire in RDTR usec (discard .024) */
    2449         e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
     2450        e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
    24502451        /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
    2451         if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
    2452             e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
     2452        if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
     2453            e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
    24532454    }
    24542455    else
    … …  
    24562457# endif /* E1K_USE_RX_TIMERS */
    24572458        /* 0 delay means immediate interrupt */
    2458         E1K_INC_ISTAT_CNT(pState->uStatIntRx);
    2459         e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
     2459        E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
     2460        e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
    24602461# ifdef E1K_USE_RX_TIMERS
    24612462    }
    … …  
    24732474 * Bring the link up after the configured delay, 5 seconds by default.
    24742475 *
    2475  * @param   pState      The device state structure.
     2476 * @param   pThis       The device state structure.
    24762477 * @thread  any
    24772478 */
    2478 DECLINLINE(void) e1kBringLinkUpDelayed(E1KSTATE* pState)
     2479DECLINLINE(void) e1kBringLinkUpDelayed(PE1KSTATE pThis)
    24792480{
    24802481    E1kLog(("%s Will bring up the link in %d seconds...\n",
    2481             pState->szPrf, pState->cMsLinkUpDelay / 1000));
    2482     e1kArmTimer(pState, pState->CTX_SUFF(pLUTimer), pState->cMsLinkUpDelay * 1000);
     2482            pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
     2483    e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), pThis->cMsLinkUpDelay * 1000);
    24832484}
    24842485
    … …  
    24912492 * @returns VBox status code.
    24922493 *
    2493  * @param   pState      The device state structure.
     2494 * @param   pThis       The device state structure.
    24942495 * @param   offset      Register offset in memory-mapped frame.
    24952496 * @param   index       Register index in register array.
    24962497 * @param   mask        Used to implement partial reads (8 and 16-bit).
    24972498 */
    2498 static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     2499static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    24992500{
    25002501    E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
    2501             pState->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
     2502            pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
    25022503            (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
    25032504    if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
    25042505    {
    25052506        /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
    2506         if (Phy::readMDIO(&pState->phy))
     2507        if (Phy::readMDIO(&pThis->phy))
    25072508            *pu32Value = CTRL | CTRL_MDIO;
    25082509        else
    25092510            *pu32Value = CTRL & ~CTRL_MDIO;
    25102511        E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
    2511                 pState->szPrf, !!(*pu32Value & CTRL_MDIO)));
     2512                pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
    25122513    }
    25132514    else
    … …  
    25252526 * Handles reset.
    25262527 *
    2527  * @param   pState      The device state structure.
     2528 * @param   pThis       The device state structure.
    25282529 * @param   offset      Register offset in memory-mapped frame.
    25292530 * @param   index       Register index in register array.
    … …  
    25322533 * @thread  EMT
    25332534 */
    2534 static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2535static int e1kRegWriteCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    25352536{
    25362537    int rc = VINF_SUCCESS;
    … …  
    25412542        return VINF_IOM_R3_IOPORT_WRITE;
    25422543#else
    2543         e1kHardReset(pState);
     2544        e1kHardReset(pThis);
    25442545#endif
    25452546    }
    … …  
    25472548    {
    25482549        if (   (value & CTRL_SLU)
    2549             && pState->fCableConnected
     2550            && pThis->fCableConnected
    25502551            && !(STATUS & STATUS_LU))
    25512552        {
    25522553            /* The driver indicates that we should bring up the link */
    25532554            /* Do so in 5 seconds (by default). */
    2554             e1kBringLinkUpDelayed(pState);
     2555            e1kBringLinkUpDelayed(pThis);
    25552556            /*
    25562557             * Change the status (but not PHY status) anyway as Windows expects
    … …  
    25612562        if (value & CTRL_VME)
    25622563        {
    2563             E1kLog(("%s VLAN Mode Enabled\n", pState->szPrf));
     2564            E1kLog(("%s VLAN Mode Enabled\n", pThis->szPrf));
    25642565        }
    25652566        E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
    2566                 pState->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
     2567                pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
    25672568                (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
    25682569        if (value & CTRL_MDC)
    … …  
    25702571            if (value & CTRL_MDIO_DIR)
    25712572            {
    2572                 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pState->szPrf, !!(value & CTRL_MDIO)));
     2573                E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
    25732574                /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
    2574                 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
     2575                Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO));
    25752576            }
    25762577            else
    25772578            {
    2578                 if (Phy::readMDIO(&pState->phy))
     2579                if (Phy::readMDIO(&pThis->phy))
    25792580                    value |= CTRL_MDIO;
    25802581                else
    25812582                    value &= ~CTRL_MDIO;
    25822583                E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
    2583                         pState->szPrf, !!(value & CTRL_MDIO)));
     2584                        pThis->szPrf, !!(value & CTRL_MDIO)));
    25842585            }
    25852586        }
    2586         rc = e1kRegWriteDefault(pState, offset, index, value);
     2587        rc = e1kRegWriteDefault(pThis, offset, index, value);
    25872588    }
    25882589
    … …  
    25952596 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
    25962597 *
    2597  * @param   pState      The device state structure.
     2598 * @param   pThis       The device state structure.
    25982599 * @param   offset      Register offset in memory-mapped frame.
    25992600 * @param   index       Register index in register array.
    … …  
    26022603 * @thread  EMT
    26032604 */
    2604 static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2605static int e1kRegWriteEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    26052606{
    26062607#ifdef IN_RING3
    26072608    /* So far we are concerned with lower byte only */
    2608     if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
     2609    if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
    26092610    {
    26102611        /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
    26112612        /* Note: 82543GC does not need to request EEPROM access */
    2612         STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
    2613         pState->eeprom.write(value & EECD_EE_WIRES);
    2614         STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
     2613        STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
     2614        pThis->eeprom.write(value & EECD_EE_WIRES);
     2615        STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
    26152616    }
    26162617    if (value & EECD_EE_REQ)
    … …  
    26182619    else
    26192620        EECD &= ~EECD_EE_GNT;
    2620     //e1kRegWriteDefault(pState, offset, index, value );
     2621    //e1kRegWriteDefault(pThis, offset, index, value );
    26212622
    26222623    return VINF_SUCCESS;
    … …  
    26332634 * @returns VBox status code.
    26342635 *
    2635  * @param   pState      The device state structure.
     2636 * @param   pThis       The device state structure.
    26362637 * @param   offset      Register offset in memory-mapped frame.
    26372638 * @param   index       Register index in register array.
    … …  
    26392640 * @thread  EMT
    26402641 */
    2641 static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     2642static int e1kRegReadEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    26422643{
    26432644#ifdef IN_RING3
    26442645    uint32_t value;
    2645     int      rc = e1kRegReadDefault(pState, offset, index, &value);
     2646    int      rc = e1kRegReadDefault(pThis, offset, index, &value);
    26462647    if (RT_SUCCESS(rc))
    26472648    {
    2648         if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
     2649        if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
    26492650        {
    26502651            /* Note: 82543GC does not need to request EEPROM access */
    26512652            /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
    2652             STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
    2653             value |= pState->eeprom.read();
    2654             STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
     2653            STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
     2654            value |= pThis->eeprom.read();
     2655            STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
    26552656        }
    26562657        *pu32Value = value;
    … …  
    26692670 * into DATA field.
    26702671 *
    2671  * @param   pState      The device state structure.
     2672 * @param   pThis       The device state structure.
    26722673 * @param   offset      Register offset in memory-mapped frame.
    26732674 * @param   index       Register index in register array.
    … …  
    26762677 * @thread  EMT
    26772678 */
    2678 static int e1kRegWriteEERD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2679static int e1kRegWriteEERD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    26792680{
    26802681#ifdef IN_RING3
    26812682    /* Make use of 'writable' and 'readable' masks. */
    2682     e1kRegWriteDefault(pState, offset, index, value);
     2683    e1kRegWriteDefault(pThis, offset, index, value);
    26832684    /* DONE and DATA are set only if read was triggered by START. */
    26842685    if (value & EERD_START)
    26852686    {
    26862687        uint16_t tmp;
    2687         STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
    2688         if (pState->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
     2688        STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
     2689        if (pThis->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
    26892690            SET_BITS(EERD, DATA, tmp);
    26902691        EERD |= EERD_DONE;
    2691         STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
     2692        STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
    26922693    }
    26932694
    … …  
    27042705 * Handles PHY read/write requests; forwards requests to internal PHY device.
    27052706 *
    2706  * @param   pState      The device state structure.
     2707 * @param   pThis       The device state structure.
    27072708 * @param   offset      Register offset in memory-mapped frame.
    27082709 * @param   index       Register index in register array.
    … …  
    27112712 * @thread  EMT
    27122713 */
    2713 static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2714static int e1kRegWriteMDIC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    27142715{
    27152716    if (value & MDIC_INT_EN)
    27162717    {
    27172718        E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
    2718                 pState->szPrf));
     2719                pThis->szPrf));
    27192720    }
    27202721    else if (value & MDIC_READY)
    27212722    {
    27222723        E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
    2723                 pState->szPrf));
     2724                pThis->szPrf));
    27242725    }
    27252726    else if (GET_BITS_V(value, MDIC, PHY) != 1)
    27262727    {
    27272728        E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
    2728                 pState->szPrf, GET_BITS_V(value, MDIC, PHY)));
     2729                pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
    27292730    }
    27302731    else
    27312732    {
    27322733        /* Store the value */
    2733         e1kRegWriteDefault(pState, offset, index, value);
    2734         STAM_COUNTER_INC(&pState->StatPHYAccesses);
     2734        e1kRegWriteDefault(pThis, offset, index, value);
     2735        STAM_COUNTER_INC(&pThis->StatPHYAccesses);
    27352736        /* Forward op to PHY */
    27362737        if (value & MDIC_OP_READ)
    2737             SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
     2738            SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG)));
    27382739        else
    2739             Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
     2740            Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
    27402741        /* Let software know that we are done */
    27412742        MDIC |= MDIC_READY;
    … …  
    27502751 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
    27512752 *
    2752  * @param   pState      The device state structure.
     2753 * @param   pThis       The device state structure.
    27532754 * @param   offset      Register offset in memory-mapped frame.
    27542755 * @param   index       Register index in register array.
    … …  
    27572758 * @thread  EMT
    27582759 */
    2759 static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2760static int e1kRegWriteICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    27602761{
    27612762    ICR &= ~value;
    … …  
    27712772 * @returns VBox status code.
    27722773 *
    2773  * @param   pState      The device state structure.
     2774 * @param   pThis       The device state structure.
    27742775 * @param   offset      Register offset in memory-mapped frame.
    27752776 * @param   index       Register index in register array.
    … …  
    27772778 * @thread  EMT
    27782779 */
    2779 static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    2780 {
    2781     int rc = e1kCsEnter(pState, VINF_IOM_R3_MMIO_READ);
     2780static int e1kRegReadICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     2781{
     2782    int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
    27822783    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    27832784        return rc;
    27842785
    27852786    uint32_t value = 0;
    2786     rc = e1kRegReadDefault(pState, offset, index, &value);
     2787    rc = e1kRegReadDefault(pThis, offset, index, &value);
    27872788    if (RT_SUCCESS(rc))
    27882789    {
    … …  
    28012802                 */
    28022803                E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
    2803                 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pState->szPrf, ICR));
     2804                E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
    28042805                /* Clear all pending interrupts */
    28052806                ICR = 0;
    2806                 pState->fIntRaised = false;
     2807                pThis->fIntRaised = false;
    28072808                /* Lower(0) INTA(0) */
    2808                 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
    2809 
    2810                 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
    2811                 if (pState->fIntMaskUsed)
    2812                     pState->fDelayInts = true;
     2809                PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
     2810
     2811                pThis->u64AckedAt = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
     2812                if (pThis->fIntMaskUsed)
     2813                    pThis->fDelayInts = true;
    28132814            }
    28142815            else
    … …  
    28182819                 * just before re-enabling interrupts
    28192820                 */
    2820                 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pState->szPrf, ICR));
     2821                E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
    28212822            }
    28222823        }
    28232824        *pu32Value = value;
    28242825    }
    2825     e1kCsLeave(pState);
     2826    e1kCsLeave(pThis);
    28262827
    28272828    return rc;
    … …  
    28332834 * Bits corresponding to 1s in 'value' will be set in ICR register.
    28342835 *
    2835  * @param   pState      The device state structure.
     2836 * @param   pThis       The device state structure.
    28362837 * @param   offset      Register offset in memory-mapped frame.
    28372838 * @param   index       Register index in register array.
    … …  
    28402841 * @thread  EMT
    28412842 */
    2842 static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    2843 {
    2844     E1K_INC_ISTAT_CNT(pState->uStatIntICS);
    2845     return e1kRaiseInterrupt(pState, VINF_IOM_R3_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
     2843static int e1kRegWriteICS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     2844{
     2845    E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
     2846    return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
    28462847}
    28472848
    … …  
    28512852 * Will trigger pending interrupts.
    28522853 *
    2853  * @param   pState      The device state structure.
     2854 * @param   pThis       The device state structure.
    28542855 * @param   offset      Register offset in memory-mapped frame.
    28552856 * @param   index       Register index in register array.
    … …  
    28582859 * @thread  EMT
    28592860 */
    2860 static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2861static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    28612862{
    28622863    IMS |= value;
    28632864    E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
    2864     E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pState->szPrf));
     2865    E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
    28652866    /* Mask changes, we need to raise pending interrupts. */
    2866     if ((ICR & IMS) && !pState->fLocked)
     2867    if ((ICR & IMS) && !pThis->fLocked)
    28672868    {
    28682869        E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
    2869                  pState->szPrf, ICR));
     2870                 pThis->szPrf, ICR));
    28702871        /* Raising an interrupt immediately causes win7 to hang upon NIC reconfiguration, see @bugref{5023}. */
    2871         TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
    2872                    TMTimerGet(pState->CTX_SUFF(pIntTimer)));
     2872        TMTimerSet(pThis->CTX_SUFF(pIntTimer), TMTimerFromNano(pThis->CTX_SUFF(pIntTimer), ITR * 256) +
     2873                   TMTimerGet(pThis->CTX_SUFF(pIntTimer)));
    28732874    }
    28742875
    … …  
    28812882 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
    28822883 *
    2883  * @param   pState      The device state structure.
     2884 * @param   pThis       The device state structure.
    28842885 * @param   offset      Register offset in memory-mapped frame.
    28852886 * @param   index       Register index in register array.
    … …  
    28882889 * @thread  EMT
    28892890 */
    2890 static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    2891 {
    2892     int rc = e1kCsEnter(pState, VINF_IOM_R3_MMIO_WRITE);
     2891static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     2892{
     2893    int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
    28932894    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    28942895        return rc;
    2895     if (pState->fIntRaised)
     2896    if (pThis->fIntRaised)
    28962897    {
    28972898        /*
    … …  
    29002901         * of interrupt handler.
    29012902         */
    2902         E1K_INC_ISTAT_CNT(pState->uStatIntLower);
    2903         STAM_COUNTER_INC(&pState->StatIntsPrevented);
     2903        E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
     2904        STAM_COUNTER_INC(&pThis->StatIntsPrevented);
    29042905        E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
    29052906        /* Lower(0) INTA(0) */
    2906         PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
    2907         pState->fIntRaised = false;
    2908         E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pState->szPrf, ICR));
     2907        PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
     2908        pThis->fIntRaised = false;
     2909        E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
    29092910    }
    29102911    IMS &= ~value;
    2911     E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pState->szPrf));
    2912     e1kCsLeave(pState);
     2912    E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
     2913    e1kCsLeave(pThis);
    29132914
    29142915    return VINF_SUCCESS;
    … …  
    29182919 * Write handler for Receive Control register.
    29192920 *
    2920  * @param   pState      The device state structure.
     2921 * @param   pThis       The device state structure.
    29212922 * @param   offset      Register offset in memory-mapped frame.
    29222923 * @param   index       Register index in register array.
    … …  
    29252926 * @thread  EMT
    29262927 */
    2927 static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2928static int e1kRegWriteRCTL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    29282929{
    29292930    /* Update promiscuous mode */
    … …  
    29352936        return VINF_IOM_R3_IOPORT_WRITE;
    29362937#else
    2937         if (pState->pDrvR3)
    2938             pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3, fBecomePromiscous);
     2938        if (pThis->pDrvR3)
     2939            pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, fBecomePromiscous);
    29392940#endif
    29402941    }
    … …  
    29442945    if (value & RCTL_BSEX)
    29452946        cbRxBuf *= 16;
    2946     if (cbRxBuf != pState->u16RxBSize)
     2947    if (cbRxBuf != pThis->u16RxBSize)
    29472948        E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
    2948                  pState->szPrf, cbRxBuf, pState->u16RxBSize));
    2949     pState->u16RxBSize = cbRxBuf;
     2949                 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
     2950    pThis->u16RxBSize = cbRxBuf;
    29502951
    29512952    /* Update the register */
    2952     e1kRegWriteDefault(pState, offset, index, value);
     2953    e1kRegWriteDefault(pThis, offset, index, value);
    29532954
    29542955    return VINF_SUCCESS;
    … …  
    29602961 * TXA = 64 - RXA.
    29612962 *
    2962  * @param   pState      The device state structure.
     2963 * @param   pThis       The device state structure.
    29632964 * @param   offset      Register offset in memory-mapped frame.
    29642965 * @param   index       Register index in register array.
    … …  
    29672968 * @thread  EMT
    29682969 */
    2969 static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    2970 {
    2971     e1kRegWriteDefault(pState, offset, index, value);
     2970static int e1kRegWritePBA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     2971{
     2972    e1kRegWriteDefault(pThis, offset, index, value);
    29722973    PBA_st->txa = 64 - PBA_st->rxa;
    29732974
    … …  
    29832984 * @returns VBox status code.
    29842985 *
    2985  * @param   pState      The device state structure.
     2986 * @param   pThis       The device state structure.
    29862987 * @param   offset      Register offset in memory-mapped frame.
    29872988 * @param   index       Register index in register array.
    … …  
    29902991 * @thread  EMT
    29912992 */
    2992 static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     2993static int e1kRegWriteRDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    29932994{
    29942995#ifndef IN_RING3
    … …  
    29962997//    return VINF_IOM_R3_MMIO_WRITE;
    29972998#endif
    2998     int rc = e1kCsRxEnter(pState, VINF_IOM_R3_MMIO_WRITE);
     2999    int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
    29993000    if (RT_LIKELY(rc == VINF_SUCCESS))
    30003001    {
    3001         E1kLog(("%s e1kRegWriteRDT\n",  pState->szPrf));
    3002         rc = e1kRegWriteDefault(pState, offset, index, value);
     3002        E1kLog(("%s e1kRegWriteRDT\n",  pThis->szPrf));
     3003        rc = e1kRegWriteDefault(pThis, offset, index, value);
    30033004#ifdef E1K_WITH_RXD_CACHE
    30043005        /*
    … …  
    30213022         * a later point in e1kRxDGet().
    30223023         */
    3023         if (e1kRxDIsCacheEmpty(pState) && (RCTL & RCTL_EN))
    3024             e1kRxDPrefetch(pState);
     3024        if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
     3025            e1kRxDPrefetch(pThis);
    30253026#endif /* E1K_WITH_RXD_CACHE */
    3026         e1kCsRxLeave(pState);
     3027        e1kCsRxLeave(pThis);
    30273028        if (RT_SUCCESS(rc))
    30283029        {
    … …  
    30343035#ifdef IN_RING3
    30353036            /* Signal that we have more receive descriptors available. */
    3036             e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
     3037            e1kWakeupReceive(pThis->CTX_SUFF(pDevIns));
    30373038#else
    3038             PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
     3039            PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));
    30393040            if (pItem)
    3040                 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
     3041                PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);
    30413042#endif
    30423043        }
    … …  
    30483049 * Write handler for Receive Delay Timer register.
    30493050 *
    3050  * @param   pState      The device state structure.
     3051 * @param   pThis       The device state structure.
    30513052 * @param   offset      Register offset in memory-mapped frame.
    30523053 * @param   index       Register index in register array.
    … …  
    30553056 * @thread  EMT
    30563057 */
    3057 static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    3058 {
    3059     e1kRegWriteDefault(pState, offset, index, value);
     3058static int e1kRegWriteRDTR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     3059{
     3060    e1kRegWriteDefault(pThis, offset, index, value);
    30603061    if (value & RDTR_FPD)
    30613062    {
    30623063        /* Flush requested, cancel both timers and raise interrupt */
    30633064#ifdef E1K_USE_RX_TIMERS
    3064         e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
    3065         e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
     3065        e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
     3066        e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
    30663067#endif
    3067         E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
    3068         return e1kRaiseInterrupt(pState, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
     3068        E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
     3069        return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
    30693070    }
    30703071
    … …  
    30723073}
    30733074
    3074 DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
     3075DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
    30753076{
    30763077    /**
    … …  
    30973098static DECLCALLBACK(void) e1kTxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    30983099{
    3099     E1KSTATE *pState = (E1KSTATE *)pvUser;
    3100     Assert(PDMCritSectIsOwner(&pState->csTx));
    3101 
    3102     E1K_INC_ISTAT_CNT(pState->uStatTxDelayExp);
     3100    PE1KSTATE pThis = (PE1KSTATE )pvUser;
     3101    Assert(PDMCritSectIsOwner(&pThis->csTx));
     3102
     3103    E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
    31033104#ifdef E1K_INT_STATS
    3104     uint64_t u64Elapsed = RTTimeNanoTS() - pState->u64ArmedAt;
    3105     if (u64Elapsed > pState->uStatMaxTxDelay)
    3106         pState->uStatMaxTxDelay = u64Elapsed;
     3105    uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
     3106    if (u64Elapsed > pThis->uStatMaxTxDelay)
     3107        pThis->uStatMaxTxDelay = u64Elapsed;
    31073108#endif
    3108     int rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
     3109    int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
    31093110    AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
    31103111}
    … …  
    31253126static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    31263127{
    3127     E1KSTATE *pState = (E1KSTATE *)pvUser;
    3128 
    3129     E1K_INC_ISTAT_CNT(pState->uStatTID);
     3128    PE1KSTATE pThis = (PE1KSTATE )pvUser;
     3129
     3130    E1K_INC_ISTAT_CNT(pThis->uStatTID);
    31303131    /* Cancel absolute delay timer as we have already got attention */
    31313132#ifndef E1K_NO_TAD
    3132     e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
     3133    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
    31333134#endif /* E1K_NO_TAD */
    3134     e1kRaiseInterrupt(pState, ICR_TXDW);
     3135    e1kRaiseInterrupt(pThis, ICR_TXDW);
    31353136}
    31363137
    … …  
    31473148static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    31483149{
    3149     E1KSTATE *pState = (E1KSTATE *)pvUser;
    3150 
    3151     E1K_INC_ISTAT_CNT(pState->uStatTAD);
     3150    PE1KSTATE pThis = (PE1KSTATE )pvUser;
     3151
     3152    E1K_INC_ISTAT_CNT(pThis->uStatTAD);
    31523153    /* Cancel interrupt delay timer as we have already got attention */
    3153     e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
    3154     e1kRaiseInterrupt(pState, ICR_TXDW);
     3154    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
     3155    e1kRaiseInterrupt(pThis, ICR_TXDW);
    31553156}
    31563157
    … …  
    31703171static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    31713172{
    3172     E1KSTATE *pState = (E1KSTATE *)pvUser;
    3173 
    3174     E1K_INC_ISTAT_CNT(pState->uStatRID);
     3173    PE1KSTATE pThis = (PE1KSTATE )pvUser;
     3174
     3175    E1K_INC_ISTAT_CNT(pThis->uStatRID);
    31753176    /* Cancel absolute delay timer as we have already got attention */
    3176     e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
    3177     e1kRaiseInterrupt(pState, ICR_RXT0);
     3177    e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
     3178    e1kRaiseInterrupt(pThis, ICR_RXT0);
    31783179}
    31793180
    … …  
    31903191static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    31913192{
    3192     E1KSTATE *pState = (E1KSTATE *)pvUser;
    3193 
    3194     E1K_INC_ISTAT_CNT(pState->uStatRAD);
     3193    PE1KSTATE pThis = (PE1KSTATE )pvUser;
     3194
     3195    E1K_INC_ISTAT_CNT(pThis->uStatRAD);
    31953196    /* Cancel interrupt delay timer as we have already got attention */
    3196     e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
    3197     e1kRaiseInterrupt(pState, ICR_RXT0);
     3197    e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
     3198    e1kRaiseInterrupt(pThis, ICR_RXT0);
    31983199}
    31993200
    … …  
    32103211static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    32113212{
    3212     E1KSTATE *pState = (E1KSTATE *)pvUser;
    3213 
    3214     STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
    3215     STAM_COUNTER_INC(&pState->StatLateInts);
    3216     E1K_INC_ISTAT_CNT(pState->uStatIntLate);
     3213    PE1KSTATE pThis = (PE1KSTATE )pvUser;
     3214
     3215    STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
     3216    STAM_COUNTER_INC(&pThis->StatLateInts);
     3217    E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
    32173218#if 0
    3218     if (pState->iStatIntLost > -100)
    3219         pState->iStatIntLost--;
     3219    if (pThis->iStatIntLost > -100)
     3220        pThis->iStatIntLost--;
    32203221#endif
    3221     e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
    3222     STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
     3222    e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, 0);
     3223    STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
    32233224}
    32243225
    … …  
    32333234static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
    32343235{
    3235     E1KSTATE *pState = (E1KSTATE *)pvUser;
     3236    PE1KSTATE pThis = (PE1KSTATE )pvUser;
    32363237
    32373238    /*
    … …  
    32403241     * and connect+disconnect the cable very quick.
    32413242     */
    3242     if (!pState->fCableConnected)
     3243    if (!pThis->fCableConnected)
    32433244        return;
    32443245
    3245     E1kLog(("%s e1kLinkUpTimer: Link is up\n", pState->szPrf));
     3246    E1kLog(("%s e1kLinkUpTimer: Link is up\n", pThis->szPrf));
    32463247    STATUS |= STATUS_LU;
    3247     Phy::setLinkStatus(&pState->phy, true);
    3248     e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
     3248    Phy::setLinkStatus(&pThis->phy, true);
     3249    e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
    32493250}
    32503251
    … …  
    33583359 * Checks if we can use GSO processing for the current TSE frame.
    33593360 *
    3360  * @param   pState              The device state structure.
     3361 * @param   pThis              The device state structure.
    33613362 * @param   pGso                The GSO context.
    33623363 * @param   pData               The first data descriptor of the frame.
    33633364 * @param   pCtx                The TSO context descriptor.
    33643365 */
    3365 DECLINLINE(bool) e1kCanDoGso(E1KSTATE *pState, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
     3366DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
    33663367{
    33673368    if (!pData->cmd.fTSE)
    … …  
    33753376        return false;
    33763377    }
    3377     if (RT_UNLIKELY(!pState->fGSOEnabled))
     3378    if (RT_UNLIKELY(!pThis->fGSOEnabled))
    33783379    {
    33793380        E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
    … …  
    34253426 * Frees the current xmit buffer.
    34263427 *
    3427  * @param   pState              The device state structure.
    3428  */
    3429 static void e1kXmitFreeBuf(E1KSTATE *pState)
    3430 {
    3431     PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
     3428 * @param   pThis              The device state structure.
     3429 */
     3430static void e1kXmitFreeBuf(PE1KSTATE pThis)
     3431{
     3432    PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
    34323433    if (pSg)
    34333434    {
    3434         pState->CTX_SUFF(pTxSg) = NULL;
    3435 
    3436         if (pSg->pvAllocator != pState)
    3437         {
    3438             PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
     3435        pThis->CTX_SUFF(pTxSg) = NULL;
     3436
     3437        if (pSg->pvAllocator != pThis)
     3438        {
     3439            PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
    34393440            if (pDrv)
    34403441                pDrv->pfnFreeBuf(pDrv, pSg);
    … …  
    34563457 *
    34573458 * @returns See PDMINETWORKUP::pfnAllocBuf.
    3458  * @param   pState              The device state structure.
     3459 * @param   pThis              The device state structure.
    34593460 * @param   cbMin               The minimum frame size.
    34603461 * @param   fExactSize          Whether cbMin is exact or if we have to max it
    … …  
    34623463 * @param   fGso                Whether this is a GSO frame or not.
    34633464 */
    3464 DECLINLINE(int) e1kXmitAllocBuf(E1KSTATE *pState, size_t cbMin, bool fExactSize, bool fGso)
     3465DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, size_t cbMin, bool fExactSize, bool fGso)
    34653466{
    34663467    /* Adjust cbMin if necessary. */
    … …  
    34693470
    34703471    /* Deal with existing buffer (descriptor screw up, reset, etc). */
    3471     if (RT_UNLIKELY(pState->CTX_SUFF(pTxSg)))
    3472         e1kXmitFreeBuf(pState);
    3473     Assert(pState->CTX_SUFF(pTxSg) == NULL);
     3472    if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
     3473        e1kXmitFreeBuf(pThis);
     3474    Assert(pThis->CTX_SUFF(pTxSg) == NULL);
    34743475
    34753476    /*
    … …  
    34793480    if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
    34803481    {
    3481         PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
     3482        PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
    34823483        if (RT_UNLIKELY(!pDrv))
    34833484            return VERR_NET_DOWN;
    3484         int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pState->GsoCtx : NULL, &pSg);
     3485        int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
    34853486        if (RT_FAILURE(rc))
    34863487        {
    … …  
    34943495        /* Create a loopback using the fallback buffer and preallocated SG. */
    34953496        AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
    3496         pSg = &pState->uTxFallback.Sg;
     3497        pSg = &pThis->uTxFallback.Sg;
    34973498        pSg->fFlags      = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
    34983499        pSg->cbUsed      = 0;
    34993500        pSg->cbAvailable = 0;
    3500         pSg->pvAllocator = pState;
     3501        pSg->pvAllocator = pThis;
    35013502        pSg->pvUser      = NULL; /* No GSO here. */
    35023503        pSg->cSegs       = 1;
    3503         pSg->aSegs[0].pvSeg = pState->aTxPacketFallback;
    3504         pSg->aSegs[0].cbSeg = sizeof(pState->aTxPacketFallback);
    3505     }
    3506 
    3507     pState->CTX_SUFF(pTxSg) = pSg;
     3504        pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
     3505        pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
     3506    }
     3507
     3508    pThis->CTX_SUFF(pTxSg) = pSg;
    35083509    return VINF_SUCCESS;
    35093510}
    … …  
    35133514 *
    35143515 * @returns See PDMINETWORKUP::pfnAllocBuf.
    3515  * @param   pState              The device state structure.
     3516 * @param   pThis              The device state structure.
    35163517 * @param   cbMin               The minimum frame size.
    35173518 * @param   fExactSize          Whether cbMin is exact or if we have to max it
    … …  
    35193520 * @param   fGso                Whether this is a GSO frame or not.
    35203521 */
    3521 DECLINLINE(int) e1kXmitAllocBuf(E1KSTATE *pState, bool fGso)
     3522DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, bool fGso)
    35223523{
    35233524    /* Deal with existing buffer (descriptor screw up, reset, etc). */
    3524     if (RT_UNLIKELY(pState->CTX_SUFF(pTxSg)))
    3525         e1kXmitFreeBuf(pState);
    3526     Assert(pState->CTX_SUFF(pTxSg) == NULL);
     3525    if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
     3526        e1kXmitFreeBuf(pThis);
     3527    Assert(pThis->CTX_SUFF(pTxSg) == NULL);
    35273528
    35283529    /*
    … …  
    35323533    if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
    35333534    {
    3534         if (pState->cbTxAlloc == 0)
     3535        if (pThis->cbTxAlloc == 0)
    35353536        {
    35363537            /* Zero packet, no need for the buffer */
    … …  
    35383539        }
    35393540
    3540         PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
     3541        PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
    35413542        if (RT_UNLIKELY(!pDrv))
    35423543            return VERR_NET_DOWN;
    3543         int rc = pDrv->pfnAllocBuf(pDrv, pState->cbTxAlloc, fGso ? &pState->GsoCtx : NULL, &pSg);
     3544        int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
    35443545        if (RT_FAILURE(rc))
    35453546        {
    … …  
    35493550        }
    35503551        E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
    3551                  pState->szPrf, pState->cbTxAlloc,
    3552                  pState->fVTag ? "VLAN " : "",
    3553                  pState->fGSO ? "GSO " : ""));
    3554         pState->cbTxAlloc = 0;
     3552                 pThis->szPrf, pThis->cbTxAlloc,
     3553                 pThis->fVTag ? "VLAN " : "",
     3554                 pThis->fGSO ? "GSO " : ""));
     3555        pThis->cbTxAlloc = 0;
    35553556    }
    35563557    else
    … …  
    35583559        /* Create a loopback using the fallback buffer and preallocated SG. */
    35593560        AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
    3560         pSg = &pState->uTxFallback.Sg;
     3561        pSg = &pThis->uTxFallback.Sg;
    35613562        pSg->fFlags      = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
    35623563        pSg->cbUsed      = 0;
    35633564        pSg->cbAvailable = 0;
    3564         pSg->pvAllocator = pState;
     3565        pSg->pvAllocator = pThis;
    35653566        pSg->pvUser      = NULL; /* No GSO here. */
    35663567        pSg->cSegs       = 1;
    3567         pSg->aSegs[0].pvSeg = pState->aTxPacketFallback;
    3568         pSg->aSegs[0].cbSeg = sizeof(pState->aTxPacketFallback);
    3569     }
    3570 
    3571     pState->CTX_SUFF(pTxSg) = pSg;
     3568        pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
     3569        pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
     3570    }
     3571
     3572    pThis->CTX_SUFF(pTxSg) = pSg;
    35723573    return VINF_SUCCESS;
    35733574}
    … …  
    35953596 * Load transmit descriptor from guest memory.
    35963597 *
    3597  * @param   pState      The device state structure.
     3598 * @param   pThis       The device state structure.
    35983599 * @param   pDesc       Pointer to descriptor union.
    35993600 * @param   addr        Physical address in guest context.
    36003601 * @thread  E1000_TX
    36013602 */
    3602 DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
    3603 {
    3604     PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
     3603DECLINLINE(void) e1kLoadDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
     3604{
     3605    PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
    36053606}
    36063607#else /* E1K_WITH_TXD_CACHE */
    … …  
    36123613 *
    36133614 * @returns the actual number of descriptors fetched.
    3614  * @param   pState      The device state structure.
     3615 * @param   pThis       The device state structure.
    36153616 * @param   pDesc       Pointer to descriptor union.
    36163617 * @param   addr        Physical address in guest context.
    36173618 * @thread  E1000_TX
    36183619 */
    3619 DECLINLINE(unsigned) e1kTxDLoadMore(E1KSTATE* pState)
    3620 {
    3621     Assert(pState->iTxDCurrent == 0);
    3622     /* We've already loaded pState->nTxDFetched descriptors past TDH. */
    3623     unsigned nDescsAvailable    = e1kGetTxLen(pState) - pState->nTxDFetched;
    3624     unsigned nDescsToFetch      = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pState->nTxDFetched);
     3620DECLINLINE(unsigned) e1kTxDLoadMore(PE1KSTATE pThis)
     3621{
     3622    Assert(pThis->iTxDCurrent == 0);
     3623    /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
     3624    unsigned nDescsAvailable    = e1kGetTxLen(pThis) - pThis->nTxDFetched;
     3625    unsigned nDescsToFetch      = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
    36253626    unsigned nDescsTotal        = TDLEN / sizeof(E1KTXDESC);
    3626     unsigned nFirstNotLoaded    = (TDH + pState->nTxDFetched) % nDescsTotal;
     3627    unsigned nFirstNotLoaded    = (TDH + pThis->nTxDFetched) % nDescsTotal;
    36273628    unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
    36283629    E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u "
    36293630             "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
    3630              pState->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
     3631             pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
    36313632             nFirstNotLoaded, nDescsInSingleRead));
    36323633    if (nDescsToFetch == 0)
    36333634        return 0;
    3634     E1KTXDESC* pFirstEmptyDesc = &pState->aTxDescriptors[pState->nTxDFetched];
    3635     PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
     3635    E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
     3636    PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
    36363637                      ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
    36373638                      pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
    36383639    E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
    3639              pState->szPrf, nDescsInSingleRead,
     3640             pThis->szPrf, nDescsInSingleRead,
    36403641             TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
    36413642             nFirstNotLoaded, TDLEN, TDH, TDT));
    36423643    if (nDescsToFetch > nDescsInSingleRead)
    36433644    {
    3644         PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
     3645        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
    36453646                          ((uint64_t)TDBAH << 32) + TDBAL,
    36463647                          pFirstEmptyDesc + nDescsInSingleRead,
    36473648                          (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
    36483649        E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
    3649                  pState->szPrf, nDescsToFetch - nDescsInSingleRead,
     3650                 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
    36503651                 TDBAH, TDBAL));
    36513652    }
    3652     pState->nTxDFetched += nDescsToFetch;
     3653    pThis->nTxDFetched += nDescsToFetch;
    36533654    return nDescsToFetch;
    36543655}
    … …  
    36593660 *
    36603661 * @returns true if there are descriptors in cache.
    3661  * @param   pState      The device state structure.
     3662 * @param   pThis       The device state structure.
    36623663 * @param   pDesc       Pointer to descriptor union.
    36633664 * @param   addr        Physical address in guest context.
    36643665 * @thread  E1000_TX
    36653666 */
    3666 DECLINLINE(bool) e1kTxDLazyLoad(E1KSTATE* pState)
    3667 {
    3668     if (pState->nTxDFetched == 0)
    3669         return e1kTxDLoadMore(pState) != 0;
     3667DECLINLINE(bool) e1kTxDLazyLoad(PE1KSTATE pThis)
     3668{
     3669    if (pThis->nTxDFetched == 0)
     3670        return e1kTxDLoadMore(pThis) != 0;
    36703671    return true;
    36713672}
    … …  
    36753676 * Write back transmit descriptor to guest memory.
    36763677 *
    3677  * @param   pState      The device state structure.
     3678 * @param   pThis       The device state structure.
    36783679 * @param   pDesc       Pointer to descriptor union.
    36793680 * @param   addr        Physical address in guest context.
    36803681 * @thread  E1000_TX
    36813682 */
    3682 DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
     3683DECLINLINE(void) e1kWriteBackDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
    36833684{
    36843685    /* Only the last half of the descriptor has to be written back. */
    3685     e1kPrintTDesc(pState, pDesc, "^^^");
    3686     PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
     3686    e1kPrintTDesc(pThis, pDesc, "^^^");
     3687    PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
    36873688}
    36883689
    … …  
    36933694 *          a real ethernet wire.
    36943695 *
    3695  * @param   pState              The device state structure.
     3696 * @param   pThis              The device state structure.
    36963697 * @param   fOnWorkerThread     Whether we're on a worker thread or an EMT.
    36973698 * @thread  E1000_TX
    36983699 */
    3699 static void e1kTransmitFrame(E1KSTATE* pState, bool fOnWorkerThread)
    3700 {
    3701     PPDMSCATTERGATHER   pSg     = pState->CTX_SUFF(pTxSg);
     3700static void e1kTransmitFrame(PE1KSTATE pThis, bool fOnWorkerThread)
     3701{
     3702    PPDMSCATTERGATHER   pSg     = pThis->CTX_SUFF(pTxSg);
    37023703    uint32_t            cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
    37033704    Assert(!pSg || pSg->cSegs == 1);
    37043705
    37053706    if (cbFrame > 70) /* unqualified guess */
    3706         pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
     3707        pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
    37073708
    37083709#ifdef E1K_INT_STATS
    37093710    if (cbFrame <= 1514)
    3710         E1K_INC_ISTAT_CNT(pState->uStatTx1514);
     3711        E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
    37113712    else if (cbFrame <= 2962)
    3712         E1K_INC_ISTAT_CNT(pState->uStatTx2962);
     3713        E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
    37133714    else if (cbFrame <= 4410)
    3714         E1K_INC_ISTAT_CNT(pState->uStatTx4410);
     3715        E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
    37153716    else if (cbFrame <= 5858)
    3716         E1K_INC_ISTAT_CNT(pState->uStatTx5858);
     3717        E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
    37173718    else if (cbFrame <= 7306)
    3718         E1K_INC_ISTAT_CNT(pState->uStatTx7306);
     3719        E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
    37193720    else if (cbFrame <= 8754)
    3720         E1K_INC_ISTAT_CNT(pState->uStatTx8754);
     3721        E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
    37213722    else if (cbFrame <= 16384)
    3722         E1K_INC_ISTAT_CNT(pState->uStatTx16384);
     3723        E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
    37233724    else if (cbFrame <= 32768)
    3724         E1K_INC_ISTAT_CNT(pState->uStatTx32768);
     3725        E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
    37253726    else
    3726         E1K_INC_ISTAT_CNT(pState->uStatTxLarge);
     3727        E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
    37273728#endif /* E1K_INT_STATS */
    37283729
    37293730    /* Add VLAN tag */
    3730     if (cbFrame > 12 && pState->fVTag)
     3731    if (cbFrame > 12 && pThis->fVTag)
    37313732    {
    37323733        E1kLog3(("%s Inserting VLAN tag %08x\n",
    3733             pState->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pState->u16VTagTCI) << 16)));
     3734            pThis->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
    37343735        memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
    3735         *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pState->u16VTagTCI) << 16);
     3736        *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
    37363737        pSg->cbUsed += 4;
    37373738        cbFrame     += 4;
    … …  
    37423743            "%.*Rhxd\n"
    37433744            "%s < < < < < < < < < < < < <  End of dump > > > > > > > > > > > >\n",
    3744             pState->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pState->szPrf));*/
     3745            pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
    37453746
    37463747    /* Update the stats */
    … …  
    37543755    /* Update octet transmit counter */
    37553756    E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
    3756     if (pState->CTX_SUFF(pDrv))
    3757         STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, cbFrame);
     3757    if (pThis->CTX_SUFF(pDrv))
     3758        STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
    37583759    if (cbFrame == 64)
    37593760        E1K_INC_CNT32(PTC64);
    … …  
    37693770        E1K_INC_CNT32(PTC1522);
    37703771
    3771     E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
     3772    E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
    37723773
    37733774    /*
    … …  
    37753776     */
    37763777    int rc = VERR_NET_DOWN;
    3777     if (pSg && pSg->pvAllocator != pState)
    3778     {
    3779         e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
    3780 
    3781         pState->CTX_SUFF(pTxSg) = NULL;
    3782         PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
     3778    if (pSg && pSg->pvAllocator != pThis)
     3779    {
     3780        e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
     3781
     3782        pThis->CTX_SUFF(pTxSg) = NULL;
     3783        PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
    37833784        if (pDrv)
    37843785        {
    37853786            /* Release critical section to avoid deadlock in CanReceive */
    3786             //e1kCsLeave(pState);
    3787             STAM_PROFILE_START(&pState->CTX_SUFF_Z(StatTransmitSend), a);
     3787            //e1kCsLeave(pThis);
     3788            STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
    37883789            rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
    3789             STAM_PROFILE_STOP(&pState->CTX_SUFF_Z(StatTransmitSend), a);
    3790             //e1kCsEnter(pState, RT_SRC_POS);
     3790            STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
     3791            //e1kCsEnter(pThis, RT_SRC_POS);
    37913792        }
    37923793    }
    37933794    else if (pSg)
    37943795    {
    3795         Assert(pSg->aSegs[0].pvSeg == pState->aTxPacketFallback);
    3796         e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
     3796        Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
     3797        e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
    37973798
    37983799        /** @todo do we actually need to check that we're in loopback mode here? */
    … …  
    38023803            RT_ZERO(status);
    38033804            status.fPIF = true;
    3804             e1kHandleRxPacket(pState, pSg->aSegs[0].pvSeg, cbFrame, status);
     3805            e1kHandleRxPacket(pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
    38053806            rc = VINF_SUCCESS;
    38063807        }
    3807         e1kXmitFreeBuf(pState);
     3808        e1kXmitFreeBuf(pThis);
    38083809    }
    38093810    else
    … …  
    38153816    }
    38163817
    3817     pState->led.Actual.s.fWriting = 0;
     3818    pThis->led.Actual.s.fWriting = 0;
    38183819}
    38193820
    … …  
    38213822 * Compute and write internet checksum (e1kCSum16) at the specified offset.
    38223823 *
    3823  * @param   pState      The device state structure.
     3824 * @param   pThis       The device state structure.
    38243825 * @param   pPkt        Pointer to the packet.
    38253826 * @param   u16PktLen   Total length of the packet.
    … …  
    38313832 * @thread  E1000_TX
    38323833 */
    3833 static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
     3834static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
    38343835{
    38353836    if (css >= u16PktLen)
    38363837    {
    38373838        E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
    3838                  pState->szPrf, cso, u16PktLen));
     3839                 pThis->szPrf, cso, u16PktLen));
    38393840        return;
    38403841    }
    … …  
    38433844    {
    38443845        E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
    3845                  pState->szPrf, cso, u16PktLen));
     3846                 pThis->szPrf, cso, u16PktLen));
    38463847        return;
    38473848    }
    … …  
    38503851        cse = u16PktLen - 1;
    38513852    uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
    3852     E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pState->szPrf,
     3853    E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
    38533854             u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
    38543855    *(uint16_t*)(pPkt + cso) = u16ChkSum;
    … …  
    38623863 *          legacy.u64BufAddr.
    38633864 *
    3864  * @param   pState          The device state structure.
     3865 * @param   pThis          The device state structure.
    38653866 * @param   pDesc           Pointer to the descriptor to transmit.
    38663867 * @param   u16Len          Length of buffer to the end of segment.
    … …  
    38703871 */
    38713872#ifndef E1K_WITH_TXD_CACHE
    3872 static void e1kFallbackAddSegment(E1KSTATE* pState, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
     3873static void e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
    38733874{
    38743875    /* TCP header being transmitted */
    38753876    struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
    3876             (pState->aTxPacketFallback + pState->contextTSE.tu.u8CSS);
     3877            (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
    38773878    /* IP header being transmitted */
    38783879    struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
    3879             (pState->aTxPacketFallback + pState->contextTSE.ip.u8CSS);
     3880            (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
    38803881
    38813882    E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
    3882              pState->szPrf, u16Len, pState->u32PayRemain, pState->u16HdrRemain, fSend));
    3883     Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
    3884 
    3885     PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), PhysAddr,
    3886                       pState->aTxPacketFallback + pState->u16TxPktLen, u16Len);
     3883             pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
     3884    Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
     3885
     3886    PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
     3887                      pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
    38873888    E1kLog3(("%s Dump of the segment:\n"
    38883889            "%.*Rhxd\n"
    38893890            "%s --- End of dump ---\n",
    3890             pState->szPrf, u16Len, pState->aTxPacketFallback + pState->u16TxPktLen, pState->szPrf));
    3891     pState->u16TxPktLen += u16Len;
    3892     E1kLog3(("%s e1kFallbackAddSegment: pState->u16TxPktLen=%x\n",
    3893             pState->szPrf, pState->u16TxPktLen));
    3894     if (pState->u16HdrRemain > 0)
     3891            pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
     3892    pThis->u16TxPktLen += u16Len;
     3893    E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
     3894            pThis->szPrf, pThis->u16TxPktLen));
     3895    if (pThis->u16HdrRemain > 0)
    38953896    {
    38963897        /* The header was not complete, check if it is now */
    3897         if (u16Len >= pState->u16HdrRemain)
     3898        if (u16Len >= pThis->u16HdrRemain)
    38983899        {
    38993900            /* The rest is payload */
    3900             u16Len -= pState->u16HdrRemain;
    3901             pState->u16HdrRemain = 0;
     3901            u16Len -= pThis->u16HdrRemain;
     3902            pThis->u16HdrRemain = 0;
    39023903            /* Save partial checksum and flags */
    3903             pState->u32SavedCsum = pTcpHdr->chksum;
    3904             pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
     3904            pThis->u32SavedCsum = pTcpHdr->chksum;
     3905            pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
    39053906            /* Clear FIN and PSH flags now and set them only in the last segment */
    39063907            pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
    … …  
    39093910        {
    39103911            /* Still not */
    3911             pState->u16HdrRemain -= u16Len;
     3912            pThis->u16HdrRemain -= u16Len;
    39123913            E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
    3913                     pState->szPrf, pState->u16HdrRemain));
     3914                    pThis->szPrf, pThis->u16HdrRemain));
    39143915            return;
    39153916        }
    39163917    }
    39173918
    3918     pState->u32PayRemain -= u16Len;
     3919    pThis->u32PayRemain -= u16Len;
    39193920
    39203921    if (fSend)
    … …  
    39223923        /* Leave ethernet header intact */
    39233924        /* IP Total Length = payload + headers - ethernet header */
    3924         pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
     3925        pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
    39253926        E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
    3926                 pState->szPrf, ntohs(pIpHdr->total_len)));
     3927                pThis->szPrf, ntohs(pIpHdr->total_len)));
    39273928        /* Update IP Checksum */
    39283929        pIpHdr->chksum = 0;
    3929         e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
    3930                           pState->contextTSE.ip.u8CSO,
    3931                           pState->contextTSE.ip.u8CSS,
    3932                           pState->contextTSE.ip.u16CSE);
     3930        e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
     3931                          pThis->contextTSE.ip.u8CSO,
     3932                          pThis->contextTSE.ip.u8CSS,
     3933                          pThis->contextTSE.ip.u16CSE);
    39333934
    39343935        /* Update TCP flags */
    39353936        /* Restore original FIN and PSH flags for the last segment */
    3936         if (pState->u32PayRemain == 0)
    3937         {
    3938             pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
     3937        if (pThis->u32PayRemain == 0)
     3938        {
     3939            pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
    39393940            E1K_INC_CNT32(TSCTC);
    39403941        }
    39413942        /* Add TCP length to partial pseudo header sum */
    3942         uint32_t csum = pState->u32SavedCsum
    3943                 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
     3943        uint32_t csum = pThis->u32SavedCsum
     3944                + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
    39443945        while (csum >> 16)
    39453946            csum = (csum >> 16) + (csum & 0xFFFF);
    39463947        pTcpHdr->chksum = csum;
    39473948        /* Compute final checksum */
    3948         e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
    3949                           pState->contextTSE.tu.u8CSO,
    3950                           pState->contextTSE.tu.u8CSS,
    3951                           pState->contextTSE.tu.u16CSE);
     3949        e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
     3950                          pThis->contextTSE.tu.u8CSO,
     3951                          pThis->contextTSE.tu.u8CSS,
     3952                          pThis->contextTSE.tu.u16CSE);
    39523953
    39533954        /*
    … …  
    39553956         * we copy of the data.
    39563957         */
    3957         if (!pState->CTX_SUFF(pTxSg))
    3958             e1kXmitAllocBuf(pState, pState->u16TxPktLen + (pState->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
    3959         if (pState->CTX_SUFF(pTxSg))
    3960         {
    3961             Assert(pState->u16TxPktLen <= pState->CTX_SUFF(pTxSg)->cbAvailable);
    3962             Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
    3963             if (pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pState->aTxPacketFallback)
    3964                 memcpy(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->aTxPacketFallback, pState->u16TxPktLen);
    3965             pState->CTX_SUFF(pTxSg)->cbUsed         = pState->u16TxPktLen;
    3966             pState->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pState->u16TxPktLen;
     3958        if (!pThis->CTX_SUFF(pTxSg))
     3959            e1kXmitAllocBuf(pThis, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
     3960        if (pThis->CTX_SUFF(pTxSg))
     3961        {
     3962            Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
     3963            Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
     3964            if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
     3965                memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
     3966            pThis->CTX_SUFF(pTxSg)->cbUsed         = pThis->u16TxPktLen;
     3967            pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
    39673968        }
    3968         e1kTransmitFrame(pState, fOnWorkerThread);
     3969        e1kTransmitFrame(pThis, fOnWorkerThread);
    39693970
    39703971        /* Update Sequence Number */
    3971         pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
    3972                                - pState->contextTSE.dw3.u8HDRLEN);
     3972        pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
     3973                               - pThis->contextTSE.dw3.u8HDRLEN);
    39733974        /* Increment IP identification */
    39743975        pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
    … …  
    39763977}
    39773978#else /* E1K_WITH_TXD_CACHE */
    3978 static int e1kFallbackAddSegment(E1KSTATE* pState, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
     3979static int e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
    39793980{
    39803981    int rc = VINF_SUCCESS;
    39813982    /* TCP header being transmitted */
    39823983    struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
    3983             (pState->aTxPacketFallback + pState->contextTSE.tu.u8CSS);
     3984            (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
    39843985    /* IP header being transmitted */
    39853986    struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
    3986             (pState->aTxPacketFallback + pState->contextTSE.ip.u8CSS);
     3987            (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
    39873988
    39883989    E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
    3989              pState->szPrf, u16Len, pState->u32PayRemain, pState->u16HdrRemain, fSend));
    3990     Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
    3991 
    3992     PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), PhysAddr,
    3993                       pState->aTxPacketFallback + pState->u16TxPktLen, u16Len);
     3990             pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
     3991    Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
     3992
     3993    PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
     3994                      pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
    39943995    E1kLog3(("%s Dump of the segment:\n"
    39953996            "%.*Rhxd\n"
    39963997            "%s --- End of dump ---\n",
    3997             pState->szPrf, u16Len, pState->aTxPacketFallback + pState->u16TxPktLen, pState->szPrf));
    3998     pState->u16TxPktLen += u16Len;
    3999     E1kLog3(("%s e1kFallbackAddSegment: pState->u16TxPktLen=%x\n",
    4000             pState->szPrf, pState->u16TxPktLen));
    4001     if (pState->u16HdrRemain > 0)
     3998            pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
     3999    pThis->u16TxPktLen += u16Len;
     4000    E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
     4001            pThis->szPrf, pThis->u16TxPktLen));
     4002    if (pThis->u16HdrRemain > 0)
    40024003    {
    40034004        /* The header was not complete, check if it is now */
    4004         if (u16Len >= pState->u16HdrRemain)
     4005        if (u16Len >= pThis->u16HdrRemain)
    40054006        {
    40064007            /* The rest is payload */
    4007             u16Len -= pState->u16HdrRemain;
    4008             pState->u16HdrRemain = 0;
     4008            u16Len -= pThis->u16HdrRemain;
     4009            pThis->u16HdrRemain = 0;
    40094010            /* Save partial checksum and flags */
    4010             pState->u32SavedCsum = pTcpHdr->chksum;
    4011             pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
     4011            pThis->u32SavedCsum = pTcpHdr->chksum;
     4012            pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
    40124013            /* Clear FIN and PSH flags now and set them only in the last segment */
    40134014            pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
    … …  
    40164017        {
    40174018            /* Still not */
    4018             pState->u16HdrRemain -= u16Len;
     4019            pThis->u16HdrRemain -= u16Len;
    40194020            E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
    4020                     pState->szPrf, pState->u16HdrRemain));
     4021                    pThis->szPrf, pThis->u16HdrRemain));
    40214022            return rc;
    40224023        }
    40234024    }
    40244025
    4025     pState->u32PayRemain -= u16Len;
     4026    pThis->u32PayRemain -= u16Len;
    40264027
    40274028    if (fSend)
    … …  
    40294030        /* Leave ethernet header intact */
    40304031        /* IP Total Length = payload + headers - ethernet header */
    4031         pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
     4032        pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
    40324033        E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
    4033                 pState->szPrf, ntohs(pIpHdr->total_len)));
     4034                pThis->szPrf, ntohs(pIpHdr->total_len)));
    40344035        /* Update IP Checksum */
    40354036        pIpHdr->chksum = 0;
    4036         e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
    4037                           pState->contextTSE.ip.u8CSO,
    4038                           pState->contextTSE.ip.u8CSS,
    4039                           pState->contextTSE.ip.u16CSE);
     4037        e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
     4038                          pThis->contextTSE.ip.u8CSO,
     4039                          pThis->contextTSE.ip.u8CSS,
     4040                          pThis->contextTSE.ip.u16CSE);
    40404041
    40414042        /* Update TCP flags */
    40424043        /* Restore original FIN and PSH flags for the last segment */
    4043         if (pState->u32PayRemain == 0)
    4044         {
    4045             pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
     4044        if (pThis->u32PayRemain == 0)
     4045        {
     4046            pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
    40464047            E1K_INC_CNT32(TSCTC);
    40474048        }
    40484049        /* Add TCP length to partial pseudo header sum */
    4049         uint32_t csum = pState->u32SavedCsum
    4050                 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
     4050        uint32_t csum = pThis->u32SavedCsum
     4051                + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
    40514052        while (csum >> 16)
    40524053            csum = (csum >> 16) + (csum & 0xFFFF);
    40534054        pTcpHdr->chksum = csum;
    40544055        /* Compute final checksum */
    4055         e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
    4056                           pState->contextTSE.tu.u8CSO,
    4057                           pState->contextTSE.tu.u8CSS,
    4058                           pState->contextTSE.tu.u16CSE);
     4056        e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
     4057                          pThis->contextTSE.tu.u8CSO,
     4058                          pThis->contextTSE.tu.u8CSS,
     4059                          pThis->contextTSE.tu.u16CSE);
    40594060
    40604061        /*
    40614062         * Transmit it.
    40624063         */
    4063         if (pState->CTX_SUFF(pTxSg))
    4064         {
    4065             Assert(pState->u16TxPktLen <= pState->CTX_SUFF(pTxSg)->cbAvailable);
    4066             Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
    4067             if (pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pState->aTxPacketFallback)
    4068                 memcpy(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->aTxPacketFallback, pState->u16TxPktLen);
    4069             pState->CTX_SUFF(pTxSg)->cbUsed         = pState->u16TxPktLen;
    4070             pState->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pState->u16TxPktLen;
     4064        if (pThis->CTX_SUFF(pTxSg))
     4065        {
     4066            Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
     4067            Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
     4068            if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
     4069                memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
     4070            pThis->CTX_SUFF(pTxSg)->cbUsed         = pThis->u16TxPktLen;
     4071            pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
    40714072        }
    4072         e1kTransmitFrame(pState, fOnWorkerThread);
     4073        e1kTransmitFrame(pThis, fOnWorkerThread);
    40734074
    40744075        /* Update Sequence Number */
    4075         pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
    4076                                - pState->contextTSE.dw3.u8HDRLEN);
     4076        pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
     4077                               - pThis->contextTSE.dw3.u8HDRLEN);
    40774078        /* Increment IP identification */
    40784079        pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
    40794080
    40804081        /* Allocate new buffer for the next segment. */
    4081         if (pState->u32PayRemain)
    4082         {
    4083             pState->cbTxAlloc = RT_MIN(pState->u32PayRemain,
    4084                                        pState->contextTSE.dw3.u16MSS)
    4085                                 + pState->contextTSE.dw3.u8HDRLEN
    4086                                 + (pState->fVTag ? 4 : 0);
    4087             rc = e1kXmitAllocBuf(pState, false /* fGSO */);
     4082        if (pThis->u32PayRemain)
     4083        {
     4084            pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
     4085                                       pThis->contextTSE.dw3.u16MSS)
     4086                                + pThis->contextTSE.dw3.u8HDRLEN
     4087                                + (pThis->fVTag ? 4 : 0);
     4088            rc = e1kXmitAllocBuf(pThis, false /* fGSO */);
    40884089        }
    40894090    }
    … …  
    41034104 * @returns true if the frame should be transmitted, false if not.
    41044105 *
    4105  * @param   pState          The device state structure.
     4106 * @param   pThis          The device state structure.
    41064107 * @param   pDesc           Pointer to the descriptor to transmit.
    41074108 * @param   cbFragment      Length of descriptor's buffer.
    … …  
    41094110 * @thread  E1000_TX
    41104111 */
    4111 static bool e1kFallbackAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
    4112 {
    4113     PPDMSCATTERGATHER pTxSg = pState->CTX_SUFF(pTxSg);
     4112static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
     4113{
     4114    PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
    41144115    Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
    41154116    Assert(pDesc->data.cmd.fTSE);
    41164117    Assert(!e1kXmitIsGsoBuf(pTxSg));
    41174118
    4118     uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
     4119    uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
    41194120    Assert(u16MaxPktLen != 0);
    41204121    Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
    … …  
    41264127    {
    41274128        /* Calculate how many bytes we have left in this TCP segment */
    4128         uint32_t cb = u16MaxPktLen - pState->u16TxPktLen;
     4129        uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
    41294130        if (cb > cbFragment)
    41304131        {
    41314132            /* This descriptor fits completely into current segment */
    41324133            cb = cbFragment;
    4133             e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
     4134            e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
    41344135        }
    41354136        else
    41364137        {
    4137             e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
     4138            e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
    41384139            /*
    41394140             * Rewind the packet tail pointer to the beginning of payload,
    41404141             * so we continue writing right beyond the header.
    41414142             */
    4142             pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
     4143            pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
    41434144        }
    41444145
    … …  
    41504151    {
    41514152        /* End of packet, next segment will contain header. */
    4152         if (pState->u32PayRemain != 0)
     4153        if (pThis->u32PayRemain != 0)
    41534154            E1K_INC_CNT32(TSCTFC);
    4154         pState->u16TxPktLen = 0;
    4155         e1kXmitFreeBuf(pState);
     4155        pThis->u16TxPktLen = 0;
     4156        e1kXmitFreeBuf(pThis);
    41564157    }
    41574158
    … …  
    41684169 * @returns error code
    41694170 *
    4170  * @param   pState          The device state structure.
     4171 * @param   pThis          The device state structure.
    41714172 * @param   pDesc           Pointer to the descriptor to transmit.
    41724173 * @param   cbFragment      Length of descriptor's buffer.
    … …  
    41744175 * @thread  E1000_TX
    41754176 */
    4176 static int e1kFallbackAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, bool fOnWorkerThread)
     4177static int e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC* pDesc, bool fOnWorkerThread)
    41774178{
    41784179    int rc = VINF_SUCCESS;
    4179     PPDMSCATTERGATHER pTxSg = pState->CTX_SUFF(pTxSg);
     4180    PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
    41804181    Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
    41814182    Assert(pDesc->data.cmd.fTSE);
    41824183    Assert(!e1kXmitIsGsoBuf(pTxSg));
    41834184
    4184     uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
     4185    uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
    41854186    Assert(u16MaxPktLen != 0);
    41864187    Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
    … …  
    41924193    {
    41934194        /* Calculate how many bytes we have left in this TCP segment */
    4194         uint32_t cb = u16MaxPktLen - pState->u16TxPktLen;
     4195        uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
    41954196        if (cb > pDesc->data.cmd.u20DTALEN)
    41964197        {
    41974198            /* This descriptor fits completely into current segment */
    41984199            cb = pDesc->data.cmd.u20DTALEN;
    4199             rc = e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
     4200            rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
    42004201        }
    42014202        else
    42024203        {
    4203             rc = e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
     4204            rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
    42044205            /*
    42054206             * Rewind the packet tail pointer to the beginning of payload,
    42064207             * so we continue writing right beyond the header.
    42074208             */
    4208             pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
     4209            pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
    42094210        }
    42104211
    … …  
    42164217    {
    42174218        /* End of packet, next segment will contain header. */
    4218         if (pState->u32PayRemain != 0)
     4219        if (pThis->u32PayRemain != 0)
    42194220            E1K_INC_CNT32(TSCTFC);
    4220         pState->u16TxPktLen = 0;
    4221         e1kXmitFreeBuf(pState);
     4221        pThis->u16TxPktLen = 0;
     4222        e1kXmitFreeBuf(pThis);
    42224223    }
    42234224
    … …  
    42404241 * @thread  E1000_TX
    42414242 */
    4242 static bool e1kAddToFrame(E1KSTATE *pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
     4243static bool e1kAddToFrame(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
    42434244{
    42444245    PPDMSCATTERGATHER   pTxSg    = pThis->CTX_SUFF(pTxSg);
    … …  
    42764277 * Write the descriptor back to guest memory and notify the guest.
    42774278 *
    4278  * @param   pState      The device state structure.
     4279 * @param   pThis       The device state structure.
    42794280 * @param   pDesc       Pointer to the descriptor have been transmitted.
    42804281 * @param   addr        Physical address of the descriptor in guest memory.
    42814282 * @thread  E1000_TX
    42824283 */
    4283 static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
     4284static void e1kDescReport(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
    42844285{
    42854286    /*
    … …  
    43054306    {
    43064307        pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
    4307         e1kWriteBackDesc(pState, pDesc, addr);
     4308        e1kWriteBackDesc(pThis, pDesc, addr);
    43084309        if (pDesc->legacy.cmd.fEOP)
    43094310        {
    … …  
    43114312            if (pDesc->legacy.cmd.fIDE)
    43124313            {
    4313                 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
    4314                 //if (pState->fIntRaised)
     4314                E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
     4315                //if (pThis->fIntRaised)
    43154316                //{
    43164317                //    /* Interrupt is already pending, no need for timers */
    … …  
    43194320                //else {
    43204321                /* Arm the timer to fire in TIVD usec (discard .024) */
    4321                 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
     4322                e1kArmTimer(pThis, pThis->CTX_SUFF(pTIDTimer), TIDV);
    43224323# ifndef E1K_NO_TAD
    43234324                /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
    43244325                E1kLog2(("%s Checking if TAD timer is running\n",
    4325                          pState->szPrf));
    4326                 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
    4327                     e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
     4326                         pThis->szPrf));
     4327                if (TADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pTADTimer)))
     4328                    e1kArmTimer(pThis, pThis->CTX_SUFF(pTADTimer), TADV);
    43284329# endif /* E1K_NO_TAD */
    43294330            }
    … …  
    43314332            {
    43324333                E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
    4333                         pState->szPrf));
     4334                        pThis->szPrf));
    43344335# ifndef E1K_NO_TAD
    43354336                /* Cancel both timers if armed and fire immediately. */
    4336                 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
     4337                e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
    43374338# endif /* E1K_NO_TAD */
    43384339#endif /* E1K_USE_TX_TIMERS */
    4339                 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
    4340                 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
     4340                E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
     4341                e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXDW);
    43414342#ifdef E1K_USE_TX_TIMERS
    43424343            }
    … …  
    43464347    else
    43474348    {
    4348         E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
     4349        E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
    43494350    }
    43504351}
    43514352
    43524353#ifndef E1K_WITH_TXD_CACHE
     4354
    43534355/**
    43544356 * Process Transmit Descriptor.
    … …  
    43594361 * - context  sets up the context for following data descriptors.
    43604362 *
    4361  * @param   pState          The device state structure.
     4363 * @param   pThis          The device state structure.
    43624364 * @param   pDesc           Pointer to descriptor union.
    43634365 * @param   addr            Physical address of descriptor in guest memory.
    … …  
    43654367 * @thread  E1000_TX
    43664368 */
    4367 static int e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
     4369static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
    43684370{
    43694371    int rc = VINF_SUCCESS;
    43704372    uint32_t cbVTag = 0;
    43714373
    4372     e1kPrintTDesc(pState, pDesc, "vvv");
     4374    e1kPrintTDesc(pThis, pDesc, "vvv");
    43734375
    43744376#ifdef E1K_USE_TX_TIMERS
    4375     e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
     4377    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
    43764378#endif /* E1K_USE_TX_TIMERS */
    43774379
    … …  
    43814383            if (pDesc->context.dw2.fTSE)
    43824384            {
    4383                 pState->contextTSE = pDesc->context;
    4384                 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
    4385                 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
    4386                 e1kSetupGsoCtx(&pState->GsoCtx, &pDesc->context);
    4387                 STAM_COUNTER_INC(&pState->StatTxDescCtxTSE);
     4385                pThis->contextTSE = pDesc->context;
     4386                pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
     4387                pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
     4388                e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
     4389                STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
    43884390            }
    43894391            else
    43904392            {
    4391                 pState->contextNormal = pDesc->context;
    4392                 STAM_COUNTER_INC(&pState->StatTxDescCtxNormal);
     4393                pThis->contextNormal = pDesc->context;
     4394                STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
    43934395            }
    43944396            E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
    4395                     ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pState->szPrf,
     4397                    ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
    43964398                     pDesc->context.dw2.fTSE ? "TSE" : "Normal",
    43974399                     pDesc->context.ip.u8CSS,
    … …  
    44014403                     pDesc->context.tu.u8CSO,
    44024404                     pDesc->context.tu.u16CSE));
    4403             E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
    4404             e1kDescReport(pState, pDesc, addr);
     4405            E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
     4406            e1kDescReport(pThis, pDesc, addr);
    44054407            break;
    44064408
    … …  
    44094411            if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
    44104412            {
    4411                 E1kLog2(("% Empty data descriptor, skipped.\n", pState->szPrf));
     4413                E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
    44124414                /** @todo Same as legacy when !TSE. See below. */
    44134415                break;
    44144416            }
    44154417            STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
    4416                              &pState->StatTxDescTSEData:
    4417                              &pState->StatTxDescData);
    4418             STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
    4419             E1K_INC_ISTAT_CNT(pState->uStatDescDat);
     4418                             &pThis->StatTxDescTSEData:
     4419                             &pThis->StatTxDescData);
     4420            STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
     4421            E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
    44204422
    44214423            /*
    … …  
    44284430            if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
    44294431            {
    4430                 pState->fVTag      = pDesc->data.cmd.fVLE;
    4431                 pState->u16VTagTCI = pDesc->data.dw3.u16Special;
     4432                pThis->fVTag      = pDesc->data.cmd.fVLE;
     4433                pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
    44324434            }
    44334435            /*
    … …  
    44354437             * packet options as these are only valid in the first fragment.
    44364438             */
    4437             if (pState->u16TxPktLen == 0)
     4439            if (pThis->u16TxPktLen == 0)
    44384440            {
    4439                 pState->fIPcsum  = pDesc->data.dw3.fIXSM;
    4440                 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
    4441                 E1kLog2(("%s Saving checksum flags:%s%s; \n", pState->szPrf,
    4442                          pState->fIPcsum ? " IP" : "",
    4443                          pState->fTCPcsum ? " TCP/UDP" : ""));
     4441                pThis->fIPcsum  = pDesc->data.dw3.fIXSM;
     4442                pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
     4443                E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
     4444                         pThis->fIPcsum ? " IP" : "",
     4445                         pThis->fTCPcsum ? " TCP/UDP" : ""));
    44444446                if (pDesc->data.cmd.fTSE)
    44454447                {
    4446                     /* 2) pDesc->data.cmd.fTSE && pState->u16TxPktLen == 0 */
    4447                     pState->fVTag      = pDesc->data.cmd.fVLE;
    4448                     pState->u16VTagTCI = pDesc->data.dw3.u16Special;
    4449                     cbVTag = pState->fVTag ? 4 : 0;
     4448                    /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
     4449                    pThis->fVTag      = pDesc->data.cmd.fVLE;
     4450                    pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
     4451                    cbVTag = pThis->fVTag ? 4 : 0;
    44504452                }
    44514453                else if (pDesc->data.cmd.fEOP)
    … …  
    44534455                else
    44544456                    cbVTag = 4;
    4455                 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pState->szPrf, cbVTag));
    4456                 if (e1kCanDoGso(pState, &pState->GsoCtx, &pDesc->data, &pState->contextTSE))
    4457                     rc = e1kXmitAllocBuf(pState, pState->contextTSE.dw2.u20PAYLEN + pState->contextTSE.dw3.u8HDRLEN + cbVTag,
     4457                E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
     4458                if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
     4459                    rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
    44584460                                    true /*fExactSize*/, true /*fGso*/);
    44594461                else if (pDesc->data.cmd.fTSE)
    4460                     rc = e1kXmitAllocBuf(pState, pState->contextTSE.dw3.u16MSS + pState->contextTSE.dw3.u8HDRLEN + cbVTag,
     4462                    rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
    44614463                                         pDesc->data.cmd.fTSE  /*fExactSize*/, false /*fGso*/);
    44624464                else
    4463                     rc = e1kXmitAllocBuf(pState, pDesc->data.cmd.u20DTALEN + cbVTag,
     4465                    rc = e1kXmitAllocBuf(pThis, pDesc->data.cmd.u20DTALEN + cbVTag,
    44644466                                         pDesc->data.cmd.fEOP  /*fExactSize*/, false /*fGso*/);
    44654467
    … …  
    44704472                if (RT_FAILURE(rc))
    44714473                {
    4472                     STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4474                    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    44734475                    break;
    44744476                }
    … …  
    44814483             * transmit it and reset the u16TxPktLen field.
    44824484             */
    4483             if (e1kXmitIsGsoBuf(pState->CTX_SUFF(pTxSg)))
     4485            if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
    44844486            {
    4485                 STAM_COUNTER_INC(&pState->StatTxPathGSO);
    4486                 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
     4487                STAM_COUNTER_INC(&pThis->StatTxPathGSO);
     4488                bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
    44874489                if (pDesc->data.cmd.fEOP)
    44884490                {
    44894491                    if (   fRc
    4490                         && pState->CTX_SUFF(pTxSg)
    4491                         && pState->CTX_SUFF(pTxSg)->cbUsed == (size_t)pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN)
     4492                        && pThis->CTX_SUFF(pTxSg)
     4493                        && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
    44924494                    {
    4493                         e1kTransmitFrame(pState, fOnWorkerThread);
     4495                        e1kTransmitFrame(pThis, fOnWorkerThread);
    44944496                        E1K_INC_CNT32(TSCTC);
    44954497                    }
    … …  
    44974499                    {
    44984500                        if (fRc)
    4499                            E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pState->szPrf,
    4500                                    pState->CTX_SUFF(pTxSg), pState->CTX_SUFF(pTxSg) ? pState->CTX_SUFF(pTxSg)->cbUsed : 0,
    4501                                    pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN));
    4502                         e1kXmitFreeBuf(pState);
     4501                           E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
     4502                                   pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
     4503                                   pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
     4504                        e1kXmitFreeBuf(pThis);
    45034505                        E1K_INC_CNT32(TSCTFC);
    45044506                    }
    4505                     pState->u16TxPktLen = 0;
     4507                    pThis->u16TxPktLen = 0;
    45064508                }
    45074509            }
    45084510            else if (!pDesc->data.cmd.fTSE)
    45094511            {
    4510                 STAM_COUNTER_INC(&pState->StatTxPathRegular);
    4511                 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
     4512                STAM_COUNTER_INC(&pThis->StatTxPathRegular);
     4513                bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
    45124514                if (pDesc->data.cmd.fEOP)
    45134515                {
    4514                     if (fRc && pState->CTX_SUFF(pTxSg))
     4516                    if (fRc && pThis->CTX_SUFF(pTxSg))
    45154517                    {
    4516                         Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
    4517                         if (pState->fIPcsum)
    4518                             e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
    4519                                               pState->contextNormal.ip.u8CSO,
    4520                                               pState->contextNormal.ip.u8CSS,
    4521                                               pState->contextNormal.ip.u16CSE);
    4522                         if (pState->fTCPcsum)
    4523                             e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
    4524                                               pState->contextNormal.tu.u8CSO,
    4525                                               pState->contextNormal.tu.u8CSS,
    4526                                               pState->contextNormal.tu.u16CSE);
    4527                         e1kTransmitFrame(pState, fOnWorkerThread);
     4518                        Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
     4519                        if (pThis->fIPcsum)
     4520                            e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
     4521                                              pThis->contextNormal.ip.u8CSO,
     4522                                              pThis->contextNormal.ip.u8CSS,
     4523                                              pThis->contextNormal.ip.u16CSE);
     4524                        if (pThis->fTCPcsum)
     4525                            e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
     4526                                              pThis->contextNormal.tu.u8CSO,
     4527                                              pThis->contextNormal.tu.u8CSS,
     4528                                              pThis->contextNormal.tu.u16CSE);
     4529                        e1kTransmitFrame(pThis, fOnWorkerThread);
    45284530                    }
    45294531                    else
    4530                         e1kXmitFreeBuf(pState);
    4531                     pState->u16TxPktLen = 0;
     4532                        e1kXmitFreeBuf(pThis);
     4533                    pThis->u16TxPktLen = 0;
    45324534                }
    45334535            }
    45344536            else
    45354537            {
    4536                 STAM_COUNTER_INC(&pState->StatTxPathFallback);
    4537                 e1kFallbackAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
     4538                STAM_COUNTER_INC(&pThis->StatTxPathFallback);
     4539                e1kFallbackAddToFrame(pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
    45384540            }
    45394541
    4540             e1kDescReport(pState, pDesc, addr);
    4541             STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4542            e1kDescReport(pThis, pDesc, addr);
     4543            STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    45424544            break;
    45434545        }
    … …  
    45464548            if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
    45474549            {
    4548                 E1kLog(("%s Empty legacy descriptor, skipped.\n", pState->szPrf));
     4550                E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
    45494551                /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
    45504552                break;
    45514553            }
    4552             STAM_COUNTER_INC(&pState->StatTxDescLegacy);
    4553             STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
     4554            STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
     4555            STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
    45544556
    45554557            /* First fragment: allocate new buffer. */
    4556             if (pState->u16TxPktLen == 0)
     4558            if (pThis->u16TxPktLen == 0)
    45574559            {
    45584560                if (pDesc->legacy.cmd.fEOP)
    … …  
    45604562                else
    45614563                    cbVTag = 4;
    4562                 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pState->szPrf, cbVTag));
     4564                E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
    45634565                /** @todo reset status bits? */
    4564                 rc = e1kXmitAllocBuf(pState, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
     4566                rc = e1kXmitAllocBuf(pThis, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
    45654567                if (RT_FAILURE(rc))
    45664568                {
    4567                     STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4569                    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    45684570                    break;
    45694571                }
    … …  
    45744576
    45754577            /* Add fragment to frame. */
    4576             if (e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
     4578            if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
    45774579            {
    4578                 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
     4580                E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
    45794581
    45804582                /* Last fragment: Transmit and reset the packet storage counter.  */
    45814583                if (pDesc->legacy.cmd.fEOP)
    45824584                {
    4583                     pState->fVTag       = pDesc->legacy.cmd.fVLE;
    4584                     pState->u16VTagTCI  = pDesc->legacy.dw3.u16Special;
     4585                    pThis->fVTag       = pDesc->legacy.cmd.fVLE;
     4586                    pThis->u16VTagTCI  = pDesc->legacy.dw3.u16Special;
    45854587                    /** @todo Offload processing goes here. */
    4586                     e1kTransmitFrame(pState, fOnWorkerThread);
    4587                     pState->u16TxPktLen = 0;
     4588                    e1kTransmitFrame(pThis, fOnWorkerThread);
     4589                    pThis->u16TxPktLen = 0;
    45884590                }
    45894591            }
    … …  
    45914593            else if (pDesc->legacy.cmd.fEOP)
    45924594            {
    4593                 e1kXmitFreeBuf(pState);
    4594                 pState->u16TxPktLen = 0;
     4595                e1kXmitFreeBuf(pThis);
     4596                pThis->u16TxPktLen = 0;
    45954597            }
    45964598
    4597             e1kDescReport(pState, pDesc, addr);
    4598             STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4599            e1kDescReport(pThis, pDesc, addr);
     4600            STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    45994601            break;
    46004602
    46014603        default:
    46024604            E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
    4603                     pState->szPrf, e1kGetDescType(pDesc)));
     4605                    pThis->szPrf, e1kGetDescType(pDesc)));
    46044606            break;
    46054607    }
    … …  
    46074609    return rc;
    46084610}
     4611
    46094612#else /* E1K_WITH_TXD_CACHE */
     4613
    46104614/**
    46114615 * Process Transmit Descriptor.
    … …  
    46164620 * - context  sets up the context for following data descriptors.
    46174621 *
    4618  * @param   pState          The device state structure.
     4622 * @param   pThis          The device state structure.
    46194623 * @param   pDesc           Pointer to descriptor union.
    46204624 * @param   addr            Physical address of descriptor in guest memory.
    … …  
    46234627 * @thread  E1000_TX
    46244628 */
    4625 static int e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr,
     4629static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr,
    46264630                       bool fOnWorkerThread)
    46274631{
    … …  
    46294633    uint32_t cbVTag = 0;
    46304634
    4631     e1kPrintTDesc(pState, pDesc, "vvv");
     4635    e1kPrintTDesc(pThis, pDesc, "vvv");
    46324636
    46334637#ifdef E1K_USE_TX_TIMERS
    4634     e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
     4638    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
    46354639#endif /* E1K_USE_TX_TIMERS */
    46364640
    … …  
    46394643        case E1K_DTYP_CONTEXT:
    46404644            /* The caller have already updated the context */
    4641             E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
    4642             e1kDescReport(pState, pDesc, addr);
     4645            E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
     4646            e1kDescReport(pThis, pDesc, addr);
    46434647            break;
    46444648
    … …  
    46464650        {
    46474651            STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
    4648                              &pState->StatTxDescTSEData:
    4649                              &pState->StatTxDescData);
    4650             E1K_INC_ISTAT_CNT(pState->uStatDescDat);
    4651             STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
     4652                             &pThis->StatTxDescTSEData:
     4653                             &pThis->StatTxDescData);
     4654            E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
     4655            STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
    46524656            if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
    46534657            {
    4654                 E1kLog2(("% Empty data descriptor, skipped.\n", pState->szPrf));
     4658                E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
    46554659            }
    46564660            else
    … …  
    46604664                 * transmit it and reset the u16TxPktLen field.
    46614665                 */
    4662                 if (e1kXmitIsGsoBuf(pState->CTX_SUFF(pTxSg)))
     4666                if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
    46634667                {
    4664                     STAM_COUNTER_INC(&pState->StatTxPathGSO);
    4665                     bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
     4668                    STAM_COUNTER_INC(&pThis->StatTxPathGSO);
     4669                    bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
    46664670                    if (pDesc->data.cmd.fEOP)
    46674671                    {
    46684672                        if (   fRc
    4669                             && pState->CTX_SUFF(pTxSg)
    4670                             && pState->CTX_SUFF(pTxSg)->cbUsed == (size_t)pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN)
     4673                            && pThis->CTX_SUFF(pTxSg)
     4674                            && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
    46714675                        {
    4672                             e1kTransmitFrame(pState, fOnWorkerThread);
     4676                            e1kTransmitFrame(pThis, fOnWorkerThread);
    46734677                            E1K_INC_CNT32(TSCTC);
    46744678                        }
    … …  
    46764680                        {
    46774681                            if (fRc)
    4678                                 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pState->szPrf,
    4679                                         pState->CTX_SUFF(pTxSg), pState->CTX_SUFF(pTxSg) ? pState->CTX_SUFF(pTxSg)->cbUsed : 0,
    4680                                         pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN));
    4681                             e1kXmitFreeBuf(pState);
     4682                                E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
     4683                                        pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
     4684                                        pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
     4685                            e1kXmitFreeBuf(pThis);
    46824686                            E1K_INC_CNT32(TSCTFC);
    46834687                        }
    4684                         pState->u16TxPktLen = 0;
     4688                        pThis->u16TxPktLen = 0;
    46854689                    }
    46864690                }
    46874691                else if (!pDesc->data.cmd.fTSE)
    46884692                {
    4689                     STAM_COUNTER_INC(&pState->StatTxPathRegular);
    4690                     bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
     4693                    STAM_COUNTER_INC(&pThis->StatTxPathRegular);
     4694                    bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
    46914695                    if (pDesc->data.cmd.fEOP)
    46924696                    {
    4693                         if (fRc && pState->CTX_SUFF(pTxSg))
     4697                        if (fRc && pThis->CTX_SUFF(pTxSg))
    46944698                        {
    4695                             Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
    4696                             if (pState->fIPcsum)
    4697                                 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
    4698                                                   pState->contextNormal.ip.u8CSO,
    4699                                                   pState->contextNormal.ip.u8CSS,
    4700                                                   pState->contextNormal.ip.u16CSE);
    4701                             if (pState->fTCPcsum)
    4702                                 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
    4703                                                   pState->contextNormal.tu.u8CSO,
    4704                                                   pState->contextNormal.tu.u8CSS,
    4705                                                   pState->contextNormal.tu.u16CSE);
    4706                             e1kTransmitFrame(pState, fOnWorkerThread);
     4699                            Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
     4700                            if (pThis->fIPcsum)
     4701                                e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
     4702                                                  pThis->contextNormal.ip.u8CSO,
     4703                                                  pThis->contextNormal.ip.u8CSS,
     4704                                                  pThis->contextNormal.ip.u16CSE);
     4705                            if (pThis->fTCPcsum)
     4706                                e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
     4707                                                  pThis->contextNormal.tu.u8CSO,
     4708                                                  pThis->contextNormal.tu.u8CSS,
     4709                                                  pThis->contextNormal.tu.u16CSE);
     4710                            e1kTransmitFrame(pThis, fOnWorkerThread);
    47074711                        }
    47084712                        else
    4709                             e1kXmitFreeBuf(pState);
    4710                         pState->u16TxPktLen = 0;
     4713                            e1kXmitFreeBuf(pThis);
     4714                        pThis->u16TxPktLen = 0;
    47114715                    }
    47124716                }
    47134717                else
    47144718                {
    4715                     STAM_COUNTER_INC(&pState->StatTxPathFallback);
    4716                     rc = e1kFallbackAddToFrame(pState, pDesc, fOnWorkerThread);
     4719                    STAM_COUNTER_INC(&pThis->StatTxPathFallback);
     4720                    rc = e1kFallbackAddToFrame(pThis, pDesc, fOnWorkerThread);
    47174721                }
    47184722            }
    4719             e1kDescReport(pState, pDesc, addr);
    4720             STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4723            e1kDescReport(pThis, pDesc, addr);
     4724            STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    47214725            break;
    47224726        }
    47234727
    47244728        case E1K_DTYP_LEGACY:
    4725             STAM_COUNTER_INC(&pState->StatTxDescLegacy);
    4726             STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
     4729            STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
     4730            STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
    47274731            if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
    47284732            {
    4729                 E1kLog(("%s Empty legacy descriptor, skipped.\n", pState->szPrf));
     4733                E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
    47304734            }
    47314735            else
    47324736            {
    47334737                /* Add fragment to frame. */
    4734                 if (e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
     4738                if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
    47354739                {
    4736                     E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
     4740                    E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
    47374741
    47384742                    /* Last fragment: Transmit and reset the packet storage counter.  */
    … …  
    47414745                        if (pDesc->legacy.cmd.fIC)
    47424746                        {
    4743                             e1kInsertChecksum(pState,
    4744                                               (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
    4745                                               pState->u16TxPktLen,
     4747                            e1kInsertChecksum(pThis,
     4748                                              (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
     4749                                              pThis->u16TxPktLen,
    47464750                                              pDesc->legacy.cmd.u8CSO,
    47474751                                              pDesc->legacy.dw3.u8CSS,
    47484752                                              0);
    47494753                        }
    4750                         e1kTransmitFrame(pState, fOnWorkerThread);
    4751                         pState->u16TxPktLen = 0;
     4754                        e1kTransmitFrame(pThis, fOnWorkerThread);
     4755                        pThis->u16TxPktLen = 0;
    47524756                    }
    47534757                }
    … …  
    47554759                else if (pDesc->legacy.cmd.fEOP)
    47564760                {
    4757                     e1kXmitFreeBuf(pState);
    4758                     pState->u16TxPktLen = 0;
     4761                    e1kXmitFreeBuf(pThis);
     4762                    pThis->u16TxPktLen = 0;
    47594763                }
    47604764            }
    4761             e1kDescReport(pState, pDesc, addr);
    4762             STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4765            e1kDescReport(pThis, pDesc, addr);
     4766            STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    47634767            break;
    47644768
    47654769        default:
    47664770            E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
    4767                     pState->szPrf, e1kGetDescType(pDesc)));
     4771                    pThis->szPrf, e1kGetDescType(pDesc)));
    47684772            break;
    47694773    }
    … …  
    47724776}
    47734777
    4774 
    4775 DECLINLINE(void) e1kUpdateTxContext(E1KSTATE* pState, E1KTXDESC* pDesc)
     4778DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC* pDesc)
    47764779{
    47774780    if (pDesc->context.dw2.fTSE)
    47784781    {
    4779         pState->contextTSE = pDesc->context;
    4780         pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
    4781         pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
    4782         e1kSetupGsoCtx(&pState->GsoCtx, &pDesc->context);
    4783         STAM_COUNTER_INC(&pState->StatTxDescCtxTSE);
     4782        pThis->contextTSE = pDesc->context;
     4783        pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
     4784        pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
     4785        e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
     4786        STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
    47844787    }
    47854788    else
    47864789    {
    4787         pState->contextNormal = pDesc->context;
    4788         STAM_COUNTER_INC(&pState->StatTxDescCtxNormal);
     4790        pThis->contextNormal = pDesc->context;
     4791        STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
    47894792    }
    47904793    E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
    4791              ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pState->szPrf,
     4794             ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
    47924795             pDesc->context.dw2.fTSE ? "TSE" : "Normal",
    47934796             pDesc->context.ip.u8CSS,
    … …  
    47994802}
    48004803
    4801 
    4802 static bool e1kLocateTxPacket(E1KSTATE *pState)
     4804static bool e1kLocateTxPacket(PE1KSTATE pThis)
    48034805{
    48044806    LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
    4805              pState->szPrf, pState->cbTxAlloc));
     4807             pThis->szPrf, pThis->cbTxAlloc));
    48064808    /* Check if we have located the packet already. */
    4807     if (pState->cbTxAlloc)
     4809    if (pThis->cbTxAlloc)
    48084810    {
    48094811        LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
    4810                  pState->szPrf, pState->cbTxAlloc));
     4812                 pThis->szPrf, pThis->cbTxAlloc));
    48114813        return true;
    48124814    }
    … …  
    48154817    uint32_t cbPacket = 0;
    48164818
    4817     for (int i = pState->iTxDCurrent; i < pState->nTxDFetched; ++i)
    4818     {
    4819         E1KTXDESC *pDesc = &pState->aTxDescriptors[i];
     4819    for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
     4820    {
     4821        E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
    48204822        switch (e1kGetDescType(pDesc))
    48214823        {
    48224824            case E1K_DTYP_CONTEXT:
    4823                 e1kUpdateTxContext(pState, pDesc);
     4825                e1kUpdateTxContext(pThis, pDesc);
    48244826                continue;
    48254827            case E1K_DTYP_LEGACY:
    … …  
    48284830                    break;
    48294831                cbPacket += pDesc->legacy.cmd.u16Length;
    4830                 pState->fGSO = false;
     4832                pThis->fGSO = false;
    48314833                break;
    48324834            case E1K_DTYP_DATA:
    … …  
    48404842                     * as these are only valid in the first fragment.
    48414843                     */
    4842                     pState->fIPcsum  = pDesc->data.dw3.fIXSM;
    4843                     pState->fTCPcsum = pDesc->data.dw3.fTXSM;
     4844                    pThis->fIPcsum  = pDesc->data.dw3.fIXSM;
     4845                    pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
    48444846                            fTSE     = pDesc->data.cmd.fTSE;
    48454847                    /*
    … …  
    48494851                    if (fTSE)
    48504852                    {
    4851                         pState->fVTag = pDesc->data.cmd.fVLE;
    4852                         pState->u16VTagTCI = pDesc->data.dw3.u16Special;
     4853                        pThis->fVTag = pDesc->data.cmd.fVLE;
     4854                        pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
    48534855                    }
    4854                     pState->fGSO = e1kCanDoGso(pState, &pState->GsoCtx, &pDesc->data, &pState->contextTSE);
     4856                    pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
    48554857                }
    48564858                cbPacket += pDesc->data.cmd.u20DTALEN;
    … …  
    48674869            if (!fTSE)
    48684870            {
    4869                 pState->fVTag = pDesc->data.cmd.fVLE;
    4870                 pState->u16VTagTCI = pDesc->data.dw3.u16Special;
     4871                pThis->fVTag = pDesc->data.cmd.fVLE;
     4872                pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
    48714873            }
    48724874            /*
    … …  
    48744876             * have to do segmentation we allocate the first segment only.
    48754877             */
    4876             pState->cbTxAlloc = (!fTSE || pState->fGSO) ?
     4878            pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
    48774879                cbPacket :
    4878                 RT_MIN(cbPacket, pState->contextTSE.dw3.u16MSS + pState->contextTSE.dw3.u8HDRLEN);
    4879             if (pState->fVTag)
    4880                 pState->cbTxAlloc += 4;
     4880                RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
     4881            if (pThis->fVTag)
     4882                pThis->cbTxAlloc += 4;
    48814883            LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
    4882                      pState->szPrf, pState->cbTxAlloc));
     4884                     pThis->szPrf, pThis->cbTxAlloc));
    48834885            return true;
    48844886        }
    48854887    }
    48864888
    4887     if (cbPacket == 0 && pState->nTxDFetched - pState->iTxDCurrent > 0)
     4889    if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
    48884890    {
    48894891        /* All descriptors were empty, we need to process them as a dummy packet */
    48904892        LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
    4891                  pState->szPrf, pState->cbTxAlloc));
     4893                 pThis->szPrf, pThis->cbTxAlloc));
    48924894        return true;
    48934895    }
    48944896    LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d\n",
    4895              pState->szPrf, pState->cbTxAlloc));
     4897             pThis->szPrf, pThis->cbTxAlloc));
    48964898    return false;
    48974899}
    48984900
    4899 
    4900 static int e1kXmitPacket(E1KSTATE *pState, bool fOnWorkerThread)
     4901static int e1kXmitPacket(PE1KSTATE pThis, bool fOnWorkerThread)
    49014902{
    49024903    int rc = VINF_SUCCESS;
    49034904
    49044905    LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
    4905              pState->szPrf, pState->iTxDCurrent, pState->nTxDFetched));
    4906 
    4907     while (pState->iTxDCurrent < pState->nTxDFetched)
    4908     {
    4909         E1KTXDESC *pDesc = &pState->aTxDescriptors[pState->iTxDCurrent];
     4906             pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
     4907
     4908    while (pThis->iTxDCurrent < pThis->nTxDFetched)
     4909    {
     4910        E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
    49104911        E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
    4911                  pState->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
    4912         rc = e1kXmitDesc(pState, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
     4912                 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
     4913        rc = e1kXmitDesc(pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
    49134914        if (RT_FAILURE(rc))
    49144915            break;
    … …  
    49164917            TDH = 0;
    49174918        uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
    4918         if (uLowThreshold != 0 && e1kGetTxLen(pState) <= uLowThreshold)
     4919        if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
    49194920        {
    49204921            E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
    4921                      pState->szPrf, e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
    4922             e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
     4922                     pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
     4923            e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
    49234924        }
    4924         ++pState->iTxDCurrent;
     4925        ++pThis->iTxDCurrent;
    49254926        if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
    49264927            break;
    … …  
    49284929
    49294930    LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
    4930              pState->szPrf, rc, pState->iTxDCurrent, pState->nTxDFetched));
     4931             pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
    49314932    return rc;
    49324933}
     4934
    49334935#endif /* E1K_WITH_TXD_CACHE */
    4934 
    49354936#ifndef E1K_WITH_TXD_CACHE
     4937
    49364938/**
    49374939 * Transmit pending descriptors.
    … …  
    49394941 * @returns VBox status code.  VERR_TRY_AGAIN is returned if we're busy.
    49404942 *
    4941  * @param   pState              The E1000 state.
     4943 * @param   pThis              The E1000 state.
    49424944 * @param   fOnWorkerThread     Whether we're on a worker thread or on an EMT.
    49434945 */
    4944 static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread)
     4946static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
    49454947{
    49464948    int rc = VINF_SUCCESS;
    … …  
    49524954     * Grab the xmit lock of the driver as well as the E1K device state.
    49534955     */
    4954     rc = e1kCsTxEnter(pState, VERR_SEM_BUSY);
     4956    rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
    49554957    if (RT_LIKELY(rc == VINF_SUCCESS))
    49564958    {
    4957         PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
     4959        PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
    49584960        if (pDrv)
    49594961        {
    … …  
    49614963            if (RT_FAILURE(rc))
    49624964            {
    4963                 e1kCsTxLeave(pState);
     4965                e1kCsTxLeave(pThis);
    49644966                return rc;
    49654967            }
    … …  
    49694971         * Note! Do not process descriptors in locked state
    49704972         */
    4971         while (TDH != TDT && !pState->fLocked)
     4973        while (TDH != TDT && !pThis->fLocked)
    49724974        {
    49734975            E1KTXDESC desc;
    49744976            E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
    4975                      pState->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
    4976 
    4977             e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
    4978             rc = e1kXmitDesc(pState, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
     4977                     pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
     4978
     4979            e1kLoadDesc(pThis, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
     4980            rc = e1kXmitDesc(pThis, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
    49794981            /* If we failed to transmit descriptor we will try it again later */
    49804982            if (RT_FAILURE(rc))
    … …  
    49834985                TDH = 0;
    49844986
    4985             if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
     4987            if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
    49864988            {
    49874989                E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
    4988                          pState->szPrf, e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
    4989                 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
     4990                         pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
     4991                e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
    49904992            }
    49914993
    4992             STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
     4994            STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
    49934995        }
    49944996
    4995         /// @todo: uncomment: pState->uStatIntTXQE++;
    4996         /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
     4997        /// @todo: uncomment: pThis->uStatIntTXQE++;
     4998        /// @todo: uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
    49974999        /*
    49985000         * Release the lock.
    … …  
    50005002        if (pDrv)
    50015003            pDrv->pfnEndXmit(pDrv);
    5002         e1kCsTxLeave(pState);
     5004        e1kCsTxLeave(pThis);
    50035005    }
    50045006
    50055007    return rc;
    50065008}
     5009
    50075010#else /* E1K_WITH_TXD_CACHE */
    5008 static void e1kDumpTxDCache(E1KSTATE *pState)
     5011
     5012static void e1kDumpTxDCache(PE1KSTATE pThis)
    50095013{
    50105014    unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
    … …  
    50145018    {
    50155019        E1KTXDESC desc;
    5016         PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(TDBAH, TDBAL, i),
     5020        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(TDBAH, TDBAL, i),
    50175021                          &desc, sizeof(desc));
    50185022        if (i == tdh)
    … …  
    50215025    }
    50225026    LogRel(("-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
    5023             pState->iTxDCurrent, TDH, pState->nTxDFetched, E1K_TXD_CACHE_SIZE));
    5024     if (tdh > pState->iTxDCurrent)
    5025         tdh -= pState->iTxDCurrent;
     5027            pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
     5028    if (tdh > pThis->iTxDCurrent)
     5029        tdh -= pThis->iTxDCurrent;
    50265030    else
    5027         tdh = cDescs + tdh - pState->iTxDCurrent;
    5028     for (i = 0; i < pState->nTxDFetched; ++i)
    5029     {
    5030         if (i == pState->iTxDCurrent)
     5031        tdh = cDescs + tdh - pThis->iTxDCurrent;
     5032    for (i = 0; i < pThis->nTxDFetched; ++i)
     5033    {
     5034        if (i == pThis->iTxDCurrent)
    50315035            LogRel((">>> "));
    5032         LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pState->aTxDescriptors[i]));
     5036        LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
    50335037    }
    50345038}
    … …  
    50395043 * @returns VBox status code.  VERR_TRY_AGAIN is returned if we're busy.
    50405044 *
    5041  * @param   pState              The E1000 state.
     5045 * @param   pThis              The E1000 state.
    50425046 * @param   fOnWorkerThread     Whether we're on a worker thread or on an EMT.
    50435047 */
    5044 static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread)
     5048static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
    50455049{
    50465050    int rc = VINF_SUCCESS;
    … …  
    50525056     * Grab the xmit lock of the driver as well as the E1K device state.
    50535057     */
    5054     PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
     5058    PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
    50555059    if (pDrv)
    50565060    {
    … …  
    50645068     * Note! Do not process descriptors in locked state
    50655069     */
    5066     rc = e1kCsTxEnter(pState, VERR_SEM_BUSY);
     5070    rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
    50675071    if (RT_LIKELY(rc == VINF_SUCCESS))
    50685072    {
    5069         STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
     5073        STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
    50705074        /*
    50715075         * fIncomplete is set whenever we try to fetch additional descriptors
    … …  
    50755079         */
    50765080        bool fIncomplete = false;
    5077         while (!pState->fLocked && e1kTxDLazyLoad(pState))
    5078         {
    5079             while (e1kLocateTxPacket(pState))
     5081        while (!pThis->fLocked && e1kTxDLazyLoad(pThis))
     5082        {
     5083            while (e1kLocateTxPacket(pThis))
    50805084            {
    50815085                fIncomplete = false;
    50825086                /* Found a complete packet, allocate it. */
    5083                 rc = e1kXmitAllocBuf(pState, pState->fGSO);
     5087                rc = e1kXmitAllocBuf(pThis, pThis->fGSO);
    50845088                /* If we're out of bandwidth we'll come back later. */
    50855089                if (RT_FAILURE(rc))
    50865090                    goto out;
    50875091                /* Copy the packet to allocated buffer and send it. */
    5088                 rc = e1kXmitPacket(pState, fOnWorkerThread);
     5092                rc = e1kXmitPacket(pThis, fOnWorkerThread);
    50895093                /* If we're out of bandwidth we'll come back later. */
    50905094                if (RT_FAILURE(rc))
    50915095                    goto out;
    50925096            }
    5093             uint8_t u8Remain = pState->nTxDFetched - pState->iTxDCurrent;
     5097            uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
    50945098            if (RT_UNLIKELY(fIncomplete))
    50955099            {
    … …  
    51025106                LogRel(("%s No complete packets in%s TxD cache! "
    51035107                      "Fetched=%d, current=%d, TX len=%d.\n",
    5104                       pState->szPrf,
     5108                      pThis->szPrf,
    51055109                      u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
    5106                       pState->nTxDFetched, pState->iTxDCurrent,
    5107                       e1kGetTxLen(pState)));
     5110                      pThis->nTxDFetched, pThis->iTxDCurrent,
     5111                      e1kGetTxLen(pThis)));
    51085112                if (!fTxDCacheDumped)
    51095113                {
    51105114                    fTxDCacheDumped = true;
    5111                     e1kDumpTxDCache(pState);
     5115                    e1kDumpTxDCache(pThis);
    51125116                }
    5113                 pState->iTxDCurrent = pState->nTxDFetched = 0;
     5117                pThis->iTxDCurrent = pThis->nTxDFetched = 0;
    51145118                /*
    51155119                 * Returning an error at this point means Guru in R0
    … …  
    51275131                Log4(("%s Incomplete packet at %d. Already fetched %d, "
    51285132                      "%d more are available\n",
    5129                       pState->szPrf, pState->iTxDCurrent, u8Remain,
    5130                       e1kGetTxLen(pState) - u8Remain));
     5133                      pThis->szPrf, pThis->iTxDCurrent, u8Remain,
     5134                      e1kGetTxLen(pThis) - u8Remain));
    51315135
    51325136                /*
    … …  
    51345138                 * the beginning of cache buffer, then load more descriptors.
    51355139                 */
    5136                 memmove(pState->aTxDescriptors,
    5137                         &pState->aTxDescriptors[pState->iTxDCurrent],
     5140                memmove(pThis->aTxDescriptors,
     5141                        &pThis->aTxDescriptors[pThis->iTxDCurrent],
    51385142                        u8Remain * sizeof(E1KTXDESC));
    5139                 pState->iTxDCurrent = 0;
    5140                 pState->nTxDFetched = u8Remain;
    5141                 e1kTxDLoadMore(pState);
     5143                pThis->iTxDCurrent = 0;
     5144                pThis->nTxDFetched = u8Remain;
     5145                e1kTxDLoadMore(pThis);
    51425146                fIncomplete = true;
    51435147            }
    51445148            else
    5145                 pState->nTxDFetched = 0;
    5146             pState->iTxDCurrent = 0;
     5149                pThis->nTxDFetched = 0;
     5150            pThis->iTxDCurrent = 0;
    51475151        }
    5148         if (!pState->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
     5152        if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
    51495153        {
    51505154            E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
    5151                      pState->szPrf));
    5152             e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
     5155                     pThis->szPrf));
     5156            e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
    51535157        }
    51545158out:
    5155         STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
    5156 
    5157         /// @todo: uncomment: pState->uStatIntTXQE++;
    5158         /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
    5159 
    5160         e1kCsTxLeave(pState);
     5159        STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
     5160
     5161        /// @todo: uncomment: pThis->uStatIntTXQE++;
     5162        /// @todo: uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
     5163
     5164        e1kCsTxLeave(pThis);
    51615165    }
    51625166
    … …  
    51695173    return rc;
    51705174}
     5175
    51715176#endif /* E1K_WITH_TXD_CACHE */
    5172 
    51735177#ifdef IN_RING3
    51745178
    … …  
    51785182static DECLCALLBACK(void) e1kNetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
    51795183{
    5180     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
     5184    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
    51815185    /* Resume suspended transmission */
    51825186    STATUS &= ~STATUS_TXOFF;
    5183     e1kXmitPending(pState, true /*fOnWorkerThread*/);
     5187    e1kXmitPending(pThis, true /*fOnWorkerThread*/);
    51845188}
    51855189
    … …  
    51965200{
    51975201    NOREF(pItem);
    5198     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    5199     E1kLog2(("%s e1kTxQueueConsumer:\n", pState->szPrf));
    5200 
    5201     int rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
     5202    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     5203    E1kLog2(("%s e1kTxQueueConsumer:\n", pThis->szPrf));
     5204
     5205    int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
    52025206    AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
    52035207
    … …  
    52195223 * Write handler for Transmit Descriptor Tail register.
    52205224 *
    5221  * @param   pState      The device state structure.
     5225 * @param   pThis       The device state structure.
    52225226 * @param   offset      Register offset in memory-mapped frame.
    52235227 * @param   index       Register index in register array.
    … …  
    52265230 * @thread  EMT
    52275231 */
    5228 static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    5229 {
    5230     int rc = e1kRegWriteDefault(pState, offset, index, value);
     5232static int e1kRegWriteTDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     5233{
     5234    int rc = e1kRegWriteDefault(pThis, offset, index, value);
    52315235
    52325236    /* All descriptors starting with head and not including tail belong to us. */
    52335237    /* Process them. */
    52345238    E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
    5235             pState->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
     5239            pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
    52365240
    52375241    /* Ignore TDT writes when the link is down. */
    52385242    if (TDH != TDT && (STATUS & STATUS_LU))
    52395243    {
    5240         E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
     5244        E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pThis)));
    52415245        E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
    5242                  pState->szPrf, e1kGetTxLen(pState)));
     5246                 pThis->szPrf, e1kGetTxLen(pThis)));
    52435247
    52445248        /* Transmit pending packets if possible, defer it if we cannot do it
    52455249           in the current context. */
    52465250#ifdef E1K_TX_DELAY
    5247         rc = e1kCsTxEnter(pState, VERR_SEM_BUSY);
     5251        rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
    52485252        if (RT_LIKELY(rc == VINF_SUCCESS))
    52495253        {
    5250             if (!TMTimerIsActive(pState->CTX_SUFF(pTXDTimer)))
     5254            if (!TMTimerIsActive(pThis->CTX_SUFF(pTXDTimer)))
    52515255            {
    52525256#ifdef E1K_INT_STATS
    5253                 pState->u64ArmedAt = RTTimeNanoTS();
     5257                pThis->u64ArmedAt = RTTimeNanoTS();
    52545258#endif
    5255                 e1kArmTimer(pState, pState->CTX_SUFF(pTXDTimer), E1K_TX_DELAY);
     5259                e1kArmTimer(pThis, pThis->CTX_SUFF(pTXDTimer), E1K_TX_DELAY);
    52565260            }
    5257             E1K_INC_ISTAT_CNT(pState->uStatTxDelayed);
    5258             e1kCsTxLeave(pState);
     5261            E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
     5262            e1kCsTxLeave(pThis);
    52595263            return rc;
    52605264        }
    … …  
    52625266#endif /* E1K_TX_DELAY */
    52635267#ifndef IN_RING3
    5264         if (!pState->CTX_SUFF(pDrv))
    5265         {
    5266             PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
     5268        if (!pThis->CTX_SUFF(pDrv))
     5269        {
     5270            PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pTxQueue));
    52675271            if (RT_UNLIKELY(pItem))
    5268                 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
     5272                PDMQueueInsert(pThis->CTX_SUFF(pTxQueue), pItem);
    52695273        }
    52705274        else
    52715275#endif
    52725276        {
    5273             rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
     5277            rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
    52745278            if (rc == VERR_TRY_AGAIN)
    52755279                rc = VINF_SUCCESS;
    … …  
    52865290 * Write handler for Multicast Table Array registers.
    52875291 *
    5288  * @param   pState      The device state structure.
     5292 * @param   pThis       The device state structure.
    52895293 * @param   offset      Register offset in memory-mapped frame.
    52905294 * @param   index       Register index in register array.
    … …  
    52925296 * @thread  EMT
    52935297 */
    5294 static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    5295 {
    5296     AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
    5297     pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
     5298static int e1kRegWriteMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     5299{
     5300    AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
     5301    pThis->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pThis->auMTA[0])] = value;
    52985302
    52995303    return VINF_SUCCESS;
    … …  
    53055309 * @returns VBox status code.
    53065310 *
    5307  * @param   pState      The device state structure.
     5311 * @param   pThis       The device state structure.
    53085312 * @param   offset      Register offset in memory-mapped frame.
    53095313 * @param   index       Register index in register array.
    53105314 * @thread  EMT
    53115315 */
    5312 static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    5313 {
    5314     AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
    5315     *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
     5316static int e1kRegReadMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     5317{
     5318    AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
     5319    *pu32Value = pThis->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
    53165320
    53175321    return VINF_SUCCESS;
    … …  
    53215325 * Write handler for Receive Address registers.
    53225326 *
    5323  * @param   pState      The device state structure.
     5327 * @param   pThis       The device state structure.
    53245328 * @param   offset      Register offset in memory-mapped frame.
    53255329 * @param   index       Register index in register array.
    … …  
    53275331 * @thread  EMT
    53285332 */
    5329 static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    5330 {
    5331     AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
    5332     pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
     5333static int e1kRegWriteRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     5334{
     5335    AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
     5336    pThis->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
    53335337
    53345338    return VINF_SUCCESS;
    … …  
    53405344 * @returns VBox status code.
    53415345 *
    5342  * @param   pState      The device state structure.
     5346 * @param   pThis       The device state structure.
    53435347 * @param   offset      Register offset in memory-mapped frame.
    53445348 * @param   index       Register index in register array.
    53455349 * @thread  EMT
    53465350 */
    5347 static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    5348 {
    5349     AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
    5350     *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
     5351static int e1kRegReadRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     5352{
     5353    AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
     5354    *pu32Value = pThis->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
    53515355
    53525356    return VINF_SUCCESS;
    … …  
    53565360 * Write handler for VLAN Filter Table Array registers.
    53575361 *
    5358  * @param   pState      The device state structure.
     5362 * @param   pThis       The device state structure.
    53595363 * @param   offset      Register offset in memory-mapped frame.
    53605364 * @param   index       Register index in register array.
    … …  
    53625366 * @thread  EMT
    53635367 */
    5364 static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
    5365 {
    5366     AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
    5367     pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
     5368static int e1kRegWriteVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
     5369{
     5370    AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
     5371    pThis->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
    53685372
    53695373    return VINF_SUCCESS;
    … …  
    53755379 * @returns VBox status code.
    53765380 *
    5377  * @param   pState      The device state structure.
     5381 * @param   pThis       The device state structure.
    53785382 * @param   offset      Register offset in memory-mapped frame.
    53795383 * @param   index       Register index in register array.
    53805384 * @thread  EMT
    53815385 */
    5382 static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    5383 {
    5384     AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
    5385     *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
     5386static int e1kRegReadVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     5387{
     5388    AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
     5389    *pu32Value = pThis->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
    53865390
    53875391    return VINF_SUCCESS;
    … …  
    53955399 * @returns VBox status code.
    53965400 *
    5397  * @param   pState      The device state structure.
     5401 * @param   pThis       The device state structure.
    53985402 * @param   offset      Register offset in memory-mapped frame.
    53995403 * @param   index       Register index in register array.
    54005404 * @thread  EMT
    54015405 */
    5402 
    5403 static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     5406static int e1kRegReadUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    54045407{
    54055408    E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
    5406             pState->szPrf, offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
     5409            pThis->szPrf, offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
    54075410    *pu32Value = 0;
    54085411
    … …  
    54215424 * @returns VBox status code.
    54225425 *
    5423  * @param   pState      The device state structure.
     5426 * @param   pThis       The device state structure.
    54245427 * @param   offset      Register offset in memory-mapped frame.
    54255428 * @param   index       Register index in register array.
    54265429 * @thread  EMT
    54275430 */
    5428 
    5429 static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     5431static int e1kRegReadAutoClear(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    54305432{
    54315433    AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
    5432     int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
    5433     pState->auRegs[index] = 0;
     5434    int rc = e1kRegReadDefault(pThis, offset, index, pu32Value);
     5435    pThis->auRegs[index] = 0;
    54345436
    54355437    return rc;
    … …  
    54475449 * @returns VBox status code.
    54485450 *
    5449  * @param   pState      The device state structure.
     5451 * @param   pThis       The device state structure.
    54505452 * @param   offset      Register offset in memory-mapped frame.
    54515453 * @param   index       Register index in register array.
    54525454 * @thread  EMT
    54535455 */
    5454 
    5455 static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     5456static int e1kRegReadDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    54565457{
    54575458    AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
    5458     *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
     5459    *pu32Value = pThis->auRegs[index] & s_e1kRegMap[index].readable;
    54595460
    54605461    return VINF_SUCCESS;
    … …  
    54665467 * Merely reports writes to unimplemented registers.
    54675468 *
    5468  * @param   pState      The device state structure.
     5469 * @param   pThis       The device state structure.
    54695470 * @param   offset      Register offset in memory-mapped frame.
    54705471 * @param   index       Register index in register array.
    … …  
    54735474 */
    54745475
    5475  static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     5476 static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    54765477{
    54775478    E1kLog(("%s At %08X write attempt (%08X) to  unimplemented register %s (%s)\n",
    5478             pState->szPrf, offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
     5479            pThis->szPrf, offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
    54795480
    54805481    return VINF_SUCCESS;
    … …  
    54895490 * @returns VBox status code.
    54905491 *
    5491  * @param   pState      The device state structure.
     5492 * @param   pThis       The device state structure.
    54925493 * @param   offset      Register offset in memory-mapped frame.
    54935494 * @param   index       Register index in register array.
    … …  
    54975498 */
    54985499
    5499 static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
     5500static int e1kRegWriteDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
    55005501{
    55015502    AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
    5502     pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
    5503             (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
     5503    pThis->auRegs[index] = (value & s_e1kRegMap[index].writable) |
     5504            (pThis->auRegs[index] & ~s_e1kRegMap[index].writable);
    55045505
    55055506    return VINF_SUCCESS;
    … …  
    55115512 * @returns Index in the register table or -1 if not found.
    55125513 *
    5513  * @param   pState      The device state structure.
    5514  * @param   uOffset     Register offset in memory-mapped region.
     5514 * @param   pThis       The device state structure.
     5515 * @param   offReg      Register offset in memory-mapped region.
    55155516 * @thread  EMT
    55165517 */
    5517 static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
     5518static int e1kRegLookup(PE1KSTATE pThis, uint32_t offReg)
    55185519{
    55195520    int index;
    … …  
    55215522    for (index = 0; index < E1K_NUM_OF_REGS; index++)
    55225523    {
    5523         if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
     5524        if (s_e1kRegMap[index].offset <= offReg && offReg < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
    55245525        {
    55255526            return index;
    … …  
    55375538 * @returns VBox status code.
    55385539 *
    5539  * @param   pState      The device state structure.
    5540  * @param   uOffset     Register offset in memory-mapped frame.
     5540 * @param   pThis       The device state structure.
     5541 * @param   offReg      Register offset in memory-mapped frame.
    55415542 * @param   pv          Where to store the result.
    55425543 * @param   cb          Number of bytes to read.
    55435544 * @thread  EMT
    55445545 */
    5545 static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
     5546static int e1kRegRead(PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
    55465547{
    55475548    uint32_t    u32    = 0;
    … …  
    55495550    uint32_t    shift;
    55505551    int         rc     = VINF_SUCCESS;
    5551     int         index  = e1kRegLookup(pState, uOffset);
    5552     const char *szInst = pState->szPrf;
     5552    int         index  = e1kRegLookup(pThis, offReg);
    55535553#ifdef DEBUG
    55545554    char        buf[9];
    … …  
    55735573        case 4: mask = 0xFFFFFFFF; break;
    55745574        default:
    5575             return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
     5575            return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
    55765576                                     "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
    5577                                      szInst, uOffset, cb);
     5577                                     pThis->szPrf, offReg, cb);
    55785578    }
    55795579    if (index != -1)
    … …  
    55825582        {
    55835583            /* Make the mask correspond to the bits we are about to read. */
    5584             shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
     5584            shift = (offReg - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
    55855585            mask <<= shift;
    55865586            if (!mask)
    5587                 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
     5587                return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
    55885588                                         "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
    5589                                          szInst, uOffset, cb);
     5589                                         pThis->szPrf, offReg, cb);
    55905590            /*
    55915591             * Read it. Pass the mask so the handler knows what has to be read.
    55925592             * Mask out irrelevant bits.
    55935593             */
    5594             //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
     5594            //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
    55955595            if (RT_UNLIKELY(rc != VINF_SUCCESS))
    55965596                return rc;
    5597             //pState->fDelayInts = false;
    5598             //pState->iStatIntLost += pState->iStatIntLostOne;
    5599             //pState->iStatIntLostOne = 0;
    5600             rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32);
     5597            //pThis->fDelayInts = false;
     5598            //pThis->iStatIntLost += pThis->iStatIntLostOne;
     5599            //pThis->iStatIntLostOne = 0;
     5600            rc = s_e1kRegMap[index].pfnRead(pThis, offReg & 0xFFFFFFFC, index, &u32);
    56015601            u32 &= mask;
    5602             //e1kCsLeave(pState);
     5602            //e1kCsLeave(pThis);
    56035603            E1kLog2(("%s At %08X read  %s          from %s (%s)\n",
    5604                     szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
     5604                    pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
    56055605            /* Shift back the result. */
    56065606            u32 >>= shift;
    … …  
    56095609        {
    56105610            E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
    5611                     szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
     5611                    pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
    56125612        }
    56135613    }
    … …  
    56155615    {
    56165616        E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
    5617                 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
     5617                pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
    56185618    }
    56195619
    … …  
    56295629 * @returns VBox status code.
    56305630 *
    5631  * @param   pState      The device state structure.
     5631 * @param   pThis       The device state structure.
    56325632 * @param   offReg      Register offset in memory-mapped frame.
    56335633 * @param   pv          Where to fetch the value.
    … …  
    56355635 * @thread  EMT
    56365636 */
    5637 static int e1kRegWrite(E1KSTATE *pState, uint32_t offReg, void const *pv, unsigned cb)
     5637static int e1kRegWrite(PE1KSTATE pThis, uint32_t offReg, void const *pv, unsigned cb)
    56385638{
    56395639    int         rc     = VINF_SUCCESS;
    5640     int         index  = e1kRegLookup(pState, offReg);
     5640    int         index  = e1kRegLookup(pThis, offReg);
    56415641    uint32_t    u32;
    56425642
    … …  
    56505650    {
    56515651        E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
    5652                 pState->szPrf, offReg, cb));
     5652                pThis->szPrf, offReg, cb));
    56535653        return VINF_SUCCESS;
    56545654    }
    … …  
    56565656    {
    56575657        E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
    5658                 pState->szPrf, offReg, cb));
     5658                pThis->szPrf, offReg, cb));
    56595659        return VINF_SUCCESS;
    56605660    }
    … …  
    56695669             */
    56705670            E1kLog2(("%s At %08X write          %08X  to  %s (%s)\n",
    5671                      pState->szPrf, offReg, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
    5672             //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
     5671                     pThis->szPrf, offReg, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
     5672            //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
    56735673            if (RT_UNLIKELY(rc != VINF_SUCCESS))
    56745674                return rc;
    5675             //pState->fDelayInts = false;
    5676             //pState->iStatIntLost += pState->iStatIntLostOne;
    5677             //pState->iStatIntLostOne = 0;
    5678             rc = s_e1kRegMap[index].pfnWrite(pState, offReg, index, u32);
    5679             //e1kCsLeave(pState);
     5675            //pThis->fDelayInts = false;
     5676            //pThis->iStatIntLost += pThis->iStatIntLostOne;
     5677            //pThis->iStatIntLostOne = 0;
     5678            rc = s_e1kRegMap[index].pfnWrite(pThis, offReg, index, u32);
     5679            //e1kCsLeave(pThis);
    56805680        }
    56815681        else
    56825682        {
    56835683            E1kLog(("%s At %08X write attempt (%08X) to  read-only register %s (%s)\n",
    5684                     pState->szPrf, offReg, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
     5684                    pThis->szPrf, offReg, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
    56855685        }
    56865686    }
    … …  
    56885688    {
    56895689        E1kLog(("%s At %08X write attempt (%08X) to  non-existing register\n",
    5690                 pState->szPrf, offReg, u32));
     5690                pThis->szPrf, offReg, u32));
    56915691    }
    56925692    return rc;
    … …  
    57115711{
    57125712    NOREF(pvUser);
    5713     E1KSTATE  *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    5714     uint32_t  offReg  = GCPhysAddr - pState->addrMMReg;
    5715     STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIORead), a);
     5713    PE1KSTATE pThis  = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     5714    uint32_t  offReg = GCPhysAddr - pThis->addrMMReg;
     5715    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
    57165716
    57175717    Assert(offReg < E1K_MM_SIZE);
    57185718
    5719     int rc = e1kRegRead(pState, offReg, pv, cb);
    5720     STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIORead), a);
     5719    int rc = e1kRegRead(pThis, offReg, pv, cb);
     5720    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
    57215721    return rc;
    57225722}
    … …  
    57375737{
    57385738    NOREF(pvUser);
    5739     E1KSTATE  *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    5740     uint32_t  offReg  = GCPhysAddr - pState->addrMMReg;
     5739    PE1KSTATE pThis  = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     5740    uint32_t  offReg = GCPhysAddr - pThis->addrMMReg;
    57415741    int       rc;
    5742     STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIOWrite), a);
     5742    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
    57435743
    57445744    Assert(offReg < E1K_MM_SIZE);
    … …  
    57495749    }
    57505750    else
    5751         rc = e1kRegWrite(pState, offReg, pv, cb);
    5752 
    5753     STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIOWrite), a);
     5751        rc = e1kRegWrite(pThis, offReg, pv, cb);
     5752
     5753    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
    57545754    return rc;
    57555755}
    … …  
    57695769PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb)
    57705770{
    5771     E1KSTATE   *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    5772     int         rc     = VINF_SUCCESS;
    5773     const char *szInst = pState->szPrf;
    5774     STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatIORead), a);
    5775 
    5776     port -= pState->addrIOPort;
     5771    PE1KSTATE   pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     5772    int         rc    = VINF_SUCCESS;
     5773    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
     5774
     5775    port -= pThis->addrIOPort;
    57775776    if (cb != 4)
    57785777    {
    5779         E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
    5780         rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
     5778        E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", pThis->szPrf, port, cb));
     5779        rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", pThis->szPrf, port, cb);
    57815780    }
    57825781    else
    … …  
    57845783        {
    57855784            case 0x00: /* IOADDR */
    5786                 *pu32 = pState->uSelectedReg;
    5787                 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
     5785                *pu32 = pThis->uSelectedReg;
     5786                E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
    57885787                break;
    57895788            case 0x04: /* IODATA */
    5790                 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
     5789                rc = e1kRegRead(pThis, pThis->uSelectedReg, pu32, cb);
    57915790                /** @todo wrong return code triggers assertions in the debug build; fix please */
    57925791                if (rc == VINF_IOM_R3_MMIO_READ)
    57935792                    rc = VINF_IOM_R3_IOPORT_READ;
    57945793
    5795                 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
     5794                E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
    57965795                break;
    57975796            default:
    5798                 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
     5797                E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, port));
    57995798        //*pRC = VERR_IOM_IOPORT_UNUSED;
    58005799        }
    58015800
    5802     STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatIORead), a);
     5801    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
    58035802    return rc;
    58045803}
    … …  
    58195818PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
    58205819{
    5821     E1KSTATE   *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
    5822     int         rc     = VINF_SUCCESS;
    5823     const char *szInst = pState->szPrf;
    5824     STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatIOWrite), a);
    5825 
    5826     E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
     5820    PE1KSTATE   pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
     5821    int         rc    = VINF_SUCCESS;
     5822    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
     5823
     5824    E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", pThis->szPrf, port, u32));
    58275825    if (cb != 4)
    58285826    {
    5829         E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
    5830         rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid op size: port=%RTiop cb=%#x\n", szInst, port, cb);
     5827        E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", pThis->szPrf, port, cb));
     5828        rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid op size: port=%RTiop cb=%#x\n", pThis->szPrf, port, cb);
    58315829    }
    58325830    else
    58335831    {
    5834         port -= pState->addrIOPort;
     5832        port -= pThis->addrIOPort;
    58355833        switch (port)
    58365834        {
    58375835            case 0x00: /* IOADDR */
    5838                 pState->uSelectedReg = u32;
    5839                 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
     5836                pThis->uSelectedReg = u32;
     5837                E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
    58405838                break;
    58415839            case 0x04: /* IODATA */
    5842                 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
    5843                 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
     5840                E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
     5841                rc = e1kRegWrite(pThis, pThis->uSelectedReg, &u32, cb);
    58445842                /** @todo wrong return code triggers assertions in the debug build; fix please */
    58455843                if (rc == VINF_IOM_R3_MMIO_WRITE)
    … …  
    58475845                break;
    58485846            default:
    5849                 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
     5847                E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, port));
    58505848                /** @todo Do we need to return an error here?
    58515849                 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
    … …  
    58555853    }
    58565854
    5857     STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatIOWrite), a);
     5855    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
    58585856    return rc;
    58595857}
    … …  
    58645862 * Dump complete device state to log.
    58655863 *
    5866  * @param   pState          Pointer to device state.
    5867  */
    5868 static void e1kDumpState(E1KSTATE *pState)
     5864 * @param   pThis          Pointer to device state.
     5865 */
     5866static void e1kDumpState(PE1KSTATE pThis)
    58695867{
    58705868    for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
    58715869    {
    5872         E1kLog2(("%s %8.8s = %08x\n", pState->szPrf,
    5873                 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
     5870        E1kLog2(("%s %8.8s = %08x\n", pThis->szPrf,
     5871                s_e1kRegMap[i].abbrev, pThis->auRegs[i]));
    58745872    }
    58755873# ifdef E1K_INT_STATS
    5876     LogRel(("%s Interrupt attempts: %d\n", pState->szPrf, pState->uStatIntTry));
    5877     LogRel(("%s Interrupts raised : %d\n", pState->szPrf, pState->uStatInt));
    5878     LogRel(("%s Interrupts lowered: %d\n", pState->szPrf, pState->uStatIntLower));
    5879     LogRel(("%s Interrupts delayed: %d\n", pState->szPrf, pState->uStatIntDly));
    5880     LogRel(("%s Disabled delayed:   %d\n", pState->szPrf, pState->uStatDisDly));
    5881     LogRel(("%s Interrupts skipped: %d\n", pState->szPrf, pState->uStatIntSkip));
    5882     LogRel(("%s Masked interrupts : %d\n", pState->szPrf, pState->uStatIntMasked));
    5883     LogRel(("%s Early interrupts  : %d\n", pState->szPrf, pState->uStatIntEarly));
    5884     LogRel(("%s Late interrupts   : %d\n", pState->szPrf, pState->uStatIntLate));
    5885     LogRel(("%s Lost interrupts   : %d\n", pState->szPrf, pState->iStatIntLost));
    5886     LogRel(("%s Interrupts by RX  : %d\n", pState->szPrf, pState->uStatIntRx));
    5887     LogRel(("%s Interrupts by TX  : %d\n", pState->szPrf, pState->uStatIntTx));
    5888     LogRel(("%s Interrupts by ICS : %d\n", pState->szPrf, pState->uStatIntICS));
    5889     LogRel(("%s Interrupts by RDTR: %d\n", pState->szPrf, pState->uStatIntRDTR));
    5890     LogRel(("%s Interrupts by RDMT: %d\n", pState->szPrf, pState->uStatIntRXDMT0));
    5891     LogRel(("%s Interrupts by TXQE: %d\n", pState->szPrf, pState->uStatIntTXQE));
    5892     LogRel(("%s TX int delay asked: %d\n", pState->szPrf, pState->uStatTxIDE));
    5893     LogRel(("%s TX delayed:         %d\n", pState->szPrf, pState->uStatTxDelayed));
    5894     LogRel(("%s TX delay expired:   %d\n", pState->szPrf, pState->uStatTxDelayExp));
    5895     LogRel(("%s TX no report asked: %d\n", pState->szPrf, pState->uStatTxNoRS));
    5896     LogRel(("%s TX abs timer expd : %d\n", pState->szPrf, pState->uStatTAD));
    5897     LogRel(("%s TX int timer expd : %d\n", pState->szPrf, pState->uStatTID));
    5898     LogRel(("%s RX abs timer expd : %d\n", pState->szPrf, pState->uStatRAD));
    5899     LogRel(("%s RX int timer expd : %d\n", pState->szPrf, pState->uStatRID));
    5900     LogRel(("%s TX CTX descriptors: %d\n", pState->szPrf, pState->uStatDescCtx));
    5901     LogRel(("%s TX DAT descriptors: %d\n", pState->szPrf, pState->uStatDescDat));
    5902     LogRel(("%s TX LEG descriptors: %d\n", pState->szPrf, pState->uStatDescLeg));
    5903     LogRel(("%s Received frames   : %d\n", pState->szPrf, pState->uStatRxFrm));
    5904     LogRel(("%s Transmitted frames: %d\n", pState->szPrf, pState->uStatTxFrm));
    5905     LogRel(("%s TX frames up to 1514: %d\n", pState->szPrf, pState->uStatTx1514));
    5906     LogRel(("%s TX frames up to 2962: %d\n", pState->szPrf, pState->uStatTx2962));
    5907     LogRel(("%s TX frames up to 4410: %d\n", pState->szPrf, pState->uStatTx4410));
    5908     LogRel(("%s TX frames up to 5858: %d\n", pState->szPrf, pState->uStatTx5858));
    5909     LogRel(("%s TX frames up to 7306: %d\n", pState->szPrf, pState->uStatTx7306));
    5910     LogRel(("%s TX frames up to 8754: %d\n", pState->szPrf, pState->uStatTx8754));
    5911     LogRel(("%s TX frames up to 16384: %d\n", pState->szPrf, pState->uStatTx16384));
    5912     LogRel(("%s TX frames up to 32768: %d\n", pState->szPrf, pState->uStatTx32768));
    5913     LogRel(("%s Larger TX frames    : %d\n", pState->szPrf, pState->uStatTxLarge));
    5914     LogRel(("%s Max TX Delay        : %lld\n", pState->szPrf, pState->uStatMaxTxDelay));
     5874    LogRel(("%s Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
     5875    LogRel(("%s Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
     5876    LogRel(("%s Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
     5877    LogRel(("%s Interrupts delayed: %d\n", pThis->szPrf, pThis->uStatIntDly));
     5878    LogRel(("%s Disabled delayed:   %d\n", pThis->szPrf, pThis->uStatDisDly));
     5879    LogRel(("%s Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
     5880    LogRel(("%s Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
     5881    LogRel(("%s Early interrupts  : %d\n", pThis->szPrf, pThis->uStatIntEarly));
     5882    LogRel(("%s Late interrupts   : %d\n", pThis->szPrf, pThis->uStatIntLate));
     5883    LogRel(("%s Lost interrupts   : %d\n", pThis->szPrf, pThis->iStatIntLost));
     5884    LogRel(("%s Interrupts by RX  : %d\n", pThis->szPrf, pThis->uStatIntRx));
     5885    LogRel(("%s Interrupts by TX  : %d\n", pThis->szPrf, pThis->uStatIntTx));
     5886    LogRel(("%s Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
     5887    LogRel(("%s Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
     5888    LogRel(("%s Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
     5889    LogRel(("%s Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
     5890    LogRel(("%s TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
     5891    LogRel(("%s TX delayed:         %d\n", pThis->szPrf, pThis->uStatTxDelayed));
     5892    LogRel(("%s TX delay expired:   %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
     5893    LogRel(("%s TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
     5894    LogRel(("%s TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
     5895    LogRel(("%s TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
     5896    LogRel(("%s RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
     5897    LogRel(("%s RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
     5898    LogRel(("%s TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
     5899    LogRel(("%s TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
     5900    LogRel(("%s TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
     5901    LogRel(("%s Received frames   : %d\n", pThis->szPrf, pThis->uStatRxFrm));
     5902    LogRel(("%s Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
     5903    LogRel(("%s TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
     5904    LogRel(("%s TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
     5905    LogRel(("%s TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
     5906    LogRel(("%s TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
     5907    LogRel(("%s TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
     5908    LogRel(("%s TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
     5909    LogRel(("%s TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
     5910    LogRel(("%s TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
     5911    LogRel(("%s Larger TX frames    : %d\n", pThis->szPrf, pThis->uStatTxLarge));
     5912    LogRel(("%s Max TX Delay        : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
    59155913# endif /* E1K_INT_STATS */
    59165914}
    … …  
    59225920{
    59235921    int       rc;
    5924     E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
     5922    PE1KSTATE pThis = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
    59255923
    59265924    switch (enmType)
    59275925    {
    59285926        case PCI_ADDRESS_SPACE_IO:
    5929             pState->addrIOPort = (RTIOPORT)GCPhysAddress;
    5930             rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
     5927            pThis->addrIOPort = (RTIOPORT)GCPhysAddress;
     5928            rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pThis->addrIOPort, cb, 0,
    59315929                                         e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
    59325930            if (RT_FAILURE(rc))
    59335931                break;
    5934             if (pState->fR0Enabled)
     5932            if (pThis->fR0Enabled)
    59355933            {
    5936                 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
     5934                rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pThis->addrIOPort, cb, 0,
    59375935                                             "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
    59385936                if (RT_FAILURE(rc))
    59395937                    break;
    59405938            }
    5941             if (pState->fGCEnabled)
     5939            if (pThis->fGCEnabled)
    59425940            {
    5943                 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
     5941                rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pThis->addrIOPort, cb, 0,
    59445942                                               "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
    59455943            }
    59465944            break;
    59475945        case PCI_ADDRESS_SPACE_MEM:
    5948             pState->addrMMReg = GCPhysAddress;
     5946            pThis->addrMMReg = GCPhysAddress;
    59495947            rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
    59505948                                       IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
    59515949                                       e1kMMIOWrite, e1kMMIORead, "E1000");
    5952             if (pState->fR0Enabled)
     5950            if (pThis->fR0Enabled)
    59535951            {
    59545952                rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
    … …  
    59575955                    break;
    59585956            }
    5959             if (pState->fGCEnabled)
     5957            if (pThis->fGCEnabled)
    59605958            {
    59615959                rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
    … …  
    59835981 * @thread  EMT
    59845982 */
    5985 static int e1kCanReceive(E1KSTATE *pState)
     5983static int e1kCanReceive(PE1KSTATE pThis)
    59865984{
    59875985#ifndef E1K_WITH_RXD_CACHE
    59885986    size_t cb;
    59895987
    5990     if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
     5988    if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
    59915989        return VERR_NET_NO_BUFFER_SPACE;
    59925990
    … …  
    59945992    {
    59955993        E1KRXDESC desc;
    5996         PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
     5994        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
    59975995                          &desc, sizeof(desc));
    59985996        if (desc.status.fDD)
    59995997            cb = 0;
    60005998        else
    6001             cb = pState->u16RxBSize;
     5999            cb = pThis->u16RxBSize;
    60026000    }
    60036001    else if (RDH < RDT)
    6004         cb = (RDT - RDH) * pState->u16RxBSize;
     6002        cb = (RDT - RDH) * pThis->u16RxBSize;
    60056003    else if (RDH > RDT)
    6006         cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
     6004        cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
    60076005    else
    60086006    {
    … …  
    60116009    }
    60126010    E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
    6013              pState->szPrf, RDH, RDT, RDLEN, pState->u16RxBSize, cb));
    6014 
    6015     e1kCsRxLeave(pState);
     6011             pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
     6012
     6013    e1kCsRxLeave(pThis);
    60166014    return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
    60176015#else /* E1K_WITH_RXD_CACHE */
    60186016    int rc = VINF_SUCCESS;
    60196017
    6020     if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
     6018    if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
    60216019        return VERR_NET_NO_BUFFER_SPACE;
    60226020
    … …  
    60246022    {
    60256023        E1KRXDESC desc;
    6026         PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
     6024        PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
    60276025                          &desc, sizeof(desc));
    60286026        if (desc.status.fDD)
    60296027            rc = VERR_NET_NO_BUFFER_SPACE;
    60306028    }
    6031     else if (e1kRxDIsCacheEmpty(pState) && RDH == RDT)
     6029    else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
    60326030    {
    60336031        /* Cache is empty, so is the RX ring. */
    … …  
    60356033    }
    60366034    E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
    6037              " u16RxBSize=%d rc=%Rrc\n", pState->szPrf,
    6038              e1kRxDInCache(pState), RDH, RDT, RDLEN, pState->u16RxBSize, rc));
    6039 
    6040     e1kCsRxLeave(pState);
     6035             " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
     6036             e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
     6037
     6038    e1kCsRxLeave(pThis);
    60416039    return rc;
    60426040#endif /* E1K_WITH_RXD_CACHE */
    … …  
    60486046static DECLCALLBACK(int) e1kNetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
    60496047{
    6050     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
    6051     int rc = e1kCanReceive(pState);
     6048    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
     6049    int rc = e1kCanReceive(pThis);
    60526050
    60536051    if (RT_SUCCESS(rc))
    … …  
    60576055
    60586056    rc = VERR_INTERRUPTED;
    6059     ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
    6060     STAM_PROFILE_START(&pState->StatRxOverflow, a);
     6057    ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
     6058    STAM_PROFILE_START(&pThis->StatRxOverflow, a);
    60616059    VMSTATE enmVMState;
    6062     while (RT_LIKELY(   (enmVMState = PDMDevHlpVMState(pState->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
     6060    while (RT_LIKELY(   (enmVMState = PDMDevHlpVMState(pThis->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
    60636061                     ||  enmVMState == VMSTATE_RUNNING_LS))
    60646062    {
    6065         int rc2 = e1kCanReceive(pState);
     6063        int rc2 = e1kCanReceive(pThis);
    60666064        if (RT_SUCCESS(rc2))
    60676065        {
    … …  
    60706068        }
    60716069        E1kLogRel(("E1000 e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
    6072         E1kLog(("%s e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pState->szPrf, cMillies));
    6073         RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
    6074     }
    6075     STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
    6076     ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
     6070        E1kLog(("%s e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
     6071        RTSemEventWait(pThis->hEventMoreRxDescAvail, cMillies);
     6072    }
     6073    STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
     6074    ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
    60776075
    60786076    return rc;
    … …  
    60856083 *
    60866084 * @returns true if address matches.
    6087  * @param   pState          Pointer to the state structure.
     6085 * @param   pThis          Pointer to the state structure.
    60886086 * @param   pvBuf           The ethernet packet.
    60896087 * @param   cb              Number of bytes available in the packet.
    60906088 * @thread  EMT
    60916089 */
    6092 static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
    6093 {
    6094     for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
    6095     {
    6096         E1KRAELEM* ra = pState->aRecAddr.array + i;
     6090static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
     6091{
     6092    for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
     6093    {
     6094        E1KRAELEM* ra = pThis->aRecAddr.array + i;
    60976095
    60986096        /* Valid address? */
    … …  
    61026100            //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
    61036101            //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
    6104             //         pState->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
     6102            //         pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
    61056103            //         ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
    61066104            /*
    … …  
    61296127 *
    61306128 * @returns true if address matches.
    6131  * @param   pState          Pointer to the state structure.
     6129 * @param   pThis          Pointer to the state structure.
    61326130 * @param   pvBuf           The ethernet packet.
    61336131 * @param   cb              Number of bytes available in the packet.
    61346132 * @thread  EMT
    61356133 */
    6136 static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
     6134static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
    61376135{
    61386136    /* Get bits 32..47 of destination address */
    … …  
    61496147    if (offset < 3)
    61506148        u16Bit = u16Bit >> (4 - offset);
    6151     return ASMBitTest(pState->auMTA, u16Bit & 0xFFF);
     6149    return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
    61526150}
    61536151
    … …  
    61626160 *
    61636161 * @returns true if packet is intended for this node.
    6164  * @param   pState          Pointer to the state structure.
     6162 * @param   pThis          Pointer to the state structure.
    61656163 * @param   pvBuf           The ethernet packet.
    61666164 * @param   cb              Number of bytes available in the packet.
    … …  
    61686166 * @thread  EMT
    61696167 */
    6170 static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
     6168static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
    61716169{
    61726170    Assert(cb > 14);
    … …  
    61786176    {
    61796177        E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
    6180                 pState->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
     6178                pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
    61816179        E1K_INC_CNT32(ROC);
    61826180        return false;
    … …  
    61866184        /* When long packet reception is disabled packets over 1522 are discarded */
    61876185        E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
    6188                 pState->szPrf, cb));
     6186                pThis->szPrf, cb));
    61896187        E1K_INC_CNT32(ROC);
    61906188        return false;
    … …  
    62026200            if (RCTL & RCTL_CFIEN)
    62036201            {
    6204                 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pState->szPrf,
     6202                E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
    62056203                         E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
    62066204                         E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
    … …  
    62096207                {
    62106208                    E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
    6211                              pState->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
     6209                             pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
    62126210                    return false;
    62136211                }
    62146212            }
    62156213            else
    6216                 E1kLog3(("%s VLAN filter: VLAN=%d\n", pState->szPrf,
     6214                E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
    62176215                         E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
    6218             if (!ASMBitTest(pState->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
     6216            if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
    62196217            {
    62206218                E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
    6221                          pState->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
     6219                         pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
    62226220                return false;
    62236221            }
    … …  
    62276225    if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
    62286226        return true;
    6229     E1kLog2(("%s Packet filter: not a broadcast\n", pState->szPrf));
     6227    E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
    62306228    if (e1kIsMulticast(pvBuf))
    62316229    {
    … …  
    62336231        if (RCTL & RCTL_MPE)
    62346232            return true;
    6235         E1kLog2(("%s Packet filter: no promiscuous multicast\n", pState->szPrf));
     6233        E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
    62366234        /* Try perfect matches first */
    6237         if (e1kPerfectMatch(pState, pvBuf))
     6235        if (e1kPerfectMatch(pThis, pvBuf))
    62386236        {
    62396237            pStatus->fPIF = true;
    62406238            return true;
    62416239        }
    6242         E1kLog2(("%s Packet filter: no perfect match\n", pState->szPrf));
    6243         if (e1kImperfectMatch(pState, pvBuf))
     6240        E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
     6241        if (e1kImperfectMatch(pThis, pvBuf))
    62446242            return true;
    6245         E1kLog2(("%s Packet filter: no imperfect match\n", pState->szPrf));
     6243        E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
    62466244    }
    62476245    else {
    … …  
    62496247        if (RCTL & RCTL_UPE)
    62506248            return true;
    6251         E1kLog2(("%s Packet filter: no promiscuous unicast\n", pState->szPrf));
    6252         if (e1kPerfectMatch(pState, pvBuf))
     6249        E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
     6250        if (e1kPerfectMatch(pThis, pvBuf))
    62536251        {
    62546252            pStatus->fPIF = true;
    62556253            return true;
    62566254        }
    6257         E1kLog2(("%s Packet filter: no perfect match\n", pState->szPrf));
    6258     }
    6259     E1kLog2(("%s Packet filter: packet discarded\n", pState->szPrf));
     6255        E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
     6256    }
     6257    E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
    62606258    return false;
    62616259}
    … …  
    62666264static DECLCALLBACK(int) e1kNetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
    62676265{
    6268     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
     6266    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
    62696267    int       rc = VINF_SUCCESS;
    62706268
    … …  
    62726270     * Drop packets if the VM is not running yet/anymore.
    62736271     */
    6274     VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pState));
     6272    VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pThis));
    62756273    if (    enmVMState != VMSTATE_RUNNING
    62766274        &&  enmVMState != VMSTATE_RUNNING_LS)
    62776275    {
    6278         E1kLog(("%s Dropping incoming packet as VM is not running.\n", pState->szPrf));
     6276        E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
    62796277        return VINF_SUCCESS;
    62806278    }
    62816279
    62826280    /* Discard incoming packets in locked state */
    6283     if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
    6284     {
    6285         E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pState->szPrf));
     6281    if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
     6282    {
     6283        E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
    62866284        return VINF_SUCCESS;
    62876285    }
    62886286
    6289     STAM_PROFILE_ADV_START(&pState->StatReceive, a);
    6290 
    6291     //if (!e1kCsEnter(pState, RT_SRC_POS))
     6287    STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
     6288
     6289    //if (!e1kCsEnter(pThis, RT_SRC_POS))
    62926290    //    return VERR_PERMISSION_DENIED;
    62936291
    6294     e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
     6292    e1kPacketDump(pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
    62956293
    62966294    /* Update stats */
    6297     if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
     6295    if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
    62986296    {
    62996297        E1K_INC_CNT32(TPR);
    63006298        E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
    6301         e1kCsLeave(pState);
    6302     }
    6303     STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
     6299        e1kCsLeave(pThis);
     6300    }
     6301    STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
    63046302    E1KRXDST status;
    63056303    RT_ZERO(status);
    6306     bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
    6307     STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
     6304    bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
     6305    STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
    63086306    if (fPassed)
    63096307    {
    6310         rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
    6311     }
    6312     //e1kCsLeave(pState);
    6313     STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
     6308        rc = e1kHandleRxPacket(pThis, pvBuf, cb, status);
     6309    }
     6310    //e1kCsLeave(pThis);
     6311    STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
    63146312
    63156313    return rc;
    … …  
    63246322static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
    63256323{
    6326     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
     6324    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
    63276325    int       rc     = VERR_PDM_LUN_NOT_FOUND;
    63286326
    63296327    if (iLUN == 0)
    63306328    {
    6331         *ppLed = &pState->led;
     6329        *ppLed = &pThis->led;
    63326330        rc     = VINF_SUCCESS;
    63336331    }
    … …  
    63436341static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
    63446342{
    6345     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
    6346     pState->eeprom.getMac(pMac);
     6343    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
     6344    pThis->eeprom.getMac(pMac);
    63476345    return VINF_SUCCESS;
    63486346}
    … …  
    63536351static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
    63546352{
    6355     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
     6353    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
    63566354    if (STATUS & STATUS_LU)
    63576355        return PDMNETWORKLINKSTATE_UP;
    … …  
    63646362static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
    63656363{
    6366     E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
     6364    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
    63676365    bool fOldUp = !!(STATUS & STATUS_LU);
    63686366    bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
    63696367
    63706368    if (   fNewUp != fOldUp
    6371         || (!fNewUp && pState->fCableConnected)) /* old state was connected but STATUS not
     6369        || (!fNewUp && pThis->fCableConnected)) /* old state was connected but STATUS not
    63726370                                                  * yet written by guest */
    63736371    {
    … …  
    63756373        {
    63766374            E1kLog(("%s Link will be up in approximately %d secs\n",
    6377                     pState->szPrf, pState->cMsLinkUpDelay / 1000));
    6378             pState->fCableConnected = true;
     6375                    pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
     6376            pThis->fCableConnected = true;
    63796377            STATUS &= ~STATUS_LU;
    6380             Phy::setLinkStatus(&pState->phy, false);
    6381             e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
     6378            Phy::setLinkStatus(&pThis->phy, false);
     6379            e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
    63826380            /* Restore the link back in 5 seconds (by default). */
    6383             e1kBringLinkUpDelayed(pState);
     6381            e1kBringLinkUpDelayed(pThis);
    63846382        }
    63856383        else
    63866384        {
    6387             E1kLog(("%s Link is down\n", pState->szPrf));
    6388             pState->fCableConnected = false;
     6385            E1kLog(("%s Link is down\n", pThis->szPrf));
     6386            pThis->fCableConnected = false;
    63896387            STATUS &= ~STATUS_LU;
    6390             Phy::setLinkStatus(&pState->phy, false);
    6391             e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
     6388            Phy::setLinkStatus(&pThis->phy, false);
     6389            e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
    63926390        }
    6393         if (pState->pDrvR3)
    6394             pState->pDrvR3->pfnNotifyLinkChanged(pState->pDrvR3, enmState);
     6391        if (pThis->pDrvR3)
     6392            pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, enmState);
    63956393    }
    63966394    return VINF_SUCCESS;
    … …  
    64056403static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
    64066404{
    6407     E1KSTATE *pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
     6405    PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
    64086406    Assert(&pThis->IBase == pInterface);
    64096407
    … …  
    64216419 * Saves the configuration.
    64226420 *
    6423  * @param   pState      The E1K state.
     6421 * @param   pThis      The E1K state.
    64246422 * @param   pSSM        The handle to the saved state.
    64256423 */
    6426 static void e1kSaveConfig(E1KSTATE *pState, PSSMHANDLE pSSM)
    6427 {
    6428     SSMR3PutMem(pSSM, &pState->macConfigured, sizeof(pState->macConfigured));
    6429     SSMR3PutU32(pSSM, pState->eChip);
     6424static void e1kSaveConfig(PE1KSTATE pThis, PSSMHANDLE pSSM)
     6425{
     6426    SSMR3PutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
     6427    SSMR3PutU32(pSSM, pThis->eChip);
    64306428}
    64316429
    … …  
    64356433static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
    64366434{
    6437     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    6438     e1kSaveConfig(pState, pSSM);
     6435    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6436    e1kSaveConfig(pThis, pSSM);
    64396437    return VINF_SSM_DONT_CALL_AGAIN;
    64406438}
    … …  
    64456443static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    64466444{
    6447     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    6448 
    6449     int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
     6445    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6446
     6447    int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
    64506448    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    64516449        return rc;
    6452     e1kCsLeave(pState);
     6450    e1kCsLeave(pThis);
    64536451    return VINF_SUCCESS;
    64546452#if 0
    64556453    /* 1) Prevent all threads from modifying the state and memory */
    6456     //pState->fLocked = true;
     6454    //pThis->fLocked = true;
    64576455    /* 2) Cancel all timers */
    64586456#ifdef E1K_TX_DELAY
    6459     e1kCancelTimer(pState, pState->CTX_SUFF(pTXDTimer));
     6457    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
    64606458#endif /* E1K_TX_DELAY */
    64616459#ifdef E1K_USE_TX_TIMERS
    6462     e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
     6460    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
    64636461#ifndef E1K_NO_TAD
    6464     e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
     6462    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
    64656463#endif /* E1K_NO_TAD */
    64666464#endif /* E1K_USE_TX_TIMERS */
    64676465#ifdef E1K_USE_RX_TIMERS
    6468     e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
    6469     e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
     6466    e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
     6467    e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
    64706468#endif /* E1K_USE_RX_TIMERS */
    6471     e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
     6469    e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
    64726470    /* 3) Did I forget anything? */
    6473     E1kLog(("%s Locked\n", pState->szPrf));
     6471    E1kLog(("%s Locked\n", pThis->szPrf));
    64746472    return VINF_SUCCESS;
    64756473#endif
    … …  
    64816479static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    64826480{
    6483     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    6484 
    6485     e1kSaveConfig(pState, pSSM);
    6486     pState->eeprom.save(pSSM);
    6487     e1kDumpState(pState);
    6488     SSMR3PutMem(pSSM, pState->auRegs, sizeof(pState->auRegs));
    6489     SSMR3PutBool(pSSM, pState->fIntRaised);
    6490     Phy::saveState(pSSM, &pState->phy);
    6491     SSMR3PutU32(pSSM, pState->uSelectedReg);
    6492     SSMR3PutMem(pSSM, pState->auMTA, sizeof(pState->auMTA));
    6493     SSMR3PutMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
    6494     SSMR3PutMem(pSSM, pState->auVFTA, sizeof(pState->auVFTA));
    6495     SSMR3PutU64(pSSM, pState->u64AckedAt);
    6496     SSMR3PutU16(pSSM, pState->u16RxBSize);
    6497     //SSMR3PutBool(pSSM, pState->fDelayInts);
    6498     //SSMR3PutBool(pSSM, pState->fIntMaskUsed);
    6499     SSMR3PutU16(pSSM, pState->u16TxPktLen);
     6481    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6482
     6483    e1kSaveConfig(pThis, pSSM);
     6484    pThis->eeprom.save(pSSM);
     6485    e1kDumpState(pThis);
     6486    SSMR3PutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
     6487    SSMR3PutBool(pSSM, pThis->fIntRaised);
     6488    Phy::saveState(pSSM, &pThis->phy);
     6489    SSMR3PutU32(pSSM, pThis->uSelectedReg);
     6490    SSMR3PutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
     6491    SSMR3PutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
     6492    SSMR3PutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
     6493    SSMR3PutU64(pSSM, pThis->u64AckedAt);
     6494    SSMR3PutU16(pSSM, pThis->u16RxBSize);
     6495    //SSMR3PutBool(pSSM, pThis->fDelayInts);
     6496    //SSMR3PutBool(pSSM, pThis->fIntMaskUsed);
     6497    SSMR3PutU16(pSSM, pThis->u16TxPktLen);
    65006498/** @todo State wrt to the TSE buffer is incomplete, so little point in
    65016499 *        saving this actually. */
    6502     SSMR3PutMem(pSSM, pState->aTxPacketFallback, pState->u16TxPktLen);
    6503     SSMR3PutBool(pSSM, pState->fIPcsum);
    6504     SSMR3PutBool(pSSM, pState->fTCPcsum);
    6505     SSMR3PutMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
    6506     SSMR3PutMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
    6507     SSMR3PutBool(pSSM, pState->fVTag);
    6508     SSMR3PutU16(pSSM, pState->u16VTagTCI);
     6500    SSMR3PutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
     6501    SSMR3PutBool(pSSM, pThis->fIPcsum);
     6502    SSMR3PutBool(pSSM, pThis->fTCPcsum);
     6503    SSMR3PutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
     6504    SSMR3PutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
     6505    SSMR3PutBool(pSSM, pThis->fVTag);
     6506    SSMR3PutU16(pSSM, pThis->u16VTagTCI);
    65096507#ifdef E1K_WITH_TXD_CACHE
    65106508#if 0
    6511     SSMR3PutU8(pSSM, pState->nTxDFetched);
    6512     SSMR3PutMem(pSSM, pState->aTxDescriptors,
    6513                 pState->nTxDFetched * sizeof(pState->aTxDescriptors[0]));
     6509    SSMR3PutU8(pSSM, pThis->nTxDFetched);
     6510    SSMR3PutMem(pSSM, pThis->aTxDescriptors,
     6511                pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
    65146512#else
    65156513    /*
    … …  
    65226520#endif /* E1K_WITH_TXD_CACHE */
    65236521/**@todo GSO requires some more state here. */
    6524     E1kLog(("%s State has been saved\n", pState->szPrf));
     6522    E1kLog(("%s State has been saved\n", pThis->szPrf));
    65256523    return VINF_SUCCESS;
    65266524}
    … …  
    65326530static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    65336531{
    6534     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6532    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    65356533
    65366534    /* If VM is being powered off unlocking will result in assertions in PGM */
    65376535    if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
    6538         pState->fLocked = false;
     6536        pThis->fLocked = false;
    65396537    else
    6540         E1kLog(("%s VM is not running -- remain locked\n", pState->szPrf));
    6541     E1kLog(("%s Unlocked\n", pState->szPrf));
     6538        E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
     6539    E1kLog(("%s Unlocked\n", pThis->szPrf));
    65426540    return VINF_SUCCESS;
    65436541}
    … …  
    65496547static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    65506548{
    6551     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    6552 
    6553     int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
     6549    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6550
     6551    int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
    65546552    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    65556553        return rc;
    6556     e1kCsLeave(pState);
     6554    e1kCsLeave(pThis);
    65576555    return VINF_SUCCESS;
    65586556}
    … …  
    65636561static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
    65646562{
    6565     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6563    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    65666564    int       rc;
    65676565
    … …  
    65816579        rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
    65826580        AssertRCReturn(rc, rc);
    6583         if (   memcmp(&macConfigured, &pState->macConfigured, sizeof(macConfigured))
     6581        if (   memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
    65846582            && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
    6585             LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pState->szPrf, &pState->macConfigured, &macConfigured));
     6583            LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
    65866584
    65876585        E1KCHIP eChip;
    65886586        rc = SSMR3GetU32(pSSM, &eChip);
    65896587        AssertRCReturn(rc, rc);
    6590         if (eChip != pState->eChip)
    6591             return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pState->eChip, eChip);
     6588        if (eChip != pThis->eChip)
     6589            return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
    65926590    }
    65936591
    … …  
    65966594        if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
    65976595        {
    6598             rc = pState->eeprom.load(pSSM);
     6596            rc = pThis->eeprom.load(pSSM);
    65996597            AssertRCReturn(rc, rc);
    66006598        }
    66016599        /* the state */
    6602         SSMR3GetMem(pSSM, &pState->auRegs, sizeof(pState->auRegs));
    6603         SSMR3GetBool(pSSM, &pState->fIntRaised);
     6600        SSMR3GetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
     6601        SSMR3GetBool(pSSM, &pThis->fIntRaised);
    66046602        /** @todo: PHY could be made a separate device with its own versioning */
    6605         Phy::loadState(pSSM, &pState->phy);
    6606         SSMR3GetU32(pSSM, &pState->uSelectedReg);
    6607         SSMR3GetMem(pSSM, &pState->auMTA, sizeof(pState->auMTA));
    6608         SSMR3GetMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
    6609         SSMR3GetMem(pSSM, &pState->auVFTA, sizeof(pState->auVFTA));
    6610         SSMR3GetU64(pSSM, &pState->u64AckedAt);
    6611         SSMR3GetU16(pSSM, &pState->u16RxBSize);
    6612         //SSMR3GetBool(pSSM, pState->fDelayInts);
    6613         //SSMR3GetBool(pSSM, pState->fIntMaskUsed);
    6614         SSMR3GetU16(pSSM, &pState->u16TxPktLen);
    6615         SSMR3GetMem(pSSM, &pState->aTxPacketFallback[0], pState->u16TxPktLen);
    6616         SSMR3GetBool(pSSM, &pState->fIPcsum);
    6617         SSMR3GetBool(pSSM, &pState->fTCPcsum);
    6618         SSMR3GetMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
    6619         rc = SSMR3GetMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
     6603        Phy::loadState(pSSM, &pThis->phy);
     6604        SSMR3GetU32(pSSM, &pThis->uSelectedReg);
     6605        SSMR3GetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
     6606        SSMR3GetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
     6607        SSMR3GetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
     6608        SSMR3GetU64(pSSM, &pThis->u64AckedAt);
     6609        SSMR3GetU16(pSSM, &pThis->u16RxBSize);
     6610        //SSMR3GetBool(pSSM, pThis->fDelayInts);
     6611        //SSMR3GetBool(pSSM, pThis->fIntMaskUsed);
     6612        SSMR3GetU16(pSSM, &pThis->u16TxPktLen);
     6613        SSMR3GetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
     6614        SSMR3GetBool(pSSM, &pThis->fIPcsum);
     6615        SSMR3GetBool(pSSM, &pThis->fTCPcsum);
     6616        SSMR3GetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
     6617        rc = SSMR3GetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
    66206618        AssertRCReturn(rc, rc);
    66216619        if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
    66226620        {
    6623             SSMR3GetBool(pSSM, &pState->fVTag);
    6624             rc = SSMR3GetU16(pSSM, &pState->u16VTagTCI);
     6621            SSMR3GetBool(pSSM, &pThis->fVTag);
     6622            rc = SSMR3GetU16(pSSM, &pThis->u16VTagTCI);
    66256623            AssertRCReturn(rc, rc);
    66266624        }
    66276625        else
    66286626        {
    6629             pState->fVTag      = false;
    6630             pState->u16VTagTCI = 0;
     6627            pThis->fVTag      = false;
     6628            pThis->u16VTagTCI = 0;
    66316629        }
    66326630#ifdef E1K_WITH_TXD_CACHE
    66336631        if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
    66346632        {
    6635             rc = SSMR3GetU8(pSSM, &pState->nTxDFetched);
     6633            rc = SSMR3GetU8(pSSM, &pThis->nTxDFetched);
    66366634            AssertRCReturn(rc, rc);
    6637             if (pState->nTxDFetched)
    6638                 SSMR3GetMem(pSSM, pState->aTxDescriptors,
    6639                             pState->nTxDFetched * sizeof(pState->aTxDescriptors[0]));
     6635            if (pThis->nTxDFetched)
     6636                SSMR3GetMem(pSSM, pThis->aTxDescriptors,
     6637                            pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
    66406638        }
    66416639        else
    6642             pState->nTxDFetched = 0;
     6640            pThis->nTxDFetched = 0;
    66436641        /*
    66446642         * @todo: Perhaps we should not store TXD cache as the entries can be
    … …  
    66516649         * state, we just need to make sure it is empty.
    66526650         */
    6653         pState->iRxDCurrent = pState->nRxDFetched = 0;
     6651        pThis->iRxDCurrent = pThis->nRxDFetched = 0;
    66546652#endif /* E1K_WITH_RXD_CACHE */
    66556653        /* derived state  */
    6656         e1kSetupGsoCtx(&pState->GsoCtx, &pState->contextTSE);
    6657 
    6658         E1kLog(("%s State has been restored\n", pState->szPrf));
    6659         e1kDumpState(pState);
     6654        e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
     6655
     6656        E1kLog(("%s State has been restored\n", pThis->szPrf));
     6657        e1kDumpState(pThis);
    66606658    }
    66616659    return VINF_SUCCESS;
    … …  
    66676665static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
    66686666{
    6669     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6667    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    66706668
    66716669    /* Update promiscuous mode */
    6672     if (pState->pDrvR3)
    6673         pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3,
     6670    if (pThis->pDrvR3)
     6671        pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3,
    66746672                                             !!(RCTL & (RCTL_UPE | RCTL_MPE)));
    66756673
    … …  
    66816679    if (    (STATUS & STATUS_LU)
    66826680        && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
    6683         && pState->cMsLinkUpDelay)
    6684     {
    6685         E1kLog(("%s Link is down temporarily\n", pState->szPrf));
     6681        && pThis->cMsLinkUpDelay)
     6682    {
     6683        E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
    66866684        STATUS &= ~STATUS_LU;
    6687         Phy::setLinkStatus(&pState->phy, false);
    6688         e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
     6685        Phy::setLinkStatus(&pThis->phy, false);
     6686        e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
    66896687        /* Restore the link back in five seconds (default). */
    6690         e1kBringLinkUpDelayed(pState);
     6688        e1kBringLinkUpDelayed(pThis);
    66916689    }
    66926690    return VINF_SUCCESS;
    … …  
    68466844static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
    68476845{
    6848     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     6846    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    68496847    unsigned  i;
    68506848    // bool        fRcvRing = false;
    … …  
    68646862     */
    68656863    pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%RTiop mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
    6866                     pDevIns->iInstance, pState->addrIOPort, pState->addrMMReg,
    6867                     &pState->macConfigured, g_Chips[pState->eChip].pcszName,
    6868                     pState->fGCEnabled ? " GC" : "", pState->fR0Enabled ? " R0" : "");
    6869 
    6870     e1kCsEnter(pState, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
     6864                    pDevIns->iInstance, pThis->addrIOPort, pThis->addrMMReg,
     6865                    &pThis->macConfigured, g_Chips[pThis->eChip].pcszName,
     6866                    pThis->fGCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
     6867
     6868    e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
    68716869
    68726870    for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
    6873         pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", s_e1kRegMap[i].abbrev, pState->auRegs[i]);
    6874 
    6875     for (i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
    6876     {
    6877         E1KRAELEM* ra = pState->aRecAddr.array + i;
     6871        pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", s_e1kRegMap[i].abbrev, pThis->auRegs[i]);
     6872
     6873    for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
     6874    {
     6875        E1KRAELEM* ra = pThis->aRecAddr.array + i;
    68786876        if (ra->ctl & RA_CTL_AV)
    68796877        {
    … …  
    69016899    }
    69026900    pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
    6903                     pState->iRxDCurrent, RDH, pState->nRxDFetched, E1K_RXD_CACHE_SIZE);
    6904     if (rdh > pState->iRxDCurrent)
    6905         rdh -= pState->iRxDCurrent;
     6901                    pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
     6902    if (rdh > pThis->iRxDCurrent)
     6903        rdh -= pThis->iRxDCurrent;
    69066904    else
    6907         rdh = cDescs + rdh - pState->iRxDCurrent;
    6908     for (i = 0; i < pState->nRxDFetched; ++i)
    6909     {
    6910         if (i == pState->iRxDCurrent)
     6905        rdh = cDescs + rdh - pThis->iRxDCurrent;
     6906    for (i = 0; i < pThis->nRxDFetched; ++i)
     6907    {
     6908        if (i == pThis->iRxDCurrent)
    69116909            pHlp->pfnPrintf(pHlp, ">>> ");
    69126910        pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
    69136911                        e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
    6914                         &pState->aRxDescriptors[i]);
     6912                        &pThis->aRxDescriptors[i]);
    69156913    }
    69166914
    … …  
    69286926    }
    69296927    pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
    6930                     pState->iTxDCurrent, TDH, pState->nTxDFetched, E1K_TXD_CACHE_SIZE);
    6931     if (tdh > pState->iTxDCurrent)
    6932         tdh -= pState->iTxDCurrent;
     6928                    pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
     6929    if (tdh > pThis->iTxDCurrent)
     6930        tdh -= pThis->iTxDCurrent;
    69336931    else
    6934         tdh = cDescs + tdh - pState->iTxDCurrent;
    6935     for (i = 0; i < pState->nTxDFetched; ++i)
    6936     {
    6937         if (i == pState->iTxDCurrent)
     6932        tdh = cDescs + tdh - pThis->iTxDCurrent;
     6933    for (i = 0; i < pThis->nTxDFetched; ++i)
     6934    {
     6935        if (i == pThis->iTxDCurrent)
    69386936            pHlp->pfnPrintf(pHlp, ">>> ");
    69396937        pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
    69406938                        e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
    6941                         &pState->aTxDescriptors[i]);
     6939                        &pThis->aTxDescriptors[i]);
    69426940    }
    69436941
    69446942
    69456943#ifdef E1K_INT_STATS
    6946     pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pState->uStatIntTry);
    6947     pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pState->uStatInt);
    6948     pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pState->uStatIntLower);
    6949     pHlp->pfnPrintf(pHlp, "Interrupts delayed: %d\n", pState->uStatIntDly);
    6950     pHlp->pfnPrintf(pHlp, "Disabled delayed:   %d\n", pState->uStatDisDly);
    6951     pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pState->uStatIntSkip);
    6952     pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pState->uStatIntMasked);
    6953     pHlp->pfnPrintf(pHlp, "Early interrupts  : %d\n", pState->uStatIntEarly);
    6954     pHlp->pfnPrintf(pHlp, "Late interrupts   : %d\n", pState->uStatIntLate);
    6955     pHlp->pfnPrintf(pHlp, "Lost interrupts   : %d\n", pState->iStatIntLost);
    6956     pHlp->pfnPrintf(pHlp, "Interrupts by RX  : %d\n", pState->uStatIntRx);
    6957     pHlp->pfnPrintf(pHlp, "Interrupts by TX  : %d\n", pState->uStatIntTx);
    6958     pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pState->uStatIntICS);
    6959     pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pState->uStatIntRDTR);
    6960     pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pState->uStatIntRXDMT0);
    6961     pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pState->uStatIntTXQE);
    6962     pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pState->uStatTxIDE);
    6963     pHlp->pfnPrintf(pHlp, "TX delayed:         %d\n", pState->uStatTxDelayed);
    6964     pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pState->uStatTxDelayExp);
    6965     pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pState->uStatTxNoRS);
    6966     pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pState->uStatTAD);
    6967     pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pState->uStatTID);
    6968     pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pState->uStatRAD);
    6969     pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pState->uStatRID);
    6970     pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pState->uStatDescCtx);
    6971     pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pState->uStatDescDat);
    6972     pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pState->uStatDescLeg);
    6973     pHlp->pfnPrintf(pHlp, "Received frames   : %d\n", pState->uStatRxFrm);
    6974     pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pState->uStatTxFrm);
    6975     pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pState->uStatTx1514);
    6976     pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pState->uStatTx2962);
    6977     pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pState->uStatTx4410);
    6978     pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pState->uStatTx5858);
    6979     pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pState->uStatTx7306);
    6980     pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pState->uStatTx8754);
    6981     pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pState->uStatTx16384);
    6982     pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pState->uStatTx32768);
    6983     pHlp->pfnPrintf(pHlp, "Larger TX frames    : %d\n", pState->uStatTxLarge);
     6944    pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
     6945    pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
     6946    pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
     6947    pHlp->pfnPrintf(pHlp, "Interrupts delayed: %d\n", pThis->uStatIntDly);
     6948    pHlp->pfnPrintf(pHlp, "Disabled delayed:   %d\n", pThis->uStatDisDly);
     6949    pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
     6950    pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
     6951    pHlp->pfnPrintf(pHlp, "Early interrupts  : %d\n", pThis->uStatIntEarly);
     6952    pHlp->pfnPrintf(pHlp, "Late interrupts   : %d\n", pThis->uStatIntLate);
     6953    pHlp->pfnPrintf(pHlp, "Lost interrupts   : %d\n", pThis->iStatIntLost);
     6954    pHlp->pfnPrintf(pHlp, "Interrupts by RX  : %d\n", pThis->uStatIntRx);
     6955    pHlp->pfnPrintf(pHlp, "Interrupts by TX  : %d\n", pThis->uStatIntTx);
     6956    pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
     6957    pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
     6958    pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
     6959    pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
     6960    pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
     6961    pHlp->pfnPrintf(pHlp, "TX delayed:         %d\n", pThis->uStatTxDelayed);
     6962    pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
     6963    pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
     6964    pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
     6965    pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
     6966    pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
     6967    pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
     6968    pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
     6969    pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
     6970    pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
     6971    pHlp->pfnPrintf(pHlp, "Received frames   : %d\n", pThis->uStatRxFrm);
     6972    pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
     6973    pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
     6974    pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
     6975    pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
     6976    pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
     6977    pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
     6978    pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
     6979    pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
     6980    pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
     6981    pHlp->pfnPrintf(pHlp, "Larger TX frames    : %d\n", pThis->uStatTxLarge);
    69846982#endif /* E1K_INT_STATS */
    69856983
    6986     e1kCsLeave(pState);
     6984    e1kCsLeave(pThis);
    69876985}
    69886986
    … …  
    70027000static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
    70037001{
    7004     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    7005     Log(("%s e1kR3Detach:\n", pState->szPrf));
     7002    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     7003    Log(("%s e1kR3Detach:\n", pThis->szPrf));
    70067004
    70077005    AssertLogRelReturnVoid(iLUN == 0);
    70087006
    7009     PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
     7007    PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
    70107008
    70117009    /** @todo: r=pritesh still need to check if i missed
    … …  
    70167014     * Zero some important members.
    70177015     */
    7018     pState->pDrvBase = NULL;
    7019     pState->pDrvR3 = NULL;
    7020     pState->pDrvR0 = NIL_RTR0PTR;
    7021     pState->pDrvRC = NIL_RTRCPTR;
    7022 
    7023     PDMCritSectLeave(&pState->cs);
     7016    pThis->pDrvBase = NULL;
     7017    pThis->pDrvR3 = NULL;
     7018    pThis->pDrvR0 = NIL_RTR0PTR;
     7019    pThis->pDrvRC = NIL_RTRCPTR;
     7020
     7021    PDMCritSectLeave(&pThis->cs);
    70247022}
    70257023
    … …  
    70387036static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
    70397037{
    7040     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    7041     LogFlow(("%s e1kR3Attach:\n",  pState->szPrf));
     7038    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     7039    LogFlow(("%s e1kR3Attach:\n",  pThis->szPrf));
    70427040
    70437041    AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
    70447042
    7045     PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
     7043    PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
    70467044
    70477045    /*
    70487046     * Attach the driver.
    70497047     */
    7050     int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
     7048    int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
    70517049    if (RT_SUCCESS(rc))
    70527050    {
    … …  
    70617059#endif
    70627060        }
    7063         pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
    7064         AssertMsgStmt(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
     7061        pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
     7062        AssertMsgStmt(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
    70657063                      rc = VERR_PDM_MISSING_INTERFACE_BELOW);
    70667064        if (RT_SUCCESS(rc))
    70677065        {
    7068             PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0);
    7069             pState->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
    7070 
    7071             PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC);
    7072             pState->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
     7066            PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0);
     7067            pThis->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
     7068
     7069            PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC);
     7070            pThis->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
    70737071        }
    70747072    }
    … …  
    70787076        /* This should never happen because this function is not called
    70797077         * if there is no driver to attach! */
    7080         Log(("%s No attached driver!\n", pState->szPrf));
     7078        Log(("%s No attached driver!\n", pThis->szPrf));
    70817079    }
    70827080
    … …  
    70897087    {
    70907088        STATUS &= ~STATUS_LU;
    7091         Phy::setLinkStatus(&pState->phy, false);
    7092         e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
     7089        Phy::setLinkStatus(&pThis->phy, false);
     7090        e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
    70937091        /* Restore the link back in 5 seconds (default). */
    7094         e1kBringLinkUpDelayed(pState);
    7095     }
    7096 
    7097     PDMCritSectLeave(&pState->cs);
     7092        e1kBringLinkUpDelayed(pThis);
     7093    }
     7094
     7095    PDMCritSectLeave(&pThis->cs);
    70987096    return rc;
    70997097
    … …  
    71147112static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
    71157113{
    7116     E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     7114    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    71177115#ifdef E1K_TX_DELAY
    7118     e1kCancelTimer(pState, pState->CTX_SUFF(pTXDTimer));
     7116    e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
    71197117#endif /* E1K_TX_DELAY */
    7120     e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
    7121     e1kCancelTimer(pState, pState->CTX_SUFF(pLUTimer));
    7122     e1kXmitFreeBuf(pState);
    7123     pState->u16TxPktLen  = 0;
    7124     pState->fIPcsum      = false;
    7125     pState->fTCPcsum     = false;
    7126     pState->fIntMaskUsed = false;
    7127     pState->fDelayInts   = false;
    7128     pState->fLocked      = false;
    7129     pState->u64AckedAt   = 0;
    7130     e1kHardReset(pState);
     7118    e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
     7119    e1kCancelTimer(pThis, pThis->CTX_SUFF(pLUTimer));
     7120    e1kXmitFreeBuf(pThis);
     7121    pThis->u16TxPktLen  = 0;
     7122    pThis->fIPcsum      = false;
     7123    pThis->fTCPcsum     = false;
     7124    pThis->fIntMaskUsed = false;
     7125    pThis->fDelayInts   = false;
     7126    pThis->fLocked      = false;
     7127    pThis->u64AckedAt   = 0;
     7128    e1kHardReset(pThis);
    71317129}
    71327130
    … …  
    71587156static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
    71597157{
    7160     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    7161     pState->pDevInsRC     = PDMDEVINS_2_RCPTR(pDevIns);
    7162     pState->pTxQueueRC    = PDMQueueRCPtr(pState->pTxQueueR3);
    7163     pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
     7158    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     7159    pThis->pDevInsRC     = PDMDEVINS_2_RCPTR(pDevIns);
     7160    pThis->pTxQueueRC    = PDMQueueRCPtr(pThis->pTxQueueR3);
     7161    pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
    71647162#ifdef E1K_USE_RX_TIMERS
    7165     pState->pRIDTimerRC   = TMTimerRCPtr(pState->pRIDTimerR3);
    7166     pState->pRADTimerRC   = TMTimerRCPtr(pState->pRADTimerR3);
     7163    pThis->pRIDTimerRC   = TMTimerRCPtr(pThis->pRIDTimerR3);
     7164    pThis->pRADTimerRC   = TMTimerRCPtr(pThis->pRADTimerR3);
    71677165#endif /* E1K_USE_RX_TIMERS */
    71687166#ifdef E1K_USE_TX_TIMERS
    7169     pState->pTIDTimerRC   = TMTimerRCPtr(pState->pTIDTimerR3);
     7167    pThis->pTIDTimerRC   = TMTimerRCPtr(pThis->pTIDTimerR3);
    71707168# ifndef E1K_NO_TAD
    7171     pState->pTADTimerRC   = TMTimerRCPtr(pState->pTADTimerR3);
     7169    pThis->pTADTimerRC   = TMTimerRCPtr(pThis->pTADTimerR3);
    71727170# endif /* E1K_NO_TAD */
    71737171#endif /* E1K_USE_TX_TIMERS */
    71747172#ifdef E1K_TX_DELAY
    7175     pState->pTXDTimerRC   = TMTimerRCPtr(pState->pTXDTimerR3);
     7173    pThis->pTXDTimerRC   = TMTimerRCPtr(pThis->pTXDTimerR3);
    71767174#endif /* E1K_TX_DELAY */
    7177     pState->pIntTimerRC   = TMTimerRCPtr(pState->pIntTimerR3);
    7178     pState->pLUTimerRC    = TMTimerRCPtr(pState->pLUTimerR3);
     7175    pThis->pIntTimerRC   = TMTimerRCPtr(pThis->pIntTimerR3);
     7176    pThis->pLUTimerRC    = TMTimerRCPtr(pThis->pLUTimerR3);
    71797177}
    71807178
    … …  
    71907188static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
    71917189{
    7192     E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     7190    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    71937191    PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
    71947192
    7195     e1kDumpState(pState);
    7196     E1kLog(("%s Destroying instance\n", pState->szPrf));
    7197     if (PDMCritSectIsInitialized(&pState->cs))
    7198     {
    7199         if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
    7200         {
    7201             RTSemEventSignal(pState->hEventMoreRxDescAvail);
    7202             RTSemEventDestroy(pState->hEventMoreRxDescAvail);
    7203             pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
     7193    e1kDumpState(pThis);
     7194    E1kLog(("%s Destroying instance\n", pThis->szPrf));
     7195    if (PDMCritSectIsInitialized(&pThis->cs))
     7196    {
     7197        if (pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
     7198        {
     7199            RTSemEventSignal(pThis->hEventMoreRxDescAvail);
     7200            RTSemEventDestroy(pThis->hEventMoreRxDescAvail);
     7201            pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
    72047202        }
    72057203#ifdef E1K_WITH_TX_CS
    7206         PDMR3CritSectDelete(&pState->csTx);
     7204        PDMR3CritSectDelete(&pThis->csTx);
    72077205#endif /* E1K_WITH_TX_CS */
    7208         PDMR3CritSectDelete(&pState->csRx);
    7209         PDMR3CritSectDelete(&pState->cs);
     7206        PDMR3CritSectDelete(&pThis->csRx);
     7207        PDMR3CritSectDelete(&pThis->cs);
    72107208    }
    72117209    return VINF_SUCCESS;
    … …  
    72917289static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
    72927290{
    7293     E1KSTATE *pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
     7291    PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
    72947292    int       rc;
    72957293    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);

  • trunk/src/VBox/Devices/Network/DevEEPROM.h

    r44529 r44542  
    3030 *          plain-old-data structure.
    3131 */
    32 struct EEPROM93C46 {
     32struct EEPROM93C46
     33{
    3334    /** General definitions */
    3435    enum {
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