Changeset 44626 in vbox for trunk/src/VBox/Devices/PC

Timestamp:

Feb 11, 2013 10:52:19 AM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

83713

Message:

DevAPIC.cpp,++: Changed the APIC MMIO registrations to let IOM handle the weird access work. Some cleanups elsewhere.

Location:

trunk/src/VBox/Devices/PC

Files:

• DevACPI.cpp (modified) (1 diff)
• DevAPIC.cpp (modified) (5 diffs)

trunk/src/VBox/Devices/PC/DevACPI.cpp

@@ -1720 +1720 @@
     R(PM1a_EVT_OFFSET,   1, acpiR3PM1aStsWrite,      acpiR3Pm1aStsRead,     "ACPI PM1a Status");
     R(PM1a_CTL_OFFSET,   1, acpiR3PM1aCtlWrite,      acpiR3Pm1aCtlRead,     "ACPI PM1a Control");
-    R(PM_TMR_OFFSET,     1, NULL,                  acpiPMTmrRead,       "ACPI PM Timer");
+    R(PM_TMR_OFFSET,     1, NULL,                    acpiPMTmrRead,         "ACPI PM Timer");
     R(GPE0_OFFSET + L,   L, acpiR3Gpe0EnWrite,       acpiR3Gpe0EnRead,      "ACPI GPE0 Enable");
     R(GPE0_OFFSET,       L, acpiR3Gpe0StsWrite,      acpiR3Gpe0StsRead,     "ACPI GPE0 Status");

trunk/src/VBox/Devices/PC/DevAPIC.cpp

@@ -1812 +1812 @@
     APICState *pApic = apicGetStateByCurEmt(pDev);
 
-    Log(("CPU%d: apicMMIORead at %llx\n", pApic->phys_id,  (uint64_t)GCPhysAddr));
+    Log(("CPU%d: apicMMIORead at %RGp\n", pApic->phys_id, GCPhysAddr));
+    Assert(cb == 4);
 
     /** @todo add LAPIC range validity checks (different LAPICs can
@@ -1818 +1819 @@
 
     STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIORead));
-    switch (cb)
-    {
-        case 1:
-            /** @todo this is not how recent APIC behave!  We will fix
-             *        this via the IOM. */
-            *(uint8_t *)pv = 0;
-            break;
-
-        case 2:
-            /** @todo this is not how recent APIC behave! */
-            *(uint16_t *)pv = 0;
-            break;
-
-        case 4:
-        {
 #if 0 /* Note! experimental */
 #ifndef IN_RING3
-            uint32_t index = (GCPhysAddr >> 4) & 0xff;
-
-            if (    index == 0x08 /* TPR */
-                &&  ++pApic->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
-            {
-#ifdef IN_RC
-                pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &pApic->tpr);
-#else
-                RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
-                pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
-#endif
-                return VINF_PATM_HC_MMIO_PATCH_READ;
-            }
+    uint32_t index = (GCPhysAddr >> 4) & 0xff;
+
+    if (    index == 0x08 /* TPR */
+        &&  ++pApic->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
+    {
+# ifdef IN_RC
+        pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &pApic->tpr);
+# else
+        RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
+        pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
+# endif
+        return VINF_PATM_HC_MMIO_PATCH_READ;
+    }
 #endif
 #endif /* experimental */
 
-            /* It does its own locking. */
-            uint64_t u64Value = 0;
-            int rc = apicReadRegister(pDev, pApic, (GCPhysAddr >> 4) & 0xff, &u64Value,
-                                      VINF_IOM_R3_MMIO_READ, false /*fMsr*/);
-            *(uint32_t *)pv = (uint32_t)u64Value;
-            return rc;
-        }
-
-        default:
-            AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
-            return VERR_INTERNAL_ERROR;
-    }
-    return VINF_SUCCESS;
+    /* Note! apicReadRegister does its own locking. */
+    uint64_t u64Value = 0;
+    int rc = apicReadRegister(pDev, pApic, (GCPhysAddr >> 4) & 0xff, &u64Value, VINF_IOM_R3_MMIO_READ, false /*fMsr*/);
+    *(uint32_t *)pv = (uint32_t)u64Value;
+    return rc;
 }
 
@@ -1871 +1849 @@
     APICState *pApic = apicGetStateByCurEmt(pDev);
 
-    Log(("CPU%d: apicMMIOWrite at %llx\n", pApic->phys_id, (uint64_t)GCPhysAddr));
+    Log(("CPU%d: apicMMIOWrite at %RGp\n", pApic->phys_id, GCPhysAddr));
+    Assert(cb == 4);
 
     /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
@@ -1877 +1856 @@
 
     STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIOWrite));
-    switch (cb)
-    {
-        case 1:
-        case 2:
-            /* ignore */
-            break;
-
-        case 4:
-            /* It does its own locking. */
-            return apicWriteRegister(pDev, pApic, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
-                                     VINF_IOM_R3_MMIO_WRITE, false /*fMsr*/);
-
-        default:
-            AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
-            return VERR_INTERNAL_ERROR;
-    }
-    return VINF_SUCCESS;
+    /* Note! It does its own locking. */
+    return apicWriteRegister(pDev, pApic, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
+                             VINF_IOM_R3_MMIO_WRITE, false /*fMsr*/);
 }
 
@@ -2381 +2346 @@
     uint32_t ApicBase = pDev->paLapicsR3[0].apicbase & ~0xfff;
     rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pDev,
-                               IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
+                               IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
                                apicMMIOWrite, apicMMIORead, "APIC Memory");
     if (RT_FAILURE(rc))