Changeset 44630 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Feb 11, 2013 12:31:26 PM (12 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (82 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r44528 r44630 5 5 6 6 /* 7 * Copyright (C) 2006-201 1Oracle Corporation7 * Copyright (C) 2006-2013 Oracle Corporation 8 8 * 9 9 * This file is part of VirtualBox Open Source Edition (OSE), as … … 31 31 } 32 32 33 34 /******************************************************************************* 35 * Defined Constants And Macros * 36 *******************************************************************************/ 33 37 #undef LOG_VOICES 34 38 #ifndef VBOX 35 39 //#define USE_MIXER 36 40 #else 37 # define USE_MIXER41 # define USE_MIXER 38 42 #endif 39 43 40 44 #define AC97_SSM_VERSION 1 41 45 42 enum { 46 #ifndef VBOX 47 # define SOFT_VOLUME 48 #else 49 # undef SOFT_VOLUME 50 #endif 51 #define SR_FIFOE RT_BIT(4) /* rwc, fifo error */ 52 #define SR_BCIS RT_BIT(3) /* rwc, buffer completion interrupt status */ 53 #define SR_LVBCI RT_BIT(2) /* rwc, last valid buffer completion interrupt */ 54 #define SR_CELV RT_BIT(1) /* ro, current equals last valid */ 55 #define SR_DCH RT_BIT(0) /* ro, controller halted */ 56 #define SR_VALID_MASK (RT_BIT(5) - 1) 57 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 58 #define SR_RO_MASK (SR_DCH | SR_CELV) 59 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 60 61 #define CR_IOCE RT_BIT(4) /* rw */ 62 #define CR_FEIE RT_BIT(3) /* rw */ 63 #define CR_LVBIE RT_BIT(2) /* rw */ 64 #define CR_RR RT_BIT(1) /* rw */ 65 #define CR_RPBM RT_BIT(0) /* rw */ 66 #define CR_VALID_MASK (RT_BIT(5) - 1) 67 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) 68 69 #define GC_WR 4 /* rw */ 70 #define GC_CR 2 /* rw */ 71 #define GC_VALID_MASK (RT_BIT(6) - 1) 72 73 #define GS_MD3 RT_BIT(17) /* rw */ 74 #define GS_AD3 RT_BIT(16) /* rw */ 75 #define GS_RCS RT_BIT(15) /* rwc */ 76 #define GS_B3S12 RT_BIT(14) /* ro */ 77 #define GS_B2S12 RT_BIT(13) /* ro */ 78 #define GS_B1S12 RT_BIT(12) /* ro */ 79 #define GS_S1R1 RT_BIT(11) /* rwc */ 80 #define GS_S0R1 RT_BIT(10) /* rwc */ 81 #define GS_S1CR RT_BIT(9) /* ro */ 82 #define GS_S0CR RT_BIT(8) /* ro */ 83 #define GS_MINT RT_BIT(7) /* ro */ 84 #define GS_POINT RT_BIT(6) /* ro */ 85 #define GS_PIINT RT_BIT(5) /* ro */ 86 #define GS_RSRVD (RT_BIT(4)|RT_BIT(3)) 87 #define GS_MOINT RT_BIT(2) /* ro */ 88 #define GS_MIINT RT_BIT(1) /* ro */ 89 #define GS_GSCI RT_BIT(0) /* rwc */ 90 #define GS_RO_MASK (GS_B3S12| \ 91 GS_B2S12| \ 92 GS_B1S12| \ 93 GS_S1CR| \ 94 GS_S0CR| \ 95 GS_MINT| \ 96 GS_POINT| \ 97 GS_PIINT| \ 98 GS_RSRVD| \ 99 GS_MOINT| \ 100 GS_MIINT) 101 #define GS_VALID_MASK (RT_BIT(18) - 1) 102 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI) 103 104 /** @name Buffer Descriptor 105 * @{ */ 106 #define BD_IOC RT_BIT(31) /**< Interrupt on Completion */ 107 #define BD_BUP RT_BIT(30) /**< Buffer Underrun Policy */ 108 /** @} */ 109 110 #define EACS_VRA 1 111 #define EACS_VRM 8 112 113 #define VOL_MASK 0x1f 114 #define MUTE_SHIFT 15 115 116 #define REC_MASK 7 117 enum 118 { 119 REC_MIC = 0, 120 REC_CD, 121 REC_VIDEO, 122 REC_AUX, 123 REC_LINE_IN, 124 REC_STEREO_MIX, 125 REC_MONO_MIX, 126 REC_PHONE 127 }; 128 129 enum 130 { 43 131 AC97_Reset = 0x00, 44 132 AC97_Master_Volume_Mute = 0x02, … … 75 163 }; 76 164 77 #ifndef VBOX 78 # define SOFT_VOLUME 79 #else 80 # undef SOFT_VOLUME 81 #endif 82 #define SR_FIFOE RT_BIT(4) /* rwc, fifo error */ 83 #define SR_BCIS RT_BIT(3) /* rwc, buffer completion interrupt status */ 84 #define SR_LVBCI RT_BIT(2) /* rwc, last valid buffer completion interrupt */ 85 #define SR_CELV RT_BIT(1) /* ro, current equals last valid */ 86 #define SR_DCH RT_BIT(0) /* ro, controller halted */ 87 #define SR_VALID_MASK (RT_BIT(5) - 1) 88 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 89 #define SR_RO_MASK (SR_DCH | SR_CELV) 90 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI) 91 92 #define CR_IOCE RT_BIT(4) /* rw */ 93 #define CR_FEIE RT_BIT(3) /* rw */ 94 #define CR_LVBIE RT_BIT(2) /* rw */ 95 #define CR_RR RT_BIT(1) /* rw */ 96 #define CR_RPBM RT_BIT(0) /* rw */ 97 #define CR_VALID_MASK (RT_BIT(5) - 1) 98 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE) 99 100 #define GC_WR 4 /* rw */ 101 #define GC_CR 2 /* rw */ 102 #define GC_VALID_MASK (RT_BIT(6) - 1) 103 104 #define GS_MD3 RT_BIT(17) /* rw */ 105 #define GS_AD3 RT_BIT(16) /* rw */ 106 #define GS_RCS RT_BIT(15) /* rwc */ 107 #define GS_B3S12 RT_BIT(14) /* ro */ 108 #define GS_B2S12 RT_BIT(13) /* ro */ 109 #define GS_B1S12 RT_BIT(12) /* ro */ 110 #define GS_S1R1 RT_BIT(11) /* rwc */ 111 #define GS_S0R1 RT_BIT(10) /* rwc */ 112 #define GS_S1CR RT_BIT(9) /* ro */ 113 #define GS_S0CR RT_BIT(8) /* ro */ 114 #define GS_MINT RT_BIT(7) /* ro */ 115 #define GS_POINT RT_BIT(6) /* ro */ 116 #define GS_PIINT RT_BIT(5) /* ro */ 117 #define GS_RSRVD (RT_BIT(4)|RT_BIT(3)) 118 #define GS_MOINT RT_BIT(2) /* ro */ 119 #define GS_MIINT RT_BIT(1) /* ro */ 120 #define GS_GSCI RT_BIT(0) /* rwc */ 121 #define GS_RO_MASK (GS_B3S12| \ 122 GS_B2S12| \ 123 GS_B1S12| \ 124 GS_S1CR| \ 125 GS_S0CR| \ 126 GS_MINT| \ 127 GS_POINT| \ 128 GS_PIINT| \ 129 GS_RSRVD| \ 130 GS_MOINT| \ 131 GS_MIINT) 132 #define GS_VALID_MASK (RT_BIT(18) - 1) 133 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI) 134 135 /** Buffer Descriptor */ 136 #define BD_IOC RT_BIT(31) /* Interrupt on Completion */ 137 #define BD_BUP RT_BIT(30) /* Buffer Underrun Policy */ 138 139 #define EACS_VRA 1 140 #define EACS_VRM 8 141 142 #define VOL_MASK 0x1f 143 #define MUTE_SHIFT 15 144 145 #define REC_MASK 7 146 enum 147 { 148 REC_MIC = 0, 149 REC_CD, 150 REC_VIDEO, 151 REC_AUX, 152 REC_LINE_IN, 153 REC_STEREO_MIX, 154 REC_MONO_MIX, 155 REC_PHONE 156 }; 157 165 166 /******************************************************************************* 167 * Structures and Typedefs * 168 *******************************************************************************/ 158 169 typedef struct BD 159 170 { … … 164 175 typedef struct AC97BusMasterRegs 165 176 { 166 uint32_t bdbar; /* rw 0, buffer descriptor list base address register */167 uint8_t civ; /* ro 0, current index value */168 uint8_t lvi; /* rw 0, last valid index */169 uint16_t sr; /* rw 1, status register */170 uint16_t picb; /* ro 0, position in current buffer */171 uint8_t piv; /* ro 0, prefetched index value */172 uint8_t cr; /* rw 0, control register */173 int bd_valid; /* initialized? */177 uint32_t bdbar; /**< rw 0, buffer descriptor list base address register */ 178 uint8_t civ; /**< ro 0, current index value */ 179 uint8_t lvi; /**< rw 0, last valid index */ 180 uint16_t sr; /**< rw 1, status register */ 181 uint16_t picb; /**< ro 0, position in current buffer */ 182 uint8_t piv; /**< ro 0, prefetched index value */ 183 uint8_t cr; /**< rw 0, control register */ 184 int bd_valid; /**< initialized? */ 174 185 BD bd; 175 186 } AC97BusMasterRegs; … … 189 200 uint8_t mixer_data[256]; 190 201 /** PCM in */ 191 SWVoiceIn 202 SWVoiceIn *voice_pi; 192 203 /** PCM out */ 193 SWVoiceOut 204 SWVoiceOut *voice_po; 194 205 /** Mic in */ 195 SWVoiceIn 206 SWVoiceIn *voice_mc; 196 207 uint8_t silence[128]; 197 208 int bup_flag; … … 208 219 } AC97LinkState; 209 220 210 #define ICHAC97STATE_2_DEVINS( pAC97) ((pAC97)->pDevIns)211 #define PCIDEV_2_ICHAC97STATE( pPciDev) ((PCIAC97LinkState *)(pPciDev))221 #define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevIns) 222 #define PCIDEV_2_ICHAC97STATE(a_pPciDev) ((PCIAC97LinkState *)(a_pPciDev)) 212 223 213 224 enum … … 253 264 }; 254 265 255 #define GET_BM( index) (((index) >> 4) & 3)256 257 static void po_callback 258 static void pi_callback 259 static void mc_callback 260 261 static void warm_reset 262 { 263 (void) s;264 } 265 266 static void cold_reset 267 { 268 (void) s;266 #define GET_BM(a_idx) ( ((a_idx) >> 4) & 3 ) 267 268 static void po_callback(void *opaque, int free); 269 static void pi_callback(void *opaque, int avail); 270 static void mc_callback(void *opaque, int avail); 271 272 static void warm_reset(AC97LinkState *s) 273 { 274 NOREF(s); 275 } 276 277 static void cold_reset(AC97LinkState * s) 278 { 279 NOREF(s); 269 280 } 270 281 271 282 /** Fetch Buffer Descriptor at _CIV */ 272 static void fetch_bd 283 static void fetch_bd(AC97LinkState *s, AC97BusMasterRegs *r) 273 284 { 274 285 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(s); 275 286 uint8_t b[8]; 276 287 277 PDMDevHlpPhysRead 288 PDMDevHlpPhysRead(pDevIns, r->bdbar + r->civ * 8, b, sizeof(b)); 278 289 r->bd_valid = 1; 279 290 #if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64) … … 284 295 #endif 285 296 r->picb = r->bd.ctl_len & 0xffff; 286 Log 297 Log(("ac97: bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 287 298 r->civ, r->bd.addr, r->bd.ctl_len >> 16, 288 299 r->bd.ctl_len & 0xffff, (r->bd.ctl_len & 0xffff) << 1)); … … 292 303 * Update the BM status register 293 304 */ 294 static void update_sr 305 static void update_sr(AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) 295 306 { 296 307 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(s); … … 299 310 uint32_t new_mask = new_sr & SR_INT_MASK; 300 311 uint32_t old_mask = r->sr & SR_INT_MASK; 301 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};312 static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT }; 302 313 303 314 if (new_mask ^ old_mask) … … 323 334 r->sr = new_sr; 324 335 325 Log 326 336 Log(("ac97: IOC%d LVB%d sr=%#x event=%d level=%d\n", 337 r->sr & SR_BCIS, r->sr & SR_LVBCI, r->sr, event, level)); 327 338 328 339 if (event) … … 333 344 s->glob_sta &= ~masks[r - s->bm_regs]; 334 345 335 Log 336 PDMDevHlpPCISetIrq 337 } 338 } 339 340 static void voice_set_active 346 Log(("ac97: set irq level=%d\n", !!level)); 347 PDMDevHlpPCISetIrq(pDevIns, 0, !!level); 348 } 349 } 350 351 static void voice_set_active(AC97LinkState *s, int bm_index, int on) 341 352 { 342 353 switch (bm_index) 343 354 { 344 case PI_INDEX: AUD_set_active_in (s->voice_pi, on); break; 345 case PO_INDEX: AUD_set_active_out(s->voice_po, on); break; 346 case MC_INDEX: AUD_set_active_in (s->voice_mc, on); break; 347 default: AssertFailed (); 348 break; 349 } 350 } 351 352 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r) 353 { 354 Log (("ac97: reset_bm_regs\n")); 355 case PI_INDEX: AUD_set_active_in( s->voice_pi, on); break; 356 case PO_INDEX: AUD_set_active_out(s->voice_po, on); break; 357 case MC_INDEX: AUD_set_active_in( s->voice_mc, on); break; 358 default: AssertFailed (); break; 359 } 360 } 361 362 static void reset_bm_regs(AC97LinkState *s, AC97BusMasterRegs *r) 363 { 364 Log(("ac97: reset_bm_regs\n")); 355 365 r->bdbar = 0; 356 366 r->civ = 0; 357 367 r->lvi = 0; 358 368 /** @todo do we need to do that? */ 359 update_sr 369 update_sr(s, r, SR_DCH); 360 370 r->picb = 0; 361 371 r->piv = 0; … … 363 373 r->bd_valid = 0; 364 374 365 voice_set_active (s, r - s->bm_regs, 0); 366 memset (s->silence, 0, sizeof (s->silence)); 367 } 368 369 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v) 370 { 371 if (i + 2 > sizeof (s->mixer_data)) 372 { 373 Log (("ac97: mixer_store: index %d out of bounds %d\n", 374 i, sizeof (s->mixer_data))); 375 voice_set_active(s, r - s->bm_regs, 0); 376 memset(s->silence, 0, sizeof(s->silence)); 377 } 378 379 static void mixer_store(AC97LinkState *s, uint32_t i, uint16_t v) 380 { 381 if (i + 2 > sizeof(s->mixer_data)) 382 { 383 Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof(s->mixer_data))); 375 384 return; 376 385 } … … 380 389 } 381 390 382 static uint16_t mixer_load 391 static uint16_t mixer_load(AC97LinkState *s, uint32_t i) 383 392 { 384 393 uint16_t val; 385 394 386 if (i + 2 > sizeof (s->mixer_data)) 387 { 388 Log (("ac97: mixer_store: index %d out of bounds %d\n", 389 i, sizeof (s->mixer_data))); 395 if (i + 2 > sizeof(s->mixer_data)) 396 { 397 Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof(s->mixer_data))); 390 398 val = 0xffff; 391 399 } … … 396 404 } 397 405 398 static void open_voice 406 static void open_voice(AC97LinkState *s, int index, int freq) 399 407 { 400 408 audsettings_t as; … … 410 418 { 411 419 case PI_INDEX: /* PCM in */ 412 s->voice_pi = AUD_open_in (&s->card, s->voice_pi, "ac97.pi", 413 s, pi_callback, &as); 420 s->voice_pi = AUD_open_in(&s->card, s->voice_pi, "ac97.pi", s, pi_callback, &as); 414 421 #ifdef LOG_VOICES 415 LogRel 422 LogRel(("AC97: open PI freq=%d (%s)\n", freq, s->voice_pi ? "ok" : "FAIL")); 416 423 #endif 417 424 break; 418 425 419 426 case PO_INDEX: /* PCM out */ 420 s->voice_po = AUD_open_out (&s->card, s->voice_po, "ac97.po", 421 s, po_callback, &as); 427 s->voice_po = AUD_open_out(&s->card, s->voice_po, "ac97.po", s, po_callback, &as); 422 428 #ifdef LOG_VOICES 423 LogRel 429 LogRel(("AC97: open PO freq=%d (%s)\n", freq, s->voice_po ? "ok" : "FAIL")); 424 430 #endif 425 431 break; 426 432 427 433 case MC_INDEX: /* Mic in */ 428 s->voice_mc = AUD_open_in (&s->card, s->voice_mc, "ac97.mc", 429 s, mc_callback, &as); 434 s->voice_mc = AUD_open_in(&s->card, s->voice_mc, "ac97.mc", s, mc_callback, &as); 430 435 #ifdef LOG_VOICES 431 LogRel 436 LogRel(("AC97: open MC freq=%d (%s)\n", freq, s->voice_mc ? "ok" : "FAIL")); 432 437 #endif 433 438 break; … … 439 444 { 440 445 case PI_INDEX: 441 AUD_close_in 446 AUD_close_in(&s->card, s->voice_pi); 442 447 #ifdef LOG_VOICES 443 LogRel 448 LogRel(("AC97: Closing PCM IN\n")); 444 449 #endif 445 450 s->voice_pi = NULL; … … 447 452 448 453 case PO_INDEX: 449 AUD_close_out 454 AUD_close_out(&s->card, s->voice_po); 450 455 #ifdef LOG_VOICES 451 LogRel 456 LogRel(("AC97: Closing PCM OUT\n")); 452 457 #endif 453 458 s->voice_po = NULL; … … 455 460 456 461 case MC_INDEX: 457 AUD_close_in 462 AUD_close_in(&s->card, s->voice_mc); 458 463 #ifdef LOG_VOICES 459 LogRel 464 LogRel(("AC97: Closing MIC IN\n")); 460 465 #endif 461 466 s->voice_mc = NULL; … … 465 470 } 466 471 467 static void reset_voices 472 static void reset_voices(AC97LinkState *s, uint8_t active[LAST_INDEX]) 468 473 { 469 474 uint16_t freq; 470 475 471 freq = mixer_load 472 open_voice 473 AUD_set_active_in 474 475 freq = mixer_load 476 open_voice 476 freq = mixer_load(s, AC97_PCM_LR_ADC_Rate); 477 open_voice(s, PI_INDEX, freq); 478 AUD_set_active_in(s->voice_pi, active[PI_INDEX]); 479 480 freq = mixer_load(s, AC97_PCM_Front_DAC_Rate); 481 open_voice(s, PO_INDEX, freq); 477 482 AUD_set_active_out (s->voice_po, active[PO_INDEX]); 478 483 479 freq = mixer_load 480 open_voice 481 AUD_set_active_in 484 freq = mixer_load(s, AC97_MIC_ADC_Rate); 485 open_voice(s, MC_INDEX, freq); 486 AUD_set_active_in(s->voice_mc, active[MC_INDEX]); 482 487 } 483 488 484 489 #ifdef USE_MIXER 485 490 486 static void set_volume (AC97LinkState *s, int index, 487 audmixerctl_t mt, uint32_t val) 491 static void set_volume(AC97LinkState *s, int index, audmixerctl_t mt, uint32_t val) 488 492 { 489 493 int mute = (val >> MUTE_SHIFT) & 1; … … 495 499 # ifdef SOFT_VOLUME 496 500 if (index == AC97_Master_Volume_Mute) 497 AUD_set_volume_out 501 AUD_set_volume_out(s->voice_po, mute, lvol, rvol); 498 502 else 499 AUD_set_volume 503 AUD_set_volume(mt, &mute, &lvol, &rvol); 500 504 # else 501 AUD_set_volume 505 AUD_set_volume(mt, &mute, &lvol, &rvol); 502 506 # endif 503 507 … … 518 522 val |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8); 519 523 520 mixer_store 521 } 522 523 static audrecsource_t ac97_to_aud_record_source 524 mixer_store(s, index, val); 525 } 526 527 static audrecsource_t ac97_to_aud_record_source(uint8_t i) 524 528 { 525 529 switch (i) … … 531 535 case REC_LINE_IN: return AUD_REC_LINE_IN; 532 536 case REC_PHONE: return AUD_REC_PHONE; 533 default: Log (("ac97: Unknown record source %d, using MIC\n", i)); 534 return AUD_REC_MIC; 535 } 536 } 537 538 static uint8_t aud_to_ac97_record_source (audrecsource_t rs) 537 default: 538 Log(("ac97: Unknown record source %d, using MIC\n", i)); 539 return AUD_REC_MIC; 540 } 541 } 542 543 static uint8_t aud_to_ac97_record_source(audrecsource_t rs) 539 544 { 540 545 switch (rs) … … 546 551 case AUD_REC_LINE_IN: return REC_LINE_IN; 547 552 case AUD_REC_PHONE: return REC_PHONE; 548 default: Log (("ac97: Unknown audio recording source %d using MIC\n", rs)); 549 return REC_MIC; 550 } 551 } 552 553 static void record_select (AC97LinkState *s, uint32_t val) 553 default: 554 Log(("ac97: Unknown audio recording source %d using MIC\n", rs)); 555 return REC_MIC; 556 } 557 } 558 559 static void record_select(AC97LinkState *s, uint32_t val) 554 560 { 555 561 uint8_t rs = val & REC_MASK; 556 562 uint8_t ls = (val >> 8) & REC_MASK; 557 audrecsource_t ars = ac97_to_aud_record_source 558 audrecsource_t als = ac97_to_aud_record_source 559 AUD_set_record_source 560 rs = aud_to_ac97_record_source 561 ls = aud_to_ac97_record_source 562 mixer_store 563 audrecsource_t ars = ac97_to_aud_record_source(rs); 564 audrecsource_t als = ac97_to_aud_record_source(ls); 565 AUD_set_record_source(&als, &ars); 566 rs = aud_to_ac97_record_source(ars); 567 ls = aud_to_ac97_record_source(als); 568 mixer_store(s, AC97_Record_Select, rs | (ls << 8)); 563 569 } 564 570 565 571 #endif /* USE_MIXER */ 566 572 567 static void mixer_reset 573 static void mixer_reset(AC97LinkState *s) 568 574 { 569 575 uint8_t active[LAST_INDEX]; 570 576 571 Log 572 memset (s->mixer_data, 0, sizeof(s->mixer_data));573 memset (active, 0, sizeof(active));574 mixer_store 575 mixer_store 576 mixer_store 577 578 mixer_store 579 mixer_store 580 mixer_store 581 mixer_store 582 mixer_store 583 mixer_store 584 mixer_store 585 mixer_store 577 Log(("ac97: mixer_reset\n")); 578 memset(s->mixer_data, 0, sizeof(s->mixer_data)); 579 memset(active, 0, sizeof(active)); 580 mixer_store(s, AC97_Reset , 0x0000); /* 6940 */ 581 mixer_store(s, AC97_Master_Volume_Mono_Mute , 0x8000); 582 mixer_store(s, AC97_PC_BEEP_Volume_Mute , 0x0000); 583 584 mixer_store(s, AC97_Phone_Volume_Mute , 0x8008); 585 mixer_store(s, AC97_Mic_Volume_Mute , 0x8008); 586 mixer_store(s, AC97_CD_Volume_Mute , 0x8808); 587 mixer_store(s, AC97_Aux_Volume_Mute , 0x8808); 588 mixer_store(s, AC97_Record_Gain_Mic_Mute , 0x8000); 589 mixer_store(s, AC97_General_Purpose , 0x0000); 590 mixer_store(s, AC97_3D_Control , 0x0000); 591 mixer_store(s, AC97_Powerdown_Ctrl_Stat , 0x000f); 586 592 587 593 /* 588 594 * Sigmatel 9700 (STAC9700) 589 595 */ 590 mixer_store 591 mixer_store 592 593 mixer_store 594 mixer_store 595 mixer_store 596 mixer_store 597 mixer_store 598 mixer_store 599 mixer_store 596 mixer_store(s, AC97_Vendor_ID1 , 0x8384); 597 mixer_store(s, AC97_Vendor_ID2 , 0x7600); /* 7608 */ 598 599 mixer_store(s, AC97_Extended_Audio_ID , 0x0809); 600 mixer_store(s, AC97_Extended_Audio_Ctrl_Stat, 0x0009); 601 mixer_store(s, AC97_PCM_Front_DAC_Rate , 0xbb80); 602 mixer_store(s, AC97_PCM_Surround_DAC_Rate , 0xbb80); 603 mixer_store(s, AC97_PCM_LFE_DAC_Rate , 0xbb80); 604 mixer_store(s, AC97_PCM_LR_ADC_Rate , 0xbb80); 605 mixer_store(s, AC97_MIC_ADC_Rate , 0xbb80); 600 606 601 607 #ifdef USE_MIXER 602 record_select 603 set_volume 604 set_volume 605 set_volume 608 record_select(s, 0); 609 set_volume(s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME, 0x8000); 610 set_volume(s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM, 0x8808); 611 set_volume(s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808); 606 612 #else 607 mixer_store 608 mixer_store 609 mixer_store 610 mixer_store 613 mixer_store(s, AC97_Record_Select, 0); 614 mixer_store(s, AC97_Master_Volume_Mute, 0x8000); 615 mixer_store(s, AC97_PCM_Out_Volume_Mute, 0x8808); 616 mixer_store(s, AC97_Line_In_Volume_Mute, 0x8808); 611 617 #endif 612 618 613 reset_voices (s, active); 614 } 615 616 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r, 617 int max, int *stop) 619 reset_voices(s, active); 620 } 621 622 static int write_audio(AC97LinkState *s, AC97BusMasterRegs *r, int max, int *stop) 618 623 { 619 624 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(s); 620 uint8_t tmpbuf[4096];621 uint32_t addr = r->bd.addr;622 uint32_t temp = r->picb << 1;623 uint32_t written = 0;624 int to_copy = 0;625 626 temp = audio_MIN (temp, (uint32_t)max);625 uint8_t tmpbuf[4096]; 626 uint32_t addr = r->bd.addr; 627 uint32_t temp = r->picb << 1; 628 uint32_t written = 0; 629 int to_copy = 0; 630 631 temp = audio_MIN(temp, (uint32_t)max); 627 632 if (!temp) 628 633 { … … 634 639 { 635 640 int copied; 636 to_copy = audio_MIN (temp, sizeof (tmpbuf)); 637 PDMDevHlpPhysRead (pDevIns, addr, tmpbuf, to_copy); 638 copied = AUD_write (s->voice_po, tmpbuf, to_copy); 639 Log (("ac97: write_audio max=%x to_copy=%x copied=%x\n", 640 max, to_copy, copied)); 641 to_copy = audio_MIN(temp, sizeof(tmpbuf)); 642 PDMDevHlpPhysRead(pDevIns, addr, tmpbuf, to_copy); 643 copied = AUD_write(s->voice_po, tmpbuf, to_copy); 644 Log(("ac97: write_audio max=%x to_copy=%x copied=%x\n", max, to_copy, copied)); 641 645 if (!copied) 642 646 { … … 653 657 if (to_copy < 4) 654 658 { 655 Log 659 Log(("ac97: whoops\n")); 656 660 s->last_samp = 0; 657 661 } … … 664 668 } 665 669 666 static void write_bup 670 static void write_bup(AC97LinkState *s, int elapsed) 667 671 { 668 672 int written = 0; 669 673 670 Log 674 Log(("ac97: write_bup\n")); 671 675 if (!(s->bup_flag & BUP_SET)) 672 676 { … … 675 679 unsigned int i; 676 680 uint32_t *p = (uint32_t*)s->silence; 677 for (i = 0; i < sizeof 681 for (i = 0; i < sizeof(s->silence) / 4; i++) 678 682 *p++ = s->last_samp; 679 683 } 680 684 else 681 memset (s->silence, 0, sizeof(s->silence));685 memset(s->silence, 0, sizeof(s->silence)); 682 686 683 687 s->bup_flag |= BUP_SET; … … 686 690 while (elapsed) 687 691 { 688 unsigned int temp = audio_MIN ((unsigned int)elapsed, sizeof(s->silence));692 unsigned int temp = audio_MIN((unsigned int)elapsed, sizeof(s->silence)); 689 693 while (temp) 690 694 { 691 int copied = AUD_write 695 int copied = AUD_write(s->voice_po, s->silence, temp); 692 696 if (!copied) 693 697 return; … … 699 703 } 700 704 701 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r, 702 int max, int *stop) 705 static int read_audio(AC97LinkState *s, AC97BusMasterRegs *r, int max, int *stop) 703 706 { 704 707 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(s); 705 uint8_t tmpbuf[4096];706 uint32_t addr = r->bd.addr;707 uint32_t temp = r->picb << 1;708 uint32_t nread = 0;709 int to_copy = 0;710 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;711 712 temp = audio_MIN (temp, (uint32_t)max);708 uint8_t tmpbuf[4096]; 709 uint32_t addr = r->bd.addr; 710 uint32_t temp = r->picb << 1; 711 uint32_t nread = 0; 712 int to_copy = 0; 713 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi; 714 715 temp = audio_MIN(temp, (uint32_t)max); 713 716 if (!temp) 714 717 { … … 720 723 { 721 724 int acquired; 722 to_copy = audio_MIN (temp, sizeof(tmpbuf));723 acquired = AUD_read 725 to_copy = audio_MIN(temp, sizeof(tmpbuf)); 726 acquired = AUD_read(voice, tmpbuf, to_copy); 724 727 if (!acquired) 725 728 { … … 727 730 break; 728 731 } 729 PDMDevHlpPhysWrite 732 PDMDevHlpPhysWrite(pDevIns, addr, tmpbuf, acquired); 730 733 temp -= acquired; 731 734 addr += acquired; … … 737 740 } 738 741 739 static void transfer_audio 742 static void transfer_audio(AC97LinkState *s, int index, int elapsed) 740 743 { 741 744 AC97BusMasterRegs *r = &s->bm_regs[index]; … … 748 751 switch (index) 749 752 { 750 case PO_INDEX:751 write_bup(s, elapsed);752 break;753 case PO_INDEX: 754 write_bup(s, elapsed); 755 break; 753 756 } 754 757 } … … 762 765 if (!r->bd_valid) 763 766 { 764 Log 765 fetch_bd 767 Log(("ac97: invalid bd\n")); 768 fetch_bd(s, r); 766 769 } 767 770 768 771 if (!r->picb) 769 772 { 770 Log (("ac97: fresh bd %d is empty %#x %#x, skipping\n", 771 r->civ, r->bd.addr, r->bd.ctl_len)); 773 Log(("ac97: fresh bd %d is empty %#x %#x, skipping\n", r->civ, r->bd.addr, r->bd.ctl_len)); 772 774 if (r->civ == r->lvi) 773 775 { … … 779 781 r->civ = r->piv; 780 782 r->piv = (r->piv + 1) % 32; 781 fetch_bd 783 fetch_bd(s, r); 782 784 continue; 783 785 } … … 786 788 { 787 789 case PO_INDEX: 788 temp = write_audio 790 temp = write_audio(s, r, elapsed, &stop); 789 791 written += temp; 790 792 elapsed -= temp; … … 795 797 case PI_INDEX: 796 798 case MC_INDEX: 797 temp = read_audio 799 temp = read_audio(s, r, elapsed, &stop); 798 800 elapsed -= temp; 799 801 Assert((temp & 1) == 0); /* Else the following shift won't work */ … … 802 804 } 803 805 804 Log 806 Log(("r->picb = %d\n", r->picb)); 805 807 806 808 if (!r->picb) … … 813 815 if (r->civ == r->lvi) 814 816 { 815 Log 817 Log(("ac97: Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi)); 816 818 new_sr |= SR_LVBCI | SR_DCH | SR_CELV; 817 819 stop = 1; … … 824 826 fetch_bd (s, r); 825 827 } 826 update_sr 827 } 828 } 829 } 830 831 static void pi_callback 832 { 833 transfer_audio ((AC97LinkState*)opaque, PI_INDEX, avail);834 } 835 836 static void mc_callback 837 { 838 transfer_audio ((AC97LinkState*)opaque, MC_INDEX, avail);839 } 840 841 static void po_callback 842 { 843 transfer_audio ((AC97LinkState*)opaque, PO_INDEX, free);828 update_sr(s, r, new_sr); 829 } 830 } 831 } 832 833 static void pi_callback(void *opaque, int avail) 834 { 835 transfer_audio((AC97LinkState *)opaque, PI_INDEX, avail); 836 } 837 838 static void mc_callback(void *opaque, int avail) 839 { 840 transfer_audio((AC97LinkState *)opaque, MC_INDEX, avail); 841 } 842 843 static void po_callback(void *opaque, int free) 844 { 845 transfer_audio((AC97LinkState *)opaque, PO_INDEX, free); 844 846 } 845 847 846 848 /** 847 * Port I/O Handler for IN operations. 848 * 849 * @returns VBox status code. 850 * 851 * @param pDevIns The device instance. 852 * @param pvUser User argument. 853 * @param uPort Port number used for the IN operation. 854 * @param pu32 Where to store the result. 855 * @param cb Number of bytes read. 849 * @callback_method_impl{FNIOMIOPORTIN} 856 850 */ 857 static DECLCALLBACK(int) ichac97IOPortNABMRead (PPDMDEVINS pDevIns, void *pvUser, 858 RTIOPORT Port, uint32_t *pu32, unsigned cb) 851 static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 859 852 { 860 853 PCIAC97LinkState *d = (PCIAC97LinkState*)pvUser; … … 873 866 case CAS: 874 867 /* Codec Access Semaphore Register */ 875 Log 868 Log(("ac97: CAS %d\n", s->cas)); 876 869 *pu32 = s->cas; 877 870 s->cas = 1; … … 881 874 case MC_CIV: 882 875 /* Current Index Value Register */ 883 r = &s->bm_regs[GET_BM 876 r = &s->bm_regs[GET_BM(index)]; 884 877 *pu32 = r->civ; 885 Log (("ac97: CIV[%d] -> %#x\n", GET_BM(index), *pu32));878 Log(("ac97: CIV[%d] -> %#x\n", GET_BM(index), *pu32)); 886 879 break; 887 880 case PI_LVI: … … 889 882 case MC_LVI: 890 883 /* Last Valid Index Register */ 891 r = &s->bm_regs[GET_BM 884 r = &s->bm_regs[GET_BM(index)]; 892 885 *pu32 = r->lvi; 893 Log (("ac97: LVI[%d] -> %#x\n", GET_BM(index), *pu32));886 Log(("ac97: LVI[%d] -> %#x\n", GET_BM(index), *pu32)); 894 887 break; 895 888 case PI_PIV: … … 897 890 case MC_PIV: 898 891 /* Prefetched Index Value Register */ 899 r = &s->bm_regs[GET_BM 892 r = &s->bm_regs[GET_BM(index)]; 900 893 *pu32 = r->piv; 901 Log (("ac97: PIV[%d] -> %#x\n", GET_BM(index), *pu32));894 Log(("ac97: PIV[%d] -> %#x\n", GET_BM(index), *pu32)); 902 895 break; 903 896 case PI_CR: … … 905 898 case MC_CR: 906 899 /* Control Register */ 907 r = &s->bm_regs[GET_BM 900 r = &s->bm_regs[GET_BM(index)]; 908 901 *pu32 = r->cr; 909 Log (("ac97: CR[%d] -> %#x\n", GET_BM(index), *pu32));902 Log(("ac97: CR[%d] -> %#x\n", GET_BM(index), *pu32)); 910 903 break; 911 904 case PI_SR: … … 913 906 case MC_SR: 914 907 /* Status Register (lower part) */ 915 r = &s->bm_regs[GET_BM 908 r = &s->bm_regs[GET_BM(index)]; 916 909 *pu32 = r->sr & 0xff; 917 Log (("ac97: SRb[%d] -> %#x\n", GET_BM(index), *pu32));910 Log(("ac97: SRb[%d] -> %#x\n", GET_BM(index), *pu32)); 918 911 break; 919 912 default: 920 Log 913 Log(("ac97: U nabm readb %#x -> %#x\n", Port, *pu32)); 921 914 break; 922 915 } … … 936 929 case MC_SR: 937 930 /* Status Register */ 938 r = &s->bm_regs[GET_BM 931 r = &s->bm_regs[GET_BM(index)]; 939 932 *pu32 = r->sr; 940 Log (("ac97: SR[%d] -> %#x\n", GET_BM(index), *pu32));933 Log(("ac97: SR[%d] -> %#x\n", GET_BM(index), *pu32)); 941 934 break; 942 935 case PI_PICB: … … 944 937 case MC_PICB: 945 938 /* Position in Current Buffer Register */ 946 r = &s->bm_regs[GET_BM 939 r = &s->bm_regs[GET_BM(index)]; 947 940 *pu32 = r->picb; 948 Log (("ac97: PICB[%d] -> %#x\n", GET_BM(index), *pu32));941 Log(("ac97: PICB[%d] -> %#x\n", GET_BM(index), *pu32)); 949 942 break; 950 943 default: 951 Log 944 Log(("ac97: U nabm readw %#x -> %#x\n", Port, *pu32)); 952 945 break; 953 946 } … … 967 960 case MC_BDBAR: 968 961 /* Buffer Descriptor Base Address Register */ 969 r = &s->bm_regs[GET_BM 962 r = &s->bm_regs[GET_BM(index)]; 970 963 *pu32 = r->bdbar; 971 Log (("ac97: BMADDR[%d] -> %#x\n", GET_BM(index), *pu32));964 Log(("ac97: BMADDR[%d] -> %#x\n", GET_BM(index), *pu32)); 972 965 break; 973 966 case PI_CIV: … … 977 970 * Last Valid Index Register + 978 971 * Status Register */ 979 r = &s->bm_regs[GET_BM 972 r = &s->bm_regs[GET_BM(index)]; 980 973 *pu32 = r->civ | (r->lvi << 8) | (r->sr << 16); 981 Log (("ac97: CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index), 982 r->civ, r->lvi, r->sr)); 974 Log(("ac97: CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM(index), r->civ, r->lvi, r->sr)); 983 975 break; 984 976 case PI_PICB: … … 988 980 * Prefetched Index Value Register + 989 981 * Control Register */ 990 r = &s->bm_regs[GET_BM 982 r = &s->bm_regs[GET_BM(index)]; 991 983 *pu32 = r->picb | (r->piv << 16) | (r->cr << 24); 992 Log (("ac97: PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index), 993 *pu32, r->picb, r->piv, r->cr)); 984 Log(("ac97: PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM(index), *pu32, r->picb, r->piv, r->cr)); 994 985 break; 995 986 case GLOB_CNT: 996 987 /* Global Control */ 997 988 *pu32 = s->glob_cnt; 998 Log 989 Log(("ac97: glob_cnt -> %#x\n", *pu32)); 999 990 break; 1000 991 case GLOB_STA: 1001 992 /* Global Status */ 1002 993 *pu32 = s->glob_sta | GS_S0CR; 1003 Log 994 Log(("ac97: glob_sta -> %#x\n", *pu32)); 1004 995 break; 1005 996 default: 1006 Log 997 Log(("ac97: U nabm readl %#x -> %#x\n", Port, *pu32)); 1007 998 break; 1008 999 } … … 1017 1008 1018 1009 /** 1019 * Port I/O Handler for OUT operations. 1020 * 1021 * @returns VBox status code. 1022 * 1023 * @param pDevIns The device instance. 1024 * @param pvUser User argument. 1025 * @param uPort Port number used for the IN operation. 1026 * @param u32 The value to output. 1027 * @param cb The value size in bytes. 1010 * @callback_method_impl{FNIOMIOPORTOUT} 1028 1011 */ 1029 static DECLCALLBACK(int) ichac97IOPortNABMWrite (PPDMDEVINS pDevIns, void *pvUser, 1030 RTIOPORT Port, uint32_t u32, unsigned cb) 1012 static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1031 1013 { 1032 1014 PCIAC97LinkState *d = (PCIAC97LinkState*)pvUser; … … 1045 1027 case MC_LVI: 1046 1028 /* Last Valid Index */ 1047 r = &s->bm_regs[GET_BM (index)]; 1048 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) { 1029 r = &s->bm_regs[GET_BM(index)]; 1030 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) 1031 { 1049 1032 r->sr &= ~(SR_DCH | SR_CELV); 1050 1033 r->civ = r->piv; … … 1053 1036 } 1054 1037 r->lvi = u32 % 32; 1055 Log (("ac97: LVI[%d] <- %#x\n", GET_BM(index), u32));1038 Log(("ac97: LVI[%d] <- %#x\n", GET_BM(index), u32)); 1056 1039 break; 1057 1040 case PI_CR: … … 1059 1042 case MC_CR: 1060 1043 /* Control Register */ 1061 r = &s->bm_regs[GET_BM 1044 r = &s->bm_regs[GET_BM(index)]; 1062 1045 if (u32 & CR_RR) 1063 reset_bm_regs 1046 reset_bm_regs(s, r); 1064 1047 else 1065 1048 { … … 1067 1050 if (!(r->cr & CR_RPBM)) 1068 1051 { 1069 voice_set_active 1052 voice_set_active(s, r - s->bm_regs, 0); 1070 1053 r->sr |= SR_DCH; 1071 1054 } … … 1074 1057 r->civ = r->piv; 1075 1058 r->piv = (r->piv + 1) % 32; 1076 fetch_bd 1059 fetch_bd(s, r); 1077 1060 r->sr &= ~SR_DCH; 1078 voice_set_active 1061 voice_set_active(s, r - s->bm_regs, 1); 1079 1062 } 1080 1063 } 1081 Log (("ac97: CR[%d] <- %#x (cr %#x)\n", GET_BM(index), u32, r->cr));1064 Log(("ac97: CR[%d] <- %#x (cr %#x)\n", GET_BM(index), u32, r->cr)); 1082 1065 break; 1083 1066 case PI_SR: … … 1085 1068 case MC_SR: 1086 1069 /* Status Register */ 1087 r = &s->bm_regs[GET_BM 1070 r = &s->bm_regs[GET_BM(index)]; 1088 1071 r->sr |= u32 & ~(SR_RO_MASK | SR_WCLEAR_MASK); 1089 update_sr 1090 Log (("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, r->sr));1072 update_sr(s, r, r->sr & ~(u32 & SR_WCLEAR_MASK)); 1073 Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, r->sr)); 1091 1074 break; 1092 1075 default: 1093 Log 1076 Log(("ac97: U nabm writeb %#x <- %#x\n", Port, u32)); 1094 1077 break; 1095 1078 } … … 1107 1090 case MC_SR: 1108 1091 /* Status Register */ 1109 r = &s->bm_regs[GET_BM 1092 r = &s->bm_regs[GET_BM(index)]; 1110 1093 r->sr |= u32 & ~(SR_RO_MASK | SR_WCLEAR_MASK); 1111 update_sr 1112 Log (("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, r->sr));1094 update_sr(s, r, r->sr & ~(u32 & SR_WCLEAR_MASK)); 1095 Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, r->sr)); 1113 1096 break; 1114 1097 default: 1115 Log 1098 Log(("ac97: U nabm writew %#x <- %#x\n", Port, u32)); 1116 1099 break; 1117 1100 } … … 1129 1112 case MC_BDBAR: 1130 1113 /* Buffer Descriptor list Base Address Register */ 1131 r = &s->bm_regs[GET_BM 1114 r = &s->bm_regs[GET_BM(index)]; 1132 1115 r->bdbar = u32 & ~3; 1133 Log (("ac97: BDBAR[%d] <- %#x (bdbar %#x)\n", 1134 GET_BM (index), u32, r->bdbar)); 1116 Log(("ac97: BDBAR[%d] <- %#x (bdbar %#x)\n", GET_BM(index), u32, r->bdbar)); 1135 1117 break; 1136 1118 case GLOB_CNT: … … 1142 1124 if (!(u32 & (GC_WR | GC_CR))) 1143 1125 s->glob_cnt = u32 & GC_VALID_MASK; 1144 Log 1126 Log(("ac97: glob_cnt <- %#x (glob_cnt %#x)\n", u32, s->glob_cnt)); 1145 1127 break; 1146 1128 case GLOB_STA: … … 1148 1130 s->glob_sta &= ~(u32 & GS_WCLEAR_MASK); 1149 1131 s->glob_sta |= (u32 & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; 1150 Log 1132 Log(("ac97: glob_sta <- %#x (glob_sta %#x)\n", u32, s->glob_sta)); 1151 1133 break; 1152 1134 default: 1153 Log 1135 Log(("ac97: U nabm writel %#x <- %#x\n", Port, u32)); 1154 1136 break; 1155 1137 } … … 1165 1147 1166 1148 /** 1167 * Port I/O Handler for IN operations. 1168 * 1169 * @returns VBox status code. 1170 * 1171 * @param pDevIns The device instance. 1172 * @param pvUser User argument. 1173 * @param uPort Port number used for the IN operation. 1174 * @param pu32 Where to store the result. 1175 * @param cb Number of bytes read. 1149 * @callback_method_impl{FNIOMIOPORTIN} 1176 1150 */ 1177 static DECLCALLBACK(int) ichac97IOPortNAMRead (PPDMDEVINS pDevIns, void *pvUser, 1178 RTIOPORT Port, uint32_t *pu32, unsigned cb) 1151 static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1179 1152 { 1180 1153 PCIAC97LinkState *d = (PCIAC97LinkState*)pvUser; … … 1185 1158 case 1: 1186 1159 { 1187 Log 1160 Log(("ac97: U nam readb %#x\n", Port)); 1188 1161 s->cas = 0; 1189 1162 *pu32 = ~0U; … … 1198 1171 switch (index) 1199 1172 { 1200 default:1201 *pu32 = mixer_load(s, index);1202 Log(("ac97: nam readw %#x -> %#x\n", Port, *pu32));1203 break;1173 default: 1174 *pu32 = mixer_load(s, index); 1175 Log(("ac97: nam readw %#x -> %#x\n", Port, *pu32)); 1176 break; 1204 1177 } 1205 1178 break; … … 1208 1181 case 4: 1209 1182 { 1210 Log 1183 Log(("ac97: U nam readl %#x\n", Port)); 1211 1184 s->cas = 0; 1212 1185 *pu32 = ~0U; … … 1221 1194 1222 1195 /** 1223 * Port I/O Handler for OUT operations. 1224 * 1225 * @returns VBox status code. 1226 * 1227 * @param pDevIns The device instance. 1228 * @param pvUser User argument. 1229 * @param uPort Port number used for the IN operation. 1230 * @param u32 The value to output. 1231 * @param cb The value size in bytes. 1196 * @callback_method_impl{FNIOMIOPORTOUT} 1232 1197 */ 1233 static DECLCALLBACK(int) ichac97IOPortNAMWrite (PPDMDEVINS pDevIns, void *pvUser, 1234 RTIOPORT Port, uint32_t u32, unsigned cb) 1198 static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1235 1199 { 1236 1200 PCIAC97LinkState *d = (PCIAC97LinkState*)pvUser; … … 1241 1205 case 1: 1242 1206 { 1243 Log 1207 Log(("ac97: U nam writeb %#x <- %#x\n", Port, u32)); 1244 1208 s->cas = 0; 1245 1209 break; … … 1253 1217 { 1254 1218 case AC97_Reset: 1255 mixer_reset 1219 mixer_reset(s); 1256 1220 break; 1257 1221 case AC97_Powerdown_Ctrl_Stat: 1258 1222 u32 &= ~0xf; 1259 u32 |= mixer_load 1260 mixer_store 1223 u32 |= mixer_load(s, index) & 0xf; 1224 mixer_store(s, index, u32); 1261 1225 break; 1262 1226 #ifdef USE_MIXER 1263 1227 case AC97_Master_Volume_Mute: 1264 set_volume 1228 set_volume(s, index, AUD_MIXER_VOLUME, u32); 1265 1229 break; 1266 1230 case AC97_PCM_Out_Volume_Mute: 1267 set_volume 1231 set_volume(s, index, AUD_MIXER_PCM, u32); 1268 1232 break; 1269 1233 case AC97_Line_In_Volume_Mute: 1270 set_volume 1234 set_volume(s, index, AUD_MIXER_LINE_IN, u32); 1271 1235 break; 1272 1236 case AC97_Record_Select: 1273 record_select 1237 record_select(s, u32); 1274 1238 break; 1275 1239 #else /* !USE_MIXER */ … … 1278 1242 case AC97_Line_In_Volume_Mute: 1279 1243 case AC97_Record_Select: 1280 mixer_store 1244 mixer_store(s, index, u32); 1281 1245 break; 1282 1246 #endif /* !USE_MIXER */ 1283 1247 case AC97_Vendor_ID1: 1284 1248 case AC97_Vendor_ID2: 1285 Log 1249 Log(("ac97: Attempt to write vendor ID to %#x\n", u32)); 1286 1250 break; 1287 1251 case AC97_Extended_Audio_ID: 1288 Log 1252 Log(("ac97: Attempt to write extended audio ID to %#x\n", u32)); 1289 1253 break; 1290 1254 case AC97_Extended_Audio_Ctrl_Stat: 1291 1255 if (!(u32 & EACS_VRA)) 1292 1256 { 1293 mixer_store 1294 mixer_store 1295 open_voice 1296 open_voice 1257 mixer_store(s, AC97_PCM_Front_DAC_Rate, 0xbb80); 1258 mixer_store(s, AC97_PCM_LR_ADC_Rate, 0xbb80); 1259 open_voice(s, PI_INDEX, 48000); 1260 open_voice(s, PO_INDEX, 48000); 1297 1261 } 1298 1262 if (!(u32 & EACS_VRM)) 1299 1263 { 1300 mixer_store 1301 open_voice 1264 mixer_store(s, AC97_MIC_ADC_Rate, 0xbb80); 1265 open_voice(s, MC_INDEX, 48000); 1302 1266 } 1303 Log 1304 mixer_store 1267 Log(("ac97: Setting extended audio control to %#x\n", u32)); 1268 mixer_store(s, AC97_Extended_Audio_Ctrl_Stat, u32); 1305 1269 break; 1306 1270 case AC97_PCM_Front_DAC_Rate: 1307 if (mixer_load 1271 if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) 1308 1272 { 1309 mixer_store 1273 mixer_store(s, index, u32); 1310 1274 Log(("ac97: Set front DAC rate to %d\n", u32)); 1311 open_voice 1275 open_voice(s, PO_INDEX, u32); 1312 1276 } 1313 1277 else 1278 Log(("ac97: Attempt to set front DAC rate to %d, but VRA is not set\n", u32)); 1279 break; 1280 case AC97_MIC_ADC_Rate: 1281 if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) 1314 1282 { 1315 Log (("ac97: Attempt to set front DAC rate to %d, " 1316 "but VRA is not set\n", 1317 u32)); 1318 } 1319 break; 1320 case AC97_MIC_ADC_Rate: 1321 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) 1322 { 1323 mixer_store (s, index, u32); 1324 Log (("ac97: Set MIC ADC rate to %d\n", u32)); 1325 open_voice (s, MC_INDEX, u32); 1283 mixer_store(s, index, u32); 1284 Log(("ac97: Set MIC ADC rate to %d\n", u32)); 1285 open_voice(s, MC_INDEX, u32); 1326 1286 } 1327 1287 else 1288 Log(("ac97: Attempt to set MIC ADC rate to %d, but VRM is not set\n", u32)); 1289 break; 1290 case AC97_PCM_LR_ADC_Rate: 1291 if (mixer_load(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) 1328 1292 { 1329 Log (("ac97: Attempt to set MIC ADC rate to %d, " 1330 "but VRM is not set\n", 1331 u32)); 1332 } 1333 break; 1334 case AC97_PCM_LR_ADC_Rate: 1335 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) 1336 { 1337 mixer_store (s, index, u32); 1338 Log (("ac97: Set front LR ADC rate to %d\n", u32)); 1339 open_voice (s, PI_INDEX, u32); 1293 mixer_store(s, index, u32); 1294 Log(("ac97: Set front LR ADC rate to %d\n", u32)); 1295 open_voice(s, PI_INDEX, u32); 1340 1296 } 1341 1297 else 1342 { 1343 Log (("ac97: Attempt to set LR ADC rate to %d, but VRA is not set\n", 1344 u32)); 1345 } 1298 Log(("ac97: Attempt to set LR ADC rate to %d, but VRA is not set\n", u32)); 1346 1299 break; 1347 1300 default: 1348 Log 1349 mixer_store 1301 Log(("ac97: U nam writew %#x <- %#x\n", Port, u32)); 1302 mixer_store(s, index, u32); 1350 1303 break; 1351 1304 } … … 1355 1308 case 4: 1356 1309 { 1357 Log 1310 Log(("ac97: U nam writel %#x <- %#x\n", Port, u32)); 1358 1311 s->cas = 0; 1359 1312 break; … … 1367 1320 } 1368 1321 1322 1369 1323 /** 1370 * Callback function for mapping a PCI I/O region. 1371 * 1372 * @return VBox status code. 1373 * @param pPciDev Pointer to PCI device. 1374 * Use pPciDev->pDevIns to get the device instance. 1375 * @param iRegion The region number. 1376 * @param GCPhysAddress Physical address of the region. 1377 * If iType is PCI_ADDRESS_SPACE_IO, this is an 1378 * I/O port, else it's a physical address. 1379 * This address is *NOT* relative 1380 * to pci_mem_base like earlier! 1381 * @param enmType One of the PCI_ADDRESS_SPACE_* values. 1324 * @callback_method_impl{FNPCIIOREGIONMAP} 1382 1325 */ 1383 static DECLCALLBACK(int) ichac97IOPortMap (PPCIDEVICE pPciDev, int iRegion, 1384 RTGCPHYS GCPhysAddress, uint32_t cb, 1385 PCIADDRESSSPACE enmType) 1386 { 1387 int rc; 1388 PPDMDEVINS pDevIns = pPciDev->pDevIns; 1389 RTIOPORT Port = (RTIOPORT)GCPhysAddress; 1390 PCIAC97LinkState *pThis = PCIDEV_2_ICHAC97STATE(pPciDev); 1326 static DECLCALLBACK(int) ichac97IOPortMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, 1327 PCIADDRESSSPACE enmType) 1328 { 1329 PPDMDEVINS pDevIns = pPciDev->pDevIns; 1330 PCIAC97LinkState *pThis = PCIDEV_2_ICHAC97STATE(pPciDev); 1331 RTIOPORT Port = (RTIOPORT)GCPhysAddress; 1332 int rc; 1391 1333 1392 1334 Assert(enmType == PCI_ADDRESS_SPACE_IO); … … 1394 1336 1395 1337 if (iRegion == 0) 1396 rc = PDMDevHlpIOPortRegister 1397 1398 1338 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 256, pThis, 1339 ichac97IOPortNAMWrite, ichac97IOPortNAMRead, 1340 NULL, NULL, "ICHAC97 NAM"); 1399 1341 else 1400 rc = PDMDevHlpIOPortRegister 1401 1402 1342 rc = PDMDevHlpIOPortRegister(pDevIns, Port, 64, pThis, 1343 ichac97IOPortNABMWrite, ichac97IOPortNABMRead, 1344 NULL, NULL, "ICHAC97 NABM"); 1403 1345 if (RT_FAILURE(rc)) 1404 1346 return rc; … … 1408 1350 } 1409 1351 1352 1410 1353 /** 1411 * Saves a state of the AC'97 device. 1412 * 1413 * @returns VBox status code. 1414 * @param pDevIns The device instance. 1415 * @param pSSMHandle The handle to save the state to. 1354 * @callback_method_impl{FNSSMDEVSAVEEXEC} 1416 1355 */ 1417 static DECLCALLBACK(int) ichac97SaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle) 1418 { 1419 PCIAC97LinkState *pThis = PDMINS_2_DATA(pDevIns, PCIAC97LinkState *); 1420 size_t i; 1421 uint8_t active[LAST_INDEX]; 1422 AC97LinkState *s = &pThis->ac97; 1423 1424 SSMR3PutU32 (pSSMHandle, s->glob_cnt); 1425 SSMR3PutU32 (pSSMHandle, s->glob_sta); 1426 SSMR3PutU32 (pSSMHandle, s->cas); 1427 1428 for (i = 0; i < sizeof (s->bm_regs) / sizeof (s->bm_regs[0]); ++i) 1429 { 1430 AC97BusMasterRegs *r = &s->bm_regs[i]; 1431 SSMR3PutU32 (pSSMHandle, r->bdbar); 1432 SSMR3PutU8 (pSSMHandle, r->civ); 1433 SSMR3PutU8 (pSSMHandle, r->lvi); 1434 SSMR3PutU16 (pSSMHandle, r->sr); 1435 SSMR3PutU16 (pSSMHandle, r->picb); 1436 SSMR3PutU8 (pSSMHandle, r->piv); 1437 SSMR3PutU8 (pSSMHandle, r->cr); 1438 SSMR3PutS32 (pSSMHandle, r->bd_valid); 1439 SSMR3PutU32 (pSSMHandle, r->bd.addr); 1440 SSMR3PutU32 (pSSMHandle, r->bd.ctl_len); 1441 } 1442 SSMR3PutMem (pSSMHandle, s->mixer_data, sizeof (s->mixer_data)); 1443 1444 active[PI_INDEX] = AUD_is_active_in (s->voice_pi) ? 1 : 0; 1445 active[PO_INDEX] = AUD_is_active_out (s->voice_po) ? 1 : 0; 1446 active[MC_INDEX] = AUD_is_active_in (s->voice_mc) ? 1 : 0; 1447 SSMR3PutMem (pSSMHandle, active, sizeof (active)); 1448 1449 return VINF_SUCCESS; 1450 } 1451 1452 /** 1453 * Loads a saved AC'97 device state. 1454 * 1455 * @returns VBox status code. 1456 * @param pDevIns The device instance. 1457 * @param pSSMHandle The handle to the saved state. 1458 * @param uVersion The data unit version number. 1459 * @param uPass The data pass. 1460 */ 1461 static DECLCALLBACK(int) ichac97LoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, 1462 uint32_t uVersion, uint32_t uPass) 1356 static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 1463 1357 { 1464 1358 PCIAC97LinkState *pThis = PDMINS_2_DATA(pDevIns, PCIAC97LinkState *); 1465 1359 AC97LinkState *s = &pThis->ac97; 1360 1361 SSMR3PutU32(pSSM, s->glob_cnt); 1362 SSMR3PutU32(pSSM, s->glob_sta); 1363 SSMR3PutU32(pSSM, s->cas); 1364 1365 for (unsigned i = 0; i < RT_ELEMENTS(s->bm_regs); i++) 1366 { 1367 AC97BusMasterRegs *r = &s->bm_regs[i]; 1368 SSMR3PutU32(pSSM, r->bdbar); 1369 SSMR3PutU8( pSSM, r->civ); 1370 SSMR3PutU8( pSSM, r->lvi); 1371 SSMR3PutU16(pSSM, r->sr); 1372 SSMR3PutU16(pSSM, r->picb); 1373 SSMR3PutU8( pSSM, r->piv); 1374 SSMR3PutU8( pSSM, r->cr); 1375 SSMR3PutS32(pSSM, r->bd_valid); 1376 SSMR3PutU32(pSSM, r->bd.addr); 1377 SSMR3PutU32(pSSM, r->bd.ctl_len); 1378 } 1379 SSMR3PutMem(pSSM, s->mixer_data, sizeof(s->mixer_data)); 1380 1466 1381 uint8_t active[LAST_INDEX]; 1467 size_t i; 1382 active[PI_INDEX] = AUD_is_active_in( s->voice_pi) ? 1 : 0; 1383 active[PO_INDEX] = AUD_is_active_out(s->voice_po) ? 1 : 0; 1384 active[MC_INDEX] = AUD_is_active_in( s->voice_mc) ? 1 : 0; 1385 SSMR3PutMem(pSSM, active, sizeof(active)); 1386 1387 return VINF_SUCCESS; 1388 } 1389 1390 1391 /** 1392 * @callback_method_impl{FNSSMDEVLOADEXEC} 1393 */ 1394 static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 1395 { 1396 PCIAC97LinkState *pThis = PDMINS_2_DATA(pDevIns, PCIAC97LinkState *); 1397 AC97LinkState *s = &pThis->ac97; 1468 1398 1469 1399 AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION); 1470 Assert 1471 1472 SSMR3GetU32 (pSSMHandle, &s->glob_cnt);1473 SSMR3GetU32 (pSSMHandle, &s->glob_sta);1474 SSMR3GetU32 (pSSMHandle, &s->cas);1475 1476 for ( i = 0; i < sizeof (s->bm_regs) / sizeof (s->bm_regs[0]); ++i)1400 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass); 1401 1402 SSMR3GetU32(pSSM, &s->glob_cnt); 1403 SSMR3GetU32(pSSM, &s->glob_sta); 1404 SSMR3GetU32(pSSM, &s->cas); 1405 1406 for (unsigned i = 0; i < RT_ELEMENTS(s->bm_regs); i++) 1477 1407 { 1478 1408 AC97BusMasterRegs *r = &s->bm_regs[i]; 1479 SSMR3GetU32 (pSSMHandle, &r->bdbar); 1480 SSMR3GetU8 (pSSMHandle, &r->civ); 1481 SSMR3GetU8 (pSSMHandle, &r->lvi); 1482 SSMR3GetU16 (pSSMHandle, &r->sr); 1483 SSMR3GetU16 (pSSMHandle, &r->picb); 1484 SSMR3GetU8 (pSSMHandle, &r->piv); 1485 SSMR3GetU8 (pSSMHandle, &r->cr); 1486 SSMR3GetS32 (pSSMHandle, &r->bd_valid); 1487 SSMR3GetU32 (pSSMHandle, &r->bd.addr); 1488 SSMR3GetU32 (pSSMHandle, &r->bd.ctl_len); 1489 } 1490 SSMR3GetMem (pSSMHandle, s->mixer_data, sizeof (s->mixer_data)); 1491 SSMR3GetMem (pSSMHandle, active, sizeof (active)); 1409 SSMR3GetU32(pSSM, &r->bdbar); 1410 SSMR3GetU8( pSSM, &r->civ); 1411 SSMR3GetU8( pSSM, &r->lvi); 1412 SSMR3GetU16(pSSM, &r->sr); 1413 SSMR3GetU16(pSSM, &r->picb); 1414 SSMR3GetU8( pSSM, &r->piv); 1415 SSMR3GetU8( pSSM, &r->cr); 1416 SSMR3GetS32(pSSM, &r->bd_valid); 1417 SSMR3GetU32(pSSM, &r->bd.addr); 1418 SSMR3GetU32(pSSM, &r->bd.ctl_len); 1419 } 1420 1421 SSMR3GetMem(pSSM, s->mixer_data, sizeof(s->mixer_data)); 1422 uint8_t active[LAST_INDEX]; 1423 SSMR3GetMem(pSSM, active, sizeof(active)); 1492 1424 1493 1425 #ifdef USE_MIXER 1494 record_select (s, mixer_load(s, AC97_Record_Select));1495 # define V_(a, b) set_volume (s, a, b, mixer_load(s, a))1496 V_ 1497 V_ 1498 V_ 1426 record_select(s, mixer_load(s, AC97_Record_Select)); 1427 # define V_(a, b) set_volume(s, a, b, mixer_load(s, a)) 1428 V_(AC97_Master_Volume_Mute, AUD_MIXER_VOLUME); 1429 V_(AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM); 1430 V_(AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN); 1499 1431 # undef V_ 1500 1432 #endif /* USE_MIXER */ 1501 reset_voices 1433 reset_voices(s, active); 1502 1434 1503 1435 s->bup_flag = 0; … … 1507 1439 } 1508 1440 1441 1509 1442 /** 1510 * Reset notification. 1443 * @interface_method_impl{PDMIBASE,pfnQueryInterface} 1444 */ 1445 static DECLCALLBACK(void *) ichac97QueryInterface(struct PDMIBASE *pInterface, const char *pszIID) 1446 { 1447 PCIAC97LinkState *pThis = RT_FROM_MEMBER(pInterface, PCIAC97LinkState, ac97.IBase); 1448 Assert(&pThis->ac97.IBase == pInterface); 1449 1450 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->ac97.IBase); 1451 return NULL; 1452 } 1453 1454 1455 /** 1456 * @interface_method_impl{PDMDEVREG,pfnReset} 1511 1457 * 1512 * @returns VBox status. 1513 * @param pDevIns The device instance data. 1514 * 1515 * @remark The original sources didn't install a reset handler, but it seems to 1458 * @remarks The original sources didn't install a reset handler, but it seems to 1516 1459 * make sense to me so we'll do it. 1517 1460 */ 1518 static DECLCALLBACK(void) ac97Reset 1461 static DECLCALLBACK(void) ac97Reset(PPDMDEVINS pDevIns) 1519 1462 { 1520 1463 PCIAC97LinkState *pThis = PDMINS_2_DATA(pDevIns, PCIAC97LinkState *); … … 1523 1466 * Reset the device state (will need pDrv later). 1524 1467 */ 1525 reset_bm_regs 1526 reset_bm_regs 1527 reset_bm_regs 1468 reset_bm_regs(&pThis->ac97, &pThis->ac97.bm_regs[0]); 1469 reset_bm_regs(&pThis->ac97, &pThis->ac97.bm_regs[1]); 1470 reset_bm_regs(&pThis->ac97, &pThis->ac97.bm_regs[2]); 1528 1471 1529 1472 /* … … 1532 1475 * the codec manually. 1533 1476 */ 1534 mixer_reset (&pThis->ac97); 1535 } 1536 1537 /** 1538 * @interface_method_impl{PDMIBASE,pfnQueryInterface} 1539 */ 1540 static DECLCALLBACK(void *) ichac97QueryInterface (struct PDMIBASE *pInterface, 1541 const char *pszIID) 1542 { 1543 PCIAC97LinkState *pThis = RT_FROM_MEMBER(pInterface, PCIAC97LinkState, ac97.IBase); 1544 Assert(&pThis->ac97.IBase == pInterface); 1545 1546 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->ac97.IBase); 1547 return NULL; 1548 } 1477 mixer_reset(&pThis->ac97); 1478 } 1479 1549 1480 1550 1481 /** 1551 1482 * @interface_method_impl{PDMDEVREG,pfnConstruct} 1552 1483 */ 1553 static DECLCALLBACK(int) ichac97Construct (PPDMDEVINS pDevIns, int iInstance, 1554 PCFGMNODE pCfgHandle) 1484 static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 1555 1485 { 1556 1486 PCIAC97LinkState *pThis = PDMINS_2_DATA(pDevIns, PCIAC97LinkState *); … … 1564 1494 * Validations. 1565 1495 */ 1566 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))1567 return PDMDEV_SET_ERROR 1568 N_("Invalid configuration for the AC97 device"));1496 if (!CFGMR3AreValuesValid(pCfg, "\0")) 1497 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, 1498 N_("Invalid configuration for the AC97 device")); 1569 1499 1570 1500 /* … … 1576 1506 1577 1507 /* PCI Device (the assertions will be removed later) */ 1578 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */ Assert (pThis->dev.config[0x00] == 0x86); Assert (pThis->dev.config[0x01] == 0x80); 1579 PCIDevSetDeviceId (&pThis->dev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */Assert (pThis->dev.config[0x02] == 0x15); Assert (pThis->dev.config[0x03] == 0x24); 1580 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert (pThis->dev.config[0x04] == 0x00); Assert (pThis->dev.config[0x05] == 0x00); 1581 PCIDevSetStatus (&pThis->dev, 1582 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert (pThis->dev.config[0x06] == 0x80); Assert (pThis->dev.config[0x07] == 0x02); 1583 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */ Assert (pThis->dev.config[0x08] == 0x01); 1584 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */ Assert (pThis->dev.config[0x09] == 0x00); 1585 PCIDevSetClassSub (&pThis->dev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert (pThis->dev.config[0x0a] == 0x01); 1586 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert (pThis->dev.config[0x0b] == 0x04); 1587 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */ Assert (pThis->dev.config[0x0e] == 0x00); 1588 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - nambar - native audio mixer base. */ 1589 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert (pThis->dev.config[0x10] == 0x01); Assert (pThis->dev.config[0x11] == 0x00); Assert (pThis->dev.config[0x12] == 0x00); Assert (pThis->dev.config[0x13] == 0x00); 1590 PCIDevSetBaseAddress (&pThis->dev, 1, /* 14 rw - nabmbar - native audio bus mastering. */ 1591 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert (pThis->dev.config[0x14] == 0x01); Assert (pThis->dev.config[0x15] == 0x00); Assert (pThis->dev.config[0x16] == 0x00); Assert (pThis->dev.config[0x17] == 0x00); 1592 PCIDevSetSubSystemVendorId (&pThis->dev, 0x8086); /* 2c ro - intel.) */ Assert (pThis->dev.config[0x2c] == 0x86); Assert (pThis->dev.config[0x2d] == 0x80); 1593 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */ Assert (pThis->dev.config[0x2e] == 0x00); Assert (pThis->dev.config[0x2f] == 0x00); 1594 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */ Assert (pThis->dev.config[0x3c] == 0x00); 1595 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert (pThis->dev.config[0x3d] == 0x01); 1508 PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */ Assert(pThis->dev.config[0x00] == 0x86); Assert(pThis->dev.config[0x01] == 0x80); 1509 PCIDevSetDeviceId (&pThis->dev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->dev.config[0x02] == 0x15); Assert(pThis->dev.config[0x03] == 0x24); 1510 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->dev.config[0x04] == 0x00); Assert(pThis->dev.config[0x05] == 0x00); 1511 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->dev.config[0x06] == 0x80); Assert(pThis->dev.config[0x07] == 0x02); 1512 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */ Assert(pThis->dev.config[0x08] == 0x01); 1513 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */ Assert(pThis->dev.config[0x09] == 0x00); 1514 PCIDevSetClassSub (&pThis->dev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->dev.config[0x0a] == 0x01); 1515 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->dev.config[0x0b] == 0x04); 1516 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->dev.config[0x0e] == 0x00); 1517 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - nambar - native audio mixer base. */ 1518 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->dev.config[0x10] == 0x01); Assert(pThis->dev.config[0x11] == 0x00); Assert(pThis->dev.config[0x12] == 0x00); Assert(pThis->dev.config[0x13] == 0x00); 1519 PCIDevSetBaseAddress (&pThis->dev, 1, /* 14 rw - nabmbar - native audio bus mastering. */ 1520 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->dev.config[0x14] == 0x01); Assert(pThis->dev.config[0x15] == 0x00); Assert(pThis->dev.config[0x16] == 0x00); Assert(pThis->dev.config[0x17] == 0x00); 1521 PCIDevSetSubSystemVendorId(&pThis->dev, 0x8086); /* 2c ro - intel.) */ Assert(pThis->dev.config[0x2c] == 0x86); Assert(pThis->dev.config[0x2d] == 0x80); 1522 PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */ Assert(pThis->dev.config[0x2e] == 0x00); Assert(pThis->dev.config[0x2f] == 0x00); 1523 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */ Assert(pThis->dev.config[0x3c] == 0x00); 1524 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->dev.config[0x3d] == 0x01); 1596 1525 1597 1526 /* … … 1599 1528 * saved state item. 1600 1529 */ 1601 rc = PDMDevHlpPCIRegister 1530 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev); 1602 1531 if (RT_FAILURE (rc)) 1603 1532 return rc; 1604 1533 1605 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, 1606 ichac97IOPortMap); 1534 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 256, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap); 1607 1535 if (RT_FAILURE (rc)) 1608 1536 return rc; 1609 1537 1610 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, 1611 ichac97IOPortMap); 1538 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 64, PCI_ADDRESS_SPACE_IO, ichac97IOPortMap); 1612 1539 if (RT_FAILURE (rc)) 1613 1540 return rc; 1614 1541 1615 rc = PDMDevHlpSSMRegister 1542 rc = PDMDevHlpSSMRegister(pDevIns, AC97_SSM_VERSION, sizeof(*pThis), ichac97SaveExec, ichac97LoadExec); 1616 1543 if (RT_FAILURE (rc)) 1617 1544 return rc; … … 1620 1547 * Attach driver. 1621 1548 */ 1622 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, 1623 &s->pDrvBase, "Audio Driver Port"); 1549 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "Audio Driver Port"); 1624 1550 if (rc == VERR_PDM_NO_ATTACHED_DRIVER) 1625 Log 1626 else if (RT_FAILURE 1627 { 1628 AssertMsgFailed 1551 Log(("ac97: No attached driver!\n")); 1552 else if (RT_FAILURE(rc)) 1553 { 1554 AssertMsgFailed(("Failed to attach AC97 LUN #0! rc=%Rrc\n", rc)); 1629 1555 return rc; 1630 1556 } 1631 1557 1632 AUD_register_card 1633 1634 ac97Reset 1558 AUD_register_card("ICH0", &s->card); 1559 1560 ac97Reset(pDevIns); 1635 1561 1636 1562 if (!AUD_is_host_voice_in_ok(s->voice_pi)) 1637 LogRel 1563 LogRel(("AC97: WARNING: Unable to open PCM IN!\n")); 1638 1564 if (!AUD_is_host_voice_in_ok(s->voice_mc)) 1639 LogRel 1565 LogRel(("AC97: WARNING: Unable to open PCM MC!\n")); 1640 1566 if (!AUD_is_host_voice_out_ok(s->voice_po)) 1641 LogRel 1642 1643 if ( !AUD_is_host_voice_in_ok( s->voice_pi)1567 LogRel(("AC97: WARNING: Unable to open PCM OUT!\n")); 1568 1569 if ( !AUD_is_host_voice_in_ok( s->voice_pi) 1644 1570 && !AUD_is_host_voice_out_ok(s->voice_po) 1645 && !AUD_is_host_voice_in_ok( s->voice_mc))1571 && !AUD_is_host_voice_in_ok( s->voice_mc)) 1646 1572 { 1647 1573 /* Was not able initialize *any* voice. Select the NULL audio driver instead */ 1648 AUD_close_in (&s->card, s->voice_pi);1649 AUD_close_out 1650 AUD_close_in (&s->card, s->voice_mc);1574 AUD_close_in( &s->card, s->voice_pi); 1575 AUD_close_out(&s->card, s->voice_po); 1576 AUD_close_in( &s->card, s->voice_mc); 1651 1577 s->voice_po = NULL; 1652 1578 s->voice_pi = NULL; 1653 1579 s->voice_mc = NULL; 1654 AUD_init_null 1655 ac97Reset 1656 1657 PDMDevHlpVMSetRuntimeError 1658 N_ 1659 1660 } 1661 else if ( !AUD_is_host_voice_in_ok( s->voice_pi)1580 AUD_init_null(); 1581 ac97Reset(pDevIns); 1582 1583 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding", 1584 N_("No audio devices could be opened. Selecting the NULL audio backend " 1585 "with the consequence that no sound is audible")); 1586 } 1587 else if ( !AUD_is_host_voice_in_ok( s->voice_pi) 1662 1588 || !AUD_is_host_voice_out_ok(s->voice_po) 1663 || !AUD_is_host_voice_in_ok( s->voice_mc))1589 || !AUD_is_host_voice_in_ok( s->voice_mc)) 1664 1590 { 1665 1591 char szMissingVoices[128]; 1666 1592 size_t len = 0; 1667 1593 if (!AUD_is_host_voice_in_ok(s->voice_pi)) 1668 len = RTStrPrintf 1594 len = RTStrPrintf(szMissingVoices, sizeof(szMissingVoices), "PCM_in"); 1669 1595 if (!AUD_is_host_voice_out_ok(s->voice_po)) 1670 len += RTStrPrintf 1596 len += RTStrPrintf(szMissingVoices + len, sizeof(szMissingVoices) - len, len ? ", PCM_out" : "PCM_out"); 1671 1597 if (!AUD_is_host_voice_in_ok(s->voice_mc)) 1672 len += RTStrPrintf 1673 1674 PDMDevHlpVMSetRuntimeError 1675 N_ 1676 1677 1678 1598 len += RTStrPrintf(szMissingVoices + len, sizeof(szMissingVoices) - len, len ? ", PCM_mic" : "PCM_mic"); 1599 1600 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding", 1601 N_("Some audio devices (%s) could not be opened. Guest applications generating audio " 1602 "output or depending on audio input may hang. Make sure your host audio device " 1603 "is working properly. Check the logfile for error messages of the audio " 1604 "subsystem"), szMissingVoices); 1679 1605 } 1680 1606
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