Changeset 44632 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Feb 11, 2013 12:52:40 PM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 83720
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r44631 r44632 185 185 BD bd; 186 186 } AC97BusMasterRegs; 187 188 typedef struct AC97LinkState 187 /** Pointer to a AC97 bus master register. */ 188 typedef AC97BusMasterRegs *PAC97BMREG; 189 190 typedef struct AC97STATE 189 191 { 190 192 /** The PCI device state. */ … … 222 224 /** Base port of the I/O space region. */ 223 225 RTIOPORT IOPortBase[2]; 224 } AC97LinkState; 226 } AC97STATE; 227 /** Pointer to the AC97 device state. */ 228 typedef AC97STATE *PAC97STATE; 225 229 226 230 #define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevIns) 227 #define PCIDEV_2_ICHAC97STATE(a_pPciDev) ((AC97LinkState *)(a_pPciDev))228 231 229 232 enum … … 269 272 static void mc_callback(void *opaque, int avail); 270 273 271 static void warm_reset( AC97LinkState *s)272 { 273 NOREF( s);274 } 275 276 static void cold_reset( AC97LinkState *s)277 { 278 NOREF( s);274 static void warm_reset(PAC97STATE pThis) 275 { 276 NOREF(pThis); 277 } 278 279 static void cold_reset(PAC97STATE pThis) 280 { 281 NOREF(pThis); 279 282 } 280 283 281 284 /** Fetch Buffer Descriptor at _CIV */ 282 static void fetch_bd( AC97LinkState *s, AC97BusMasterRegs *r)283 { 284 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS( s);285 static void fetch_bd(PAC97STATE pThis, PAC97BMREG pReg) 286 { 287 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis); 285 288 uint8_t b[8]; 286 289 287 PDMDevHlpPhysRead(pDevIns, r->bdbar + r->civ * 8, b, sizeof(b));288 r->bd_valid = 1;290 PDMDevHlpPhysRead(pDevIns, pReg->bdbar + pReg->civ * 8, b, sizeof(b)); 291 pReg->bd_valid = 1; 289 292 #if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64) 290 293 # error Please adapt the code (audio buffers are little endian)! 291 294 #else 292 r->bd.addr = (*(uint32_t *) &b[0]) & ~3;293 r->bd.ctl_len = (*(uint32_t *) &b[4]);295 pReg->bd.addr = (*(uint32_t *) &b[0]) & ~3; 296 pReg->bd.ctl_len = (*(uint32_t *) &b[4]); 294 297 #endif 295 r->picb = r->bd.ctl_len & 0xffff;298 pReg->picb = pReg->bd.ctl_len & 0xffff; 296 299 Log(("ac97: bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 297 r->civ, r->bd.addr, r->bd.ctl_len >> 16,298 r->bd.ctl_len & 0xffff, (r->bd.ctl_len & 0xffff) << 1));300 pReg->civ, pReg->bd.addr, pReg->bd.ctl_len >> 16, 301 pReg->bd.ctl_len & 0xffff, (pReg->bd.ctl_len & 0xffff) << 1)); 299 302 } 300 303 … … 302 305 * Update the BM status register 303 306 */ 304 static void update_sr( AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)305 { 306 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS( s);307 static void update_sr(PAC97STATE pThis, PAC97BMREG pReg, uint32_t new_sr) 308 { 309 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis); 307 310 int event = 0; 308 311 int level = 0; 309 312 uint32_t new_mask = new_sr & SR_INT_MASK; 310 uint32_t old_mask = r->sr & SR_INT_MASK;313 uint32_t old_mask = pReg->sr & SR_INT_MASK; 311 314 static uint32_t const masks[] = { GS_PIINT, GS_POINT, GS_MINT }; 312 315 … … 319 322 level = 0; 320 323 } 321 else if ((new_mask & SR_LVBCI) && ( r->cr & CR_LVBIE))324 else if ((new_mask & SR_LVBCI) && (pReg->cr & CR_LVBIE)) 322 325 { 323 326 event = 1; 324 327 level = 1; 325 328 } 326 else if ((new_mask & SR_BCIS) && ( r->cr & CR_IOCE))329 else if ((new_mask & SR_BCIS) && (pReg->cr & CR_IOCE)) 327 330 { 328 331 event = 1; … … 331 334 } 332 335 333 r->sr = new_sr;336 pReg->sr = new_sr; 334 337 335 338 Log(("ac97: IOC%d LVB%d sr=%#x event=%d level=%d\n", 336 r->sr & SR_BCIS, r->sr & SR_LVBCI, r->sr, event, level));339 pReg->sr & SR_BCIS, pReg->sr & SR_LVBCI, pReg->sr, event, level)); 337 340 338 341 if (event) 339 342 { 340 343 if (level) 341 s->glob_sta |= masks[r -s->bm_regs];344 pThis->glob_sta |= masks[pReg - pThis->bm_regs]; 342 345 else 343 s->glob_sta &= ~masks[r -s->bm_regs];346 pThis->glob_sta &= ~masks[pReg - pThis->bm_regs]; 344 347 345 348 Log(("ac97: set irq level=%d\n", !!level)); … … 348 351 } 349 352 350 static void voice_set_active( AC97LinkState *s, int bm_index, int on)353 static void voice_set_active(PAC97STATE pThis, int bm_index, int on) 351 354 { 352 355 switch (bm_index) 353 356 { 354 case PI_INDEX: AUD_set_active_in( s->voice_pi, on); break;355 case PO_INDEX: AUD_set_active_out( s->voice_po, on); break;356 case MC_INDEX: AUD_set_active_in( s->voice_mc, on); break;357 case PI_INDEX: AUD_set_active_in( pThis->voice_pi, on); break; 358 case PO_INDEX: AUD_set_active_out(pThis->voice_po, on); break; 359 case MC_INDEX: AUD_set_active_in( pThis->voice_mc, on); break; 357 360 default: AssertFailed (); break; 358 361 } 359 362 } 360 363 361 static void reset_bm_regs( AC97LinkState *s, AC97BusMasterRegs *r)364 static void reset_bm_regs(PAC97STATE pThis, PAC97BMREG pReg) 362 365 { 363 366 Log(("ac97: reset_bm_regs\n")); 364 r->bdbar = 0;365 r->civ = 0;366 r->lvi = 0;367 pReg->bdbar = 0; 368 pReg->civ = 0; 369 pReg->lvi = 0; 367 370 /** @todo do we need to do that? */ 368 update_sr( s, r, SR_DCH);369 r->picb = 0;370 r->piv = 0;371 r->cr = r->cr & CR_DONT_CLEAR_MASK;372 r->bd_valid = 0;373 374 voice_set_active( s, r -s->bm_regs, 0);375 memset( s->silence, 0, sizeof(s->silence));376 } 377 378 static void mixer_store( AC97LinkState *s, uint32_t i, uint16_t v)379 { 380 if (i + 2 > sizeof( s->mixer_data))381 { 382 Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof( s->mixer_data)));371 update_sr(pThis, pReg, SR_DCH); 372 pReg->picb = 0; 373 pReg->piv = 0; 374 pReg->cr = pReg->cr & CR_DONT_CLEAR_MASK; 375 pReg->bd_valid = 0; 376 377 voice_set_active(pThis, pReg - pThis->bm_regs, 0); 378 memset(pThis->silence, 0, sizeof(pThis->silence)); 379 } 380 381 static void mixer_store(PAC97STATE pThis, uint32_t i, uint16_t v) 382 { 383 if (i + 2 > sizeof(pThis->mixer_data)) 384 { 385 Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof(pThis->mixer_data))); 383 386 return; 384 387 } 385 388 386 s->mixer_data[i + 0] = v & 0xff;387 s->mixer_data[i + 1] = v >> 8;388 } 389 390 static uint16_t mixer_load( AC97LinkState *s, uint32_t i)389 pThis->mixer_data[i + 0] = v & 0xff; 390 pThis->mixer_data[i + 1] = v >> 8; 391 } 392 393 static uint16_t mixer_load(PAC97STATE pThis, uint32_t i) 391 394 { 392 395 uint16_t val; 393 396 394 if (i + 2 > sizeof( s->mixer_data))395 { 396 Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof( s->mixer_data)));397 if (i + 2 > sizeof(pThis->mixer_data)) 398 { 399 Log(("ac97: mixer_store: index %d out of bounds %d\n", i, sizeof(pThis->mixer_data))); 397 400 val = 0xffff; 398 401 } 399 402 else 400 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);403 val = pThis->mixer_data[i + 0] | (pThis->mixer_data[i + 1] << 8); 401 404 402 405 return val; 403 406 } 404 407 405 static void open_voice( AC97LinkState *s, int index, int freq)408 static void open_voice(PAC97STATE pThis, int index, int freq) 406 409 { 407 410 audsettings_t as; … … 417 420 { 418 421 case PI_INDEX: /* PCM in */ 419 s->voice_pi = AUD_open_in(&s->card, s->voice_pi, "ac97.pi",s, pi_callback, &as);422 pThis->voice_pi = AUD_open_in(&pThis->card, pThis->voice_pi, "ac97.pi", pThis, pi_callback, &as); 420 423 #ifdef LOG_VOICES 421 LogRel(("AC97: open PI freq=%d (%s)\n", freq, s->voice_pi ? "ok" : "FAIL"));424 LogRel(("AC97: open PI freq=%d (%s)\n", freq, pThis->voice_pi ? "ok" : "FAIL")); 422 425 #endif 423 426 break; 424 427 425 428 case PO_INDEX: /* PCM out */ 426 s->voice_po = AUD_open_out(&s->card, s->voice_po, "ac97.po",s, po_callback, &as);429 pThis->voice_po = AUD_open_out(&pThis->card, pThis->voice_po, "ac97.po", pThis, po_callback, &as); 427 430 #ifdef LOG_VOICES 428 LogRel(("AC97: open PO freq=%d (%s)\n", freq, s->voice_po ? "ok" : "FAIL"));431 LogRel(("AC97: open PO freq=%d (%s)\n", freq, pThis->voice_po ? "ok" : "FAIL")); 429 432 #endif 430 433 break; 431 434 432 435 case MC_INDEX: /* Mic in */ 433 s->voice_mc = AUD_open_in(&s->card, s->voice_mc, "ac97.mc",s, mc_callback, &as);436 pThis->voice_mc = AUD_open_in(&pThis->card, pThis->voice_mc, "ac97.mc", pThis, mc_callback, &as); 434 437 #ifdef LOG_VOICES 435 LogRel(("AC97: open MC freq=%d (%s)\n", freq, s->voice_mc ? "ok" : "FAIL"));438 LogRel(("AC97: open MC freq=%d (%s)\n", freq, pThis->voice_mc ? "ok" : "FAIL")); 436 439 #endif 437 440 break; … … 443 446 { 444 447 case PI_INDEX: 445 AUD_close_in(& s->card,s->voice_pi);448 AUD_close_in(&pThis->card, pThis->voice_pi); 446 449 #ifdef LOG_VOICES 447 450 LogRel(("AC97: Closing PCM IN\n")); 448 451 #endif 449 s->voice_pi = NULL;452 pThis->voice_pi = NULL; 450 453 break; 451 454 452 455 case PO_INDEX: 453 AUD_close_out(& s->card,s->voice_po);456 AUD_close_out(&pThis->card, pThis->voice_po); 454 457 #ifdef LOG_VOICES 455 458 LogRel(("AC97: Closing PCM OUT\n")); 456 459 #endif 457 s->voice_po = NULL;460 pThis->voice_po = NULL; 458 461 break; 459 462 460 463 case MC_INDEX: 461 AUD_close_in(& s->card,s->voice_mc);464 AUD_close_in(&pThis->card, pThis->voice_mc); 462 465 #ifdef LOG_VOICES 463 466 LogRel(("AC97: Closing MIC IN\n")); 464 467 #endif 465 s->voice_mc = NULL;468 pThis->voice_mc = NULL; 466 469 break; 467 470 } … … 469 472 } 470 473 471 static void reset_voices( AC97LinkState *s, uint8_t active[LAST_INDEX])474 static void reset_voices(PAC97STATE pThis, uint8_t active[LAST_INDEX]) 472 475 { 473 476 uint16_t freq; 474 477 475 freq = mixer_load( s, AC97_PCM_LR_ADC_Rate);476 open_voice( s, PI_INDEX, freq);477 AUD_set_active_in( s->voice_pi, active[PI_INDEX]);478 479 freq = mixer_load( s, AC97_PCM_Front_DAC_Rate);480 open_voice( s, PO_INDEX, freq);481 AUD_set_active_out (s->voice_po, active[PO_INDEX]);482 483 freq = mixer_load( s, AC97_MIC_ADC_Rate);484 open_voice( s, MC_INDEX, freq);485 AUD_set_active_in( s->voice_mc, active[MC_INDEX]);478 freq = mixer_load(pThis, AC97_PCM_LR_ADC_Rate); 479 open_voice(pThis, PI_INDEX, freq); 480 AUD_set_active_in(pThis->voice_pi, active[PI_INDEX]); 481 482 freq = mixer_load(pThis, AC97_PCM_Front_DAC_Rate); 483 open_voice(pThis, PO_INDEX, freq); 484 AUD_set_active_out(pThis->voice_po, active[PO_INDEX]); 485 486 freq = mixer_load(pThis, AC97_MIC_ADC_Rate); 487 open_voice(pThis, MC_INDEX, freq); 488 AUD_set_active_in(pThis->voice_mc, active[MC_INDEX]); 486 489 } 487 490 488 491 #ifdef USE_MIXER 489 492 490 static void set_volume( AC97LinkState *s, int index, audmixerctl_t mt, uint32_t val)493 static void set_volume(PAC97STATE pThis, int index, audmixerctl_t mt, uint32_t val) 491 494 { 492 495 int mute = (val >> MUTE_SHIFT) & 1; … … 498 501 # ifdef SOFT_VOLUME 499 502 if (index == AC97_Master_Volume_Mute) 500 AUD_set_volume_out( s->voice_po, mute, lvol, rvol);503 AUD_set_volume_out(pThis->voice_po, mute, lvol, rvol); 501 504 else 502 505 AUD_set_volume(mt, &mute, &lvol, &rvol); … … 521 524 val |= RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8); 522 525 523 mixer_store( s, index, val);526 mixer_store(pThis, index, val); 524 527 } 525 528 … … 556 559 } 557 560 558 static void record_select( AC97LinkState *s, uint32_t val)561 static void record_select(PAC97STATE pThis, uint32_t val) 559 562 { 560 563 uint8_t rs = val & REC_MASK; … … 565 568 rs = aud_to_ac97_record_source(ars); 566 569 ls = aud_to_ac97_record_source(als); 567 mixer_store( s, AC97_Record_Select, rs | (ls << 8));570 mixer_store(pThis, AC97_Record_Select, rs | (ls << 8)); 568 571 } 569 572 570 573 #endif /* USE_MIXER */ 571 574 572 static void mixer_reset( AC97LinkState *s)575 static void mixer_reset(PAC97STATE pThis) 573 576 { 574 577 uint8_t active[LAST_INDEX]; 575 578 576 579 Log(("ac97: mixer_reset\n")); 577 memset( s->mixer_data, 0, sizeof(s->mixer_data));580 memset(pThis->mixer_data, 0, sizeof(pThis->mixer_data)); 578 581 memset(active, 0, sizeof(active)); 579 mixer_store( s, AC97_Reset , 0x0000); /* 6940 */580 mixer_store( s, AC97_Master_Volume_Mono_Mute , 0x8000);581 mixer_store( s, AC97_PC_BEEP_Volume_Mute , 0x0000);582 583 mixer_store( s, AC97_Phone_Volume_Mute , 0x8008);584 mixer_store( s, AC97_Mic_Volume_Mute , 0x8008);585 mixer_store( s, AC97_CD_Volume_Mute , 0x8808);586 mixer_store( s, AC97_Aux_Volume_Mute , 0x8808);587 mixer_store( s, AC97_Record_Gain_Mic_Mute , 0x8000);588 mixer_store( s, AC97_General_Purpose , 0x0000);589 mixer_store( s, AC97_3D_Control , 0x0000);590 mixer_store( s, AC97_Powerdown_Ctrl_Stat , 0x000f);582 mixer_store(pThis, AC97_Reset , 0x0000); /* 6940 */ 583 mixer_store(pThis, AC97_Master_Volume_Mono_Mute , 0x8000); 584 mixer_store(pThis, AC97_PC_BEEP_Volume_Mute , 0x0000); 585 586 mixer_store(pThis, AC97_Phone_Volume_Mute , 0x8008); 587 mixer_store(pThis, AC97_Mic_Volume_Mute , 0x8008); 588 mixer_store(pThis, AC97_CD_Volume_Mute , 0x8808); 589 mixer_store(pThis, AC97_Aux_Volume_Mute , 0x8808); 590 mixer_store(pThis, AC97_Record_Gain_Mic_Mute , 0x8000); 591 mixer_store(pThis, AC97_General_Purpose , 0x0000); 592 mixer_store(pThis, AC97_3D_Control , 0x0000); 593 mixer_store(pThis, AC97_Powerdown_Ctrl_Stat , 0x000f); 591 594 592 595 /* 593 596 * Sigmatel 9700 (STAC9700) 594 597 */ 595 mixer_store( s, AC97_Vendor_ID1 , 0x8384);596 mixer_store( s, AC97_Vendor_ID2 , 0x7600); /* 7608 */597 598 mixer_store( s, AC97_Extended_Audio_ID , 0x0809);599 mixer_store( s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);600 mixer_store( s, AC97_PCM_Front_DAC_Rate , 0xbb80);601 mixer_store( s, AC97_PCM_Surround_DAC_Rate , 0xbb80);602 mixer_store( s, AC97_PCM_LFE_DAC_Rate , 0xbb80);603 mixer_store( s, AC97_PCM_LR_ADC_Rate , 0xbb80);604 mixer_store( s, AC97_MIC_ADC_Rate , 0xbb80);598 mixer_store(pThis, AC97_Vendor_ID1 , 0x8384); 599 mixer_store(pThis, AC97_Vendor_ID2 , 0x7600); /* 7608 */ 600 601 mixer_store(pThis, AC97_Extended_Audio_ID , 0x0809); 602 mixer_store(pThis, AC97_Extended_Audio_Ctrl_Stat, 0x0009); 603 mixer_store(pThis, AC97_PCM_Front_DAC_Rate , 0xbb80); 604 mixer_store(pThis, AC97_PCM_Surround_DAC_Rate , 0xbb80); 605 mixer_store(pThis, AC97_PCM_LFE_DAC_Rate , 0xbb80); 606 mixer_store(pThis, AC97_PCM_LR_ADC_Rate , 0xbb80); 607 mixer_store(pThis, AC97_MIC_ADC_Rate , 0xbb80); 605 608 606 609 #ifdef USE_MIXER 607 record_select( s, 0);608 set_volume( s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME, 0x8000);609 set_volume( s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM, 0x8808);610 set_volume( s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);610 record_select(pThis, 0); 611 set_volume(pThis, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME, 0x8000); 612 set_volume(pThis, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM, 0x8808); 613 set_volume(pThis, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808); 611 614 #else 612 mixer_store( s, AC97_Record_Select, 0);613 mixer_store( s, AC97_Master_Volume_Mute, 0x8000);614 mixer_store( s, AC97_PCM_Out_Volume_Mute, 0x8808);615 mixer_store( s, AC97_Line_In_Volume_Mute, 0x8808);615 mixer_store(pThis, AC97_Record_Select, 0); 616 mixer_store(pThis, AC97_Master_Volume_Mute, 0x8000); 617 mixer_store(pThis, AC97_PCM_Out_Volume_Mute, 0x8808); 618 mixer_store(pThis, AC97_Line_In_Volume_Mute, 0x8808); 616 619 #endif 617 620 618 reset_voices( s, active);619 } 620 621 static int write_audio( AC97LinkState *s, AC97BusMasterRegs *r, int max, int *stop)622 { 623 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS( s);621 reset_voices(pThis, active); 622 } 623 624 static int write_audio(PAC97STATE pThis, PAC97BMREG pReg, int max, int *stop) 625 { 626 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis); 624 627 uint8_t tmpbuf[4096]; 625 uint32_t addr = r->bd.addr;626 uint32_t temp = r->picb << 1;628 uint32_t addr = pReg->bd.addr; 629 uint32_t temp = pReg->picb << 1; 627 630 uint32_t written = 0; 628 631 int to_copy = 0; … … 640 643 to_copy = audio_MIN(temp, sizeof(tmpbuf)); 641 644 PDMDevHlpPhysRead(pDevIns, addr, tmpbuf, to_copy); 642 copied = AUD_write( s->voice_po, tmpbuf, to_copy);645 copied = AUD_write(pThis->voice_po, tmpbuf, to_copy); 643 646 Log(("ac97: write_audio max=%x to_copy=%x copied=%x\n", max, to_copy, copied)); 644 647 if (!copied) … … 657 660 { 658 661 Log(("ac97: whoops\n")); 659 s->last_samp = 0;662 pThis->last_samp = 0; 660 663 } 661 664 else 662 s->last_samp = *(uint32_t *)&tmpbuf[to_copy - 4];663 } 664 665 r->bd.addr = addr;665 pThis->last_samp = *(uint32_t *)&tmpbuf[to_copy - 4]; 666 } 667 668 pReg->bd.addr = addr; 666 669 return written; 667 670 } 668 671 669 static void write_bup( AC97LinkState *s, int elapsed)672 static void write_bup(PAC97STATE pThis, int elapsed) 670 673 { 671 674 int written = 0; 672 675 673 676 Log(("ac97: write_bup\n")); 674 if (!( s->bup_flag & BUP_SET))675 { 676 if ( s->bup_flag & BUP_LAST)677 if (!(pThis->bup_flag & BUP_SET)) 678 { 679 if (pThis->bup_flag & BUP_LAST) 677 680 { 678 681 unsigned int i; 679 uint32_t *p = (uint32_t*) s->silence;680 for (i = 0; i < sizeof( s->silence) / 4; i++)681 *p++ = s->last_samp;682 uint32_t *p = (uint32_t*)pThis->silence; 683 for (i = 0; i < sizeof(pThis->silence) / 4; i++) 684 *p++ = pThis->last_samp; 682 685 } 683 686 else 684 memset( s->silence, 0, sizeof(s->silence));685 686 s->bup_flag |= BUP_SET;687 memset(pThis->silence, 0, sizeof(pThis->silence)); 688 689 pThis->bup_flag |= BUP_SET; 687 690 } 688 691 689 692 while (elapsed) 690 693 { 691 unsigned int temp = audio_MIN((unsigned int)elapsed, sizeof( s->silence));694 unsigned int temp = audio_MIN((unsigned int)elapsed, sizeof(pThis->silence)); 692 695 while (temp) 693 696 { 694 int copied = AUD_write( s->voice_po,s->silence, temp);697 int copied = AUD_write(pThis->voice_po, pThis->silence, temp); 695 698 if (!copied) 696 699 return; … … 702 705 } 703 706 704 static int read_audio( AC97LinkState *s, AC97BusMasterRegs *r, int max, int *stop)705 { 706 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS( s);707 static int read_audio(PAC97STATE pThis, PAC97BMREG pReg, int max, int *stop) 708 { 709 PPDMDEVINS pDevIns = ICHAC97STATE_2_DEVINS(pThis); 707 710 uint8_t tmpbuf[4096]; 708 uint32_t addr = r->bd.addr;709 uint32_t temp = r->picb << 1;711 uint32_t addr = pReg->bd.addr; 712 uint32_t temp = pReg->picb << 1; 710 713 uint32_t nread = 0; 711 714 int to_copy = 0; 712 SWVoiceIn *voice = ( r - s->bm_regs) == MC_INDEX ? s->voice_mc :s->voice_pi;715 SWVoiceIn *voice = (pReg - pThis->bm_regs) == MC_INDEX ? pThis->voice_mc : pThis->voice_pi; 713 716 714 717 temp = audio_MIN(temp, (uint32_t)max); … … 735 738 } 736 739 737 r->bd.addr = addr;740 pReg->bd.addr = addr; 738 741 return nread; 739 742 } 740 743 741 static void transfer_audio(AC97LinkState *s, int index, int elapsed) 742 { 743 AC97BusMasterRegs *r = &s->bm_regs[index]; 744 int written = 0, stop = 0; 745 746 if (r->sr & SR_DCH) 747 { 748 if (r->cr & CR_RPBM) 744 static void transfer_audio(PAC97STATE pThis, int index, int elapsed) 745 { 746 PAC97BMREG pReg = &pThis->bm_regs[index]; 747 int written = 0; 748 int stop = 0; 749 750 if (pReg->sr & SR_DCH) 751 { 752 if (pReg->cr & CR_RPBM) 749 753 { 750 754 switch (index) 751 755 { 752 756 case PO_INDEX: 753 write_bup( s, elapsed);757 write_bup(pThis, elapsed); 754 758 break; 755 759 } … … 762 766 int temp; 763 767 764 if (! r->bd_valid)768 if (!pReg->bd_valid) 765 769 { 766 770 Log(("ac97: invalid bd\n")); 767 fetch_bd( s, r);768 } 769 770 if (! r->picb)771 { 772 Log(("ac97: fresh bd %d is empty %#x %#x, skipping\n", r->civ, r->bd.addr, r->bd.ctl_len));773 if ( r->civ == r->lvi)771 fetch_bd(pThis, pReg); 772 } 773 774 if (!pReg->picb) 775 { 776 Log(("ac97: fresh bd %d is empty %#x %#x, skipping\n", pReg->civ, pReg->bd.addr, pReg->bd.ctl_len)); 777 if (pReg->civ == pReg->lvi) 774 778 { 775 r->sr |= SR_DCH; /* CELV? */776 s->bup_flag = 0;779 pReg->sr |= SR_DCH; /* CELV? */ 780 pThis->bup_flag = 0; 777 781 break; 778 782 } 779 r->sr &= ~SR_CELV;780 r->civ = r->piv;781 r->piv = (r->piv + 1) % 32;782 fetch_bd( s, r);783 pReg->sr &= ~SR_CELV; 784 pReg->civ = pReg->piv; 785 pReg->piv = (pReg->piv + 1) % 32; 786 fetch_bd(pThis, pReg); 783 787 continue; 784 788 } … … 787 791 { 788 792 case PO_INDEX: 789 temp = write_audio( s, r, elapsed, &stop);793 temp = write_audio(pThis, pReg, elapsed, &stop); 790 794 written += temp; 791 795 elapsed -= temp; 792 796 Assert((temp & 1) == 0); /* Else the following shift won't work */ 793 r->picb -= (temp >> 1);797 pReg->picb -= (temp >> 1); 794 798 break; 795 799 796 800 case PI_INDEX: 797 801 case MC_INDEX: 798 temp = read_audio( s, r, elapsed, &stop);802 temp = read_audio(pThis, pReg, elapsed, &stop); 799 803 elapsed -= temp; 800 804 Assert((temp & 1) == 0); /* Else the following shift won't work */ 801 r->picb -= (temp >> 1);805 pReg->picb -= (temp >> 1); 802 806 break; 803 807 } 804 808 805 Log((" r->picb = %d\n", r->picb));806 807 if (! r->picb)808 { 809 uint32_t new_sr = r->sr & ~SR_CELV;810 811 if ( r->bd.ctl_len & BD_IOC)809 Log(("pReg->picb = %d\n", pReg->picb)); 810 811 if (!pReg->picb) 812 { 813 uint32_t new_sr = pReg->sr & ~SR_CELV; 814 815 if (pReg->bd.ctl_len & BD_IOC) 812 816 new_sr |= SR_BCIS; 813 817 814 if ( r->civ == r->lvi)818 if (pReg->civ == pReg->lvi) 815 819 { 816 Log(("ac97: Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi));820 Log(("ac97: Underrun civ (%d) == lvi (%d)\n", pReg->civ, pReg->lvi)); 817 821 new_sr |= SR_LVBCI | SR_DCH | SR_CELV; 818 822 stop = 1; 819 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;823 pThis->bup_flag = (pReg->bd.ctl_len & BD_BUP) ? BUP_LAST : 0; 820 824 } 821 825 else 822 826 { 823 r->civ = r->piv;824 r->piv = (r->piv + 1) % 32;825 fetch_bd (s, r);827 pReg->civ = pReg->piv; 828 pReg->piv = (pReg->piv + 1) % 32; 829 fetch_bd(pThis, pReg); 826 830 } 827 update_sr( s, r, new_sr);831 update_sr(pThis, pReg, new_sr); 828 832 } 829 833 } … … 832 836 static void pi_callback(void *opaque, int avail) 833 837 { 834 transfer_audio((AC97 LinkState*)opaque, PI_INDEX, avail);838 transfer_audio((AC97STATE *)opaque, PI_INDEX, avail); 835 839 } 836 840 837 841 static void mc_callback(void *opaque, int avail) 838 842 { 839 transfer_audio((AC97 LinkState*)opaque, MC_INDEX, avail);843 transfer_audio((AC97STATE *)opaque, MC_INDEX, avail); 840 844 } 841 845 842 846 static void po_callback(void *opaque, int free) 843 847 { 844 transfer_audio((AC97 LinkState*)opaque, PO_INDEX, free);848 transfer_audio((AC97STATE *)opaque, PO_INDEX, free); 845 849 } 846 850 … … 850 854 static DECLCALLBACK(int) ichac97IOPortNABMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 851 855 { 852 AC97LinkState *d = (AC97LinkState *)pvUser; 853 AC97LinkState *s = d; 856 PAC97STATE pThis = (PAC97STATE)pvUser; 854 857 855 858 switch (cb) … … 857 860 case 1: 858 861 { 859 AC97BusMasterRegs *r= NULL;860 uint32_t index = Port - s->IOPortBase[1];862 PAC97BMREG pReg = NULL; 863 uint32_t index = Port - pThis->IOPortBase[1]; 861 864 *pu32 = ~0U; 862 865 … … 865 868 case CAS: 866 869 /* Codec Access Semaphore Register */ 867 Log(("ac97: CAS %d\n", s->cas));868 *pu32 = s->cas;869 s->cas = 1;870 Log(("ac97: CAS %d\n", pThis->cas)); 871 *pu32 = pThis->cas; 872 pThis->cas = 1; 870 873 break; 871 874 case PI_CIV: … … 873 876 case MC_CIV: 874 877 /* Current Index Value Register */ 875 r = &s->bm_regs[GET_BM(index)];876 *pu32 = r->civ;878 pReg = &pThis->bm_regs[GET_BM(index)]; 879 *pu32 = pReg->civ; 877 880 Log(("ac97: CIV[%d] -> %#x\n", GET_BM(index), *pu32)); 878 881 break; … … 881 884 case MC_LVI: 882 885 /* Last Valid Index Register */ 883 r = &s->bm_regs[GET_BM(index)];884 *pu32 = r->lvi;886 pReg = &pThis->bm_regs[GET_BM(index)]; 887 *pu32 = pReg->lvi; 885 888 Log(("ac97: LVI[%d] -> %#x\n", GET_BM(index), *pu32)); 886 889 break; … … 889 892 case MC_PIV: 890 893 /* Prefetched Index Value Register */ 891 r = &s->bm_regs[GET_BM(index)];892 *pu32 = r->piv;894 pReg = &pThis->bm_regs[GET_BM(index)]; 895 *pu32 = pReg->piv; 893 896 Log(("ac97: PIV[%d] -> %#x\n", GET_BM(index), *pu32)); 894 897 break; … … 897 900 case MC_CR: 898 901 /* Control Register */ 899 r = &s->bm_regs[GET_BM(index)];900 *pu32 = r->cr;902 pReg = &pThis->bm_regs[GET_BM(index)]; 903 *pu32 = pReg->cr; 901 904 Log(("ac97: CR[%d] -> %#x\n", GET_BM(index), *pu32)); 902 905 break; … … 905 908 case MC_SR: 906 909 /* Status Register (lower part) */ 907 r = &s->bm_regs[GET_BM(index)];908 *pu32 = r->sr & 0xff;910 pReg = &pThis->bm_regs[GET_BM(index)]; 911 *pu32 = pReg->sr & 0xff; 909 912 Log(("ac97: SRb[%d] -> %#x\n", GET_BM(index), *pu32)); 910 913 break; … … 918 921 case 2: 919 922 { 920 AC97BusMasterRegs *r= NULL;921 uint32_t index = Port - s->IOPortBase[1];923 PAC97BMREG pReg = NULL; 924 uint32_t index = Port - pThis->IOPortBase[1]; 922 925 *pu32 = ~0U; 923 926 … … 928 931 case MC_SR: 929 932 /* Status Register */ 930 r = &s->bm_regs[GET_BM(index)];931 *pu32 = r->sr;933 pReg = &pThis->bm_regs[GET_BM(index)]; 934 *pu32 = pReg->sr; 932 935 Log(("ac97: SR[%d] -> %#x\n", GET_BM(index), *pu32)); 933 936 break; … … 936 939 case MC_PICB: 937 940 /* Position in Current Buffer Register */ 938 r = &s->bm_regs[GET_BM(index)];939 *pu32 = r->picb;941 pReg = &pThis->bm_regs[GET_BM(index)]; 942 *pu32 = pReg->picb; 940 943 Log(("ac97: PICB[%d] -> %#x\n", GET_BM(index), *pu32)); 941 944 break; … … 949 952 case 4: 950 953 { 951 AC97BusMasterRegs *r= NULL;952 uint32_t index = Port - s->IOPortBase[1];954 PAC97BMREG pReg = NULL; 955 uint32_t index = Port - pThis->IOPortBase[1]; 953 956 *pu32 = ~0U; 954 957 … … 959 962 case MC_BDBAR: 960 963 /* Buffer Descriptor Base Address Register */ 961 r = &s->bm_regs[GET_BM(index)];962 *pu32 = r->bdbar;964 pReg = &pThis->bm_regs[GET_BM(index)]; 965 *pu32 = pReg->bdbar; 963 966 Log(("ac97: BMADDR[%d] -> %#x\n", GET_BM(index), *pu32)); 964 967 break; … … 969 972 * Last Valid Index Register + 970 973 * Status Register */ 971 r = &s->bm_regs[GET_BM(index)];972 *pu32 = r->civ | (r->lvi << 8) | (r->sr << 16);973 Log(("ac97: CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM(index), r->civ, r->lvi, r->sr));974 pReg = &pThis->bm_regs[GET_BM(index)]; 975 *pu32 = pReg->civ | (pReg->lvi << 8) | (pReg->sr << 16); 976 Log(("ac97: CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM(index), pReg->civ, pReg->lvi, pReg->sr)); 974 977 break; 975 978 case PI_PICB: … … 979 982 * Prefetched Index Value Register + 980 983 * Control Register */ 981 r = &s->bm_regs[GET_BM(index)];982 *pu32 = r->picb | (r->piv << 16) | (r->cr << 24);983 Log(("ac97: PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM(index), *pu32, r->picb, r->piv, r->cr));984 pReg = &pThis->bm_regs[GET_BM(index)]; 985 *pu32 = pReg->picb | (pReg->piv << 16) | (pReg->cr << 24); 986 Log(("ac97: PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM(index), *pu32, pReg->picb, pReg->piv, pReg->cr)); 984 987 break; 985 988 case GLOB_CNT: 986 989 /* Global Control */ 987 *pu32 = s->glob_cnt;990 *pu32 = pThis->glob_cnt; 988 991 Log(("ac97: glob_cnt -> %#x\n", *pu32)); 989 992 break; 990 993 case GLOB_STA: 991 994 /* Global Status */ 992 *pu32 = s->glob_sta | GS_S0CR;995 *pu32 = pThis->glob_sta | GS_S0CR; 993 996 Log(("ac97: glob_sta -> %#x\n", *pu32)); 994 997 break; … … 1011 1014 static DECLCALLBACK(int) ichac97IOPortNABMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1012 1015 { 1013 AC97LinkState *d = (AC97LinkState *)pvUser; 1014 AC97LinkState *s = d; 1016 PAC97STATE pThis = (PAC97STATE)pvUser; 1015 1017 1016 1018 switch (cb) … … 1018 1020 case 1: 1019 1021 { 1020 AC97BusMasterRegs *r= NULL;1021 uint32_t index = Port - s->IOPortBase[1];1022 PAC97BMREG pReg = NULL; 1023 uint32_t index = Port - pThis->IOPortBase[1]; 1022 1024 switch (index) 1023 1025 { … … 1026 1028 case MC_LVI: 1027 1029 /* Last Valid Index */ 1028 r = &s->bm_regs[GET_BM(index)];1029 if (( r->cr & CR_RPBM) && (r->sr & SR_DCH))1030 pReg = &pThis->bm_regs[GET_BM(index)]; 1031 if ((pReg->cr & CR_RPBM) && (pReg->sr & SR_DCH)) 1030 1032 { 1031 r->sr &= ~(SR_DCH | SR_CELV);1032 r->civ = r->piv;1033 r->piv = (r->piv + 1) % 32;1034 fetch_bd (s, r);1033 pReg->sr &= ~(SR_DCH | SR_CELV); 1034 pReg->civ = pReg->piv; 1035 pReg->piv = (pReg->piv + 1) % 32; 1036 fetch_bd(pThis, pReg); 1035 1037 } 1036 r->lvi = u32 % 32;1038 pReg->lvi = u32 % 32; 1037 1039 Log(("ac97: LVI[%d] <- %#x\n", GET_BM(index), u32)); 1038 1040 break; … … 1041 1043 case MC_CR: 1042 1044 /* Control Register */ 1043 r = &s->bm_regs[GET_BM(index)];1045 pReg = &pThis->bm_regs[GET_BM(index)]; 1044 1046 if (u32 & CR_RR) 1045 reset_bm_regs( s, r);1047 reset_bm_regs(pThis, pReg); 1046 1048 else 1047 1049 { 1048 r->cr = u32 & CR_VALID_MASK;1049 if (!( r->cr & CR_RPBM))1050 pReg->cr = u32 & CR_VALID_MASK; 1051 if (!(pReg->cr & CR_RPBM)) 1050 1052 { 1051 voice_set_active( s, r -s->bm_regs, 0);1052 r->sr |= SR_DCH;1053 voice_set_active(pThis, pReg - pThis->bm_regs, 0); 1054 pReg->sr |= SR_DCH; 1053 1055 } 1054 1056 else 1055 1057 { 1056 r->civ = r->piv;1057 r->piv = (r->piv + 1) % 32;1058 fetch_bd( s, r);1059 r->sr &= ~SR_DCH;1060 voice_set_active( s, r -s->bm_regs, 1);1058 pReg->civ = pReg->piv; 1059 pReg->piv = (pReg->piv + 1) % 32; 1060 fetch_bd(pThis, pReg); 1061 pReg->sr &= ~SR_DCH; 1062 voice_set_active(pThis, pReg - pThis->bm_regs, 1); 1061 1063 } 1062 1064 } 1063 Log(("ac97: CR[%d] <- %#x (cr %#x)\n", GET_BM(index), u32, r->cr));1065 Log(("ac97: CR[%d] <- %#x (cr %#x)\n", GET_BM(index), u32, pReg->cr)); 1064 1066 break; 1065 1067 case PI_SR: … … 1067 1069 case MC_SR: 1068 1070 /* Status Register */ 1069 r = &s->bm_regs[GET_BM(index)];1070 r->sr |= u32 & ~(SR_RO_MASK | SR_WCLEAR_MASK);1071 update_sr( s, r, r->sr & ~(u32 & SR_WCLEAR_MASK));1072 Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, r->sr));1071 pReg = &pThis->bm_regs[GET_BM(index)]; 1072 pReg->sr |= u32 & ~(SR_RO_MASK | SR_WCLEAR_MASK); 1073 update_sr(pThis, pReg, pReg->sr & ~(u32 & SR_WCLEAR_MASK)); 1074 Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, pReg->sr)); 1073 1075 break; 1074 1076 default: … … 1081 1083 case 2: 1082 1084 { 1083 AC97BusMasterRegs *r= NULL;1084 uint32_t index = Port - s->IOPortBase[1];1085 PAC97BMREG pReg = NULL; 1086 uint32_t index = Port - pThis->IOPortBase[1]; 1085 1087 switch (index) 1086 1088 { … … 1089 1091 case MC_SR: 1090 1092 /* Status Register */ 1091 r = &s->bm_regs[GET_BM(index)];1092 r->sr |= u32 & ~(SR_RO_MASK | SR_WCLEAR_MASK);1093 update_sr( s, r, r->sr & ~(u32 & SR_WCLEAR_MASK));1094 Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, r->sr));1093 pReg = &pThis->bm_regs[GET_BM(index)]; 1094 pReg->sr |= u32 & ~(SR_RO_MASK | SR_WCLEAR_MASK); 1095 update_sr(pThis, pReg, pReg->sr & ~(u32 & SR_WCLEAR_MASK)); 1096 Log(("ac97: SR[%d] <- %#x (sr %#x)\n", GET_BM(index), u32, pReg->sr)); 1095 1097 break; 1096 1098 default: … … 1103 1105 case 4: 1104 1106 { 1105 AC97BusMasterRegs *r= NULL;1106 uint32_t index = Port - s->IOPortBase[1];1107 PAC97BMREG pReg = NULL; 1108 uint32_t index = Port - pThis->IOPortBase[1]; 1107 1109 switch (index) 1108 1110 { … … 1111 1113 case MC_BDBAR: 1112 1114 /* Buffer Descriptor list Base Address Register */ 1113 r = &s->bm_regs[GET_BM(index)];1114 r->bdbar = u32 & ~3;1115 Log(("ac97: BDBAR[%d] <- %#x (bdbar %#x)\n", GET_BM(index), u32, r->bdbar));1115 pReg = &pThis->bm_regs[GET_BM(index)]; 1116 pReg->bdbar = u32 & ~3; 1117 Log(("ac97: BDBAR[%d] <- %#x (bdbar %#x)\n", GET_BM(index), u32, pReg->bdbar)); 1116 1118 break; 1117 1119 case GLOB_CNT: 1118 1120 /* Global Control */ 1119 1121 if (u32 & GC_WR) 1120 warm_reset (s);1122 warm_reset(pThis); 1121 1123 if (u32 & GC_CR) 1122 cold_reset (s);1124 cold_reset(pThis); 1123 1125 if (!(u32 & (GC_WR | GC_CR))) 1124 s->glob_cnt = u32 & GC_VALID_MASK;1125 Log(("ac97: glob_cnt <- %#x (glob_cnt %#x)\n", u32, s->glob_cnt));1126 pThis->glob_cnt = u32 & GC_VALID_MASK; 1127 Log(("ac97: glob_cnt <- %#x (glob_cnt %#x)\n", u32, pThis->glob_cnt)); 1126 1128 break; 1127 1129 case GLOB_STA: 1128 1130 /* Global Status */ 1129 s->glob_sta &= ~(u32 & GS_WCLEAR_MASK);1130 s->glob_sta |= (u32 & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;1131 Log(("ac97: glob_sta <- %#x (glob_sta %#x)\n", u32, s->glob_sta));1131 pThis->glob_sta &= ~(u32 & GS_WCLEAR_MASK); 1132 pThis->glob_sta |= (u32 & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK; 1133 Log(("ac97: glob_sta <- %#x (glob_sta %#x)\n", u32, pThis->glob_sta)); 1132 1134 break; 1133 1135 default: … … 1150 1152 static DECLCALLBACK(int) ichac97IOPortNAMRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) 1151 1153 { 1152 AC97LinkState *d = (AC97LinkState *)pvUser; 1153 AC97LinkState *s = d; 1154 PAC97STATE pThis = (PAC97STATE)pvUser; 1154 1155 1155 1156 switch (cb) … … 1158 1159 { 1159 1160 Log(("ac97: U nam readb %#x\n", Port)); 1160 s->cas = 0;1161 pThis->cas = 0; 1161 1162 *pu32 = ~0U; 1162 1163 break; … … 1165 1166 case 2: 1166 1167 { 1167 uint32_t index = Port - s->IOPortBase[0];1168 uint32_t index = Port - pThis->IOPortBase[0]; 1168 1169 *pu32 = ~0U; 1169 s->cas = 0;1170 pThis->cas = 0; 1170 1171 switch (index) 1171 1172 { 1172 1173 default: 1173 *pu32 = mixer_load( s, index);1174 *pu32 = mixer_load(pThis, index); 1174 1175 Log(("ac97: nam readw %#x -> %#x\n", Port, *pu32)); 1175 1176 break; … … 1181 1182 { 1182 1183 Log(("ac97: U nam readl %#x\n", Port)); 1183 s->cas = 0;1184 pThis->cas = 0; 1184 1185 *pu32 = ~0U; 1185 1186 break; … … 1197 1198 static DECLCALLBACK(int) ichac97IOPortNAMWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) 1198 1199 { 1199 AC97LinkState *d = (AC97LinkState *)pvUser; 1200 AC97LinkState *s = d; 1200 PAC97STATE pThis = (PAC97STATE)pvUser; 1201 1201 1202 1202 switch (cb) … … 1205 1205 { 1206 1206 Log(("ac97: U nam writeb %#x <- %#x\n", Port, u32)); 1207 s->cas = 0;1207 pThis->cas = 0; 1208 1208 break; 1209 1209 } … … 1211 1211 case 2: 1212 1212 { 1213 uint32_t index = Port - s->IOPortBase[0];1214 s->cas = 0;1213 uint32_t index = Port - pThis->IOPortBase[0]; 1214 pThis->cas = 0; 1215 1215 switch (index) 1216 1216 { 1217 1217 case AC97_Reset: 1218 mixer_reset( s);1218 mixer_reset(pThis); 1219 1219 break; 1220 1220 case AC97_Powerdown_Ctrl_Stat: 1221 1221 u32 &= ~0xf; 1222 u32 |= mixer_load( s, index) & 0xf;1223 mixer_store( s, index, u32);1222 u32 |= mixer_load(pThis, index) & 0xf; 1223 mixer_store(pThis, index, u32); 1224 1224 break; 1225 1225 #ifdef USE_MIXER 1226 1226 case AC97_Master_Volume_Mute: 1227 set_volume( s, index, AUD_MIXER_VOLUME, u32);1227 set_volume(pThis, index, AUD_MIXER_VOLUME, u32); 1228 1228 break; 1229 1229 case AC97_PCM_Out_Volume_Mute: 1230 set_volume( s, index, AUD_MIXER_PCM, u32);1230 set_volume(pThis, index, AUD_MIXER_PCM, u32); 1231 1231 break; 1232 1232 case AC97_Line_In_Volume_Mute: 1233 set_volume( s, index, AUD_MIXER_LINE_IN, u32);1233 set_volume(pThis, index, AUD_MIXER_LINE_IN, u32); 1234 1234 break; 1235 1235 case AC97_Record_Select: 1236 record_select( s, u32);1236 record_select(pThis, u32); 1237 1237 break; 1238 1238 #else /* !USE_MIXER */ … … 1241 1241 case AC97_Line_In_Volume_Mute: 1242 1242 case AC97_Record_Select: 1243 mixer_store( s, index, u32);1243 mixer_store(pThis, index, u32); 1244 1244 break; 1245 1245 #endif /* !USE_MIXER */ … … 1254 1254 if (!(u32 & EACS_VRA)) 1255 1255 { 1256 mixer_store( s, AC97_PCM_Front_DAC_Rate, 0xbb80);1257 mixer_store( s, AC97_PCM_LR_ADC_Rate, 0xbb80);1258 open_voice( s, PI_INDEX, 48000);1259 open_voice( s, PO_INDEX, 48000);1256 mixer_store(pThis, AC97_PCM_Front_DAC_Rate, 0xbb80); 1257 mixer_store(pThis, AC97_PCM_LR_ADC_Rate, 0xbb80); 1258 open_voice(pThis, PI_INDEX, 48000); 1259 open_voice(pThis, PO_INDEX, 48000); 1260 1260 } 1261 1261 if (!(u32 & EACS_VRM)) 1262 1262 { 1263 mixer_store( s, AC97_MIC_ADC_Rate, 0xbb80);1264 open_voice( s, MC_INDEX, 48000);1263 mixer_store(pThis, AC97_MIC_ADC_Rate, 0xbb80); 1264 open_voice(pThis, MC_INDEX, 48000); 1265 1265 } 1266 1266 Log(("ac97: Setting extended audio control to %#x\n", u32)); 1267 mixer_store( s, AC97_Extended_Audio_Ctrl_Stat, u32);1267 mixer_store(pThis, AC97_Extended_Audio_Ctrl_Stat, u32); 1268 1268 break; 1269 1269 case AC97_PCM_Front_DAC_Rate: 1270 if (mixer_load( s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)1270 if (mixer_load(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) 1271 1271 { 1272 mixer_store( s, index, u32);1272 mixer_store(pThis, index, u32); 1273 1273 Log(("ac97: Set front DAC rate to %d\n", u32)); 1274 open_voice( s, PO_INDEX, u32);1274 open_voice(pThis, PO_INDEX, u32); 1275 1275 } 1276 1276 else … … 1278 1278 break; 1279 1279 case AC97_MIC_ADC_Rate: 1280 if (mixer_load( s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)1280 if (mixer_load(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) 1281 1281 { 1282 mixer_store( s, index, u32);1282 mixer_store(pThis, index, u32); 1283 1283 Log(("ac97: Set MIC ADC rate to %d\n", u32)); 1284 open_voice( s, MC_INDEX, u32);1284 open_voice(pThis, MC_INDEX, u32); 1285 1285 } 1286 1286 else … … 1288 1288 break; 1289 1289 case AC97_PCM_LR_ADC_Rate: 1290 if (mixer_load( s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)1290 if (mixer_load(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) 1291 1291 { 1292 mixer_store( s, index, u32);1292 mixer_store(pThis, index, u32); 1293 1293 Log(("ac97: Set front LR ADC rate to %d\n", u32)); 1294 open_voice( s, PI_INDEX, u32);1294 open_voice(pThis, PI_INDEX, u32); 1295 1295 } 1296 1296 else … … 1299 1299 default: 1300 1300 Log(("ac97: U nam writew %#x <- %#x\n", Port, u32)); 1301 mixer_store( s, index, u32);1301 mixer_store(pThis, index, u32); 1302 1302 break; 1303 1303 } … … 1308 1308 { 1309 1309 Log(("ac97: U nam writel %#x <- %#x\n", Port, u32)); 1310 s->cas = 0;1310 pThis->cas = 0; 1311 1311 break; 1312 1312 } … … 1326 1326 PCIADDRESSSPACE enmType) 1327 1327 { 1328 PPDMDEVINS 1329 AC97LinkState *pThis = PCIDEV_2_ICHAC97STATE(pPciDev);1330 RTIOPORT 1331 int 1328 PPDMDEVINS pDevIns = pPciDev->pDevIns; 1329 PAC97STATE pThis = RT_FROM_MEMBER(pPciDev, AC97STATE, PciDev); 1330 RTIOPORT Port = (RTIOPORT)GCPhysAddress; 1331 int rc; 1332 1332 1333 1333 Assert(enmType == PCI_ADDRESS_SPACE_IO); … … 1355 1355 static DECLCALLBACK(int) ichac97SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) 1356 1356 { 1357 AC97LinkState *pThis = PDMINS_2_DATA(pDevIns, AC97LinkState *); 1358 AC97LinkState *s = pThis; 1359 1360 SSMR3PutU32(pSSM, s->glob_cnt); 1361 SSMR3PutU32(pSSM, s->glob_sta); 1362 SSMR3PutU32(pSSM, s->cas); 1363 1364 for (unsigned i = 0; i < RT_ELEMENTS(s->bm_regs); i++) 1365 { 1366 AC97BusMasterRegs *r = &s->bm_regs[i]; 1367 SSMR3PutU32(pSSM, r->bdbar); 1368 SSMR3PutU8( pSSM, r->civ); 1369 SSMR3PutU8( pSSM, r->lvi); 1370 SSMR3PutU16(pSSM, r->sr); 1371 SSMR3PutU16(pSSM, r->picb); 1372 SSMR3PutU8( pSSM, r->piv); 1373 SSMR3PutU8( pSSM, r->cr); 1374 SSMR3PutS32(pSSM, r->bd_valid); 1375 SSMR3PutU32(pSSM, r->bd.addr); 1376 SSMR3PutU32(pSSM, r->bd.ctl_len); 1377 } 1378 SSMR3PutMem(pSSM, s->mixer_data, sizeof(s->mixer_data)); 1357 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE *); 1358 1359 SSMR3PutU32(pSSM, pThis->glob_cnt); 1360 SSMR3PutU32(pSSM, pThis->glob_sta); 1361 SSMR3PutU32(pSSM, pThis->cas); 1362 1363 for (unsigned i = 0; i < RT_ELEMENTS(pThis->bm_regs); i++) 1364 { 1365 PAC97BMREG pReg = &pThis->bm_regs[i]; 1366 SSMR3PutU32(pSSM, pReg->bdbar); 1367 SSMR3PutU8( pSSM, pReg->civ); 1368 SSMR3PutU8( pSSM, pReg->lvi); 1369 SSMR3PutU16(pSSM, pReg->sr); 1370 SSMR3PutU16(pSSM, pReg->picb); 1371 SSMR3PutU8( pSSM, pReg->piv); 1372 SSMR3PutU8( pSSM, pReg->cr); 1373 SSMR3PutS32(pSSM, pReg->bd_valid); 1374 SSMR3PutU32(pSSM, pReg->bd.addr); 1375 SSMR3PutU32(pSSM, pReg->bd.ctl_len); 1376 } 1377 SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data)); 1379 1378 1380 1379 uint8_t active[LAST_INDEX]; 1381 active[PI_INDEX] = AUD_is_active_in( s->voice_pi) ? 1 : 0;1382 active[PO_INDEX] = AUD_is_active_out( s->voice_po) ? 1 : 0;1383 active[MC_INDEX] = AUD_is_active_in( s->voice_mc) ? 1 : 0;1380 active[PI_INDEX] = AUD_is_active_in( pThis->voice_pi) ? 1 : 0; 1381 active[PO_INDEX] = AUD_is_active_out(pThis->voice_po) ? 1 : 0; 1382 active[MC_INDEX] = AUD_is_active_in( pThis->voice_mc) ? 1 : 0; 1384 1383 SSMR3PutMem(pSSM, active, sizeof(active)); 1385 1384 … … 1393 1392 static DECLCALLBACK(int) ichac97LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) 1394 1393 { 1395 AC97LinkState *pThis = PDMINS_2_DATA(pDevIns, AC97LinkState *); 1396 AC97LinkState *s = pThis; 1394 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE *); 1397 1395 1398 1396 AssertMsgReturn (uVersion == AC97_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION); 1399 1397 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass); 1400 1398 1401 SSMR3GetU32(pSSM, & s->glob_cnt);1402 SSMR3GetU32(pSSM, & s->glob_sta);1403 SSMR3GetU32(pSSM, & s->cas);1404 1405 for (unsigned i = 0; i < RT_ELEMENTS( s->bm_regs); i++)1406 { 1407 AC97BusMasterRegs *r = &s->bm_regs[i];1408 SSMR3GetU32(pSSM, & r->bdbar);1409 SSMR3GetU8( pSSM, & r->civ);1410 SSMR3GetU8( pSSM, & r->lvi);1411 SSMR3GetU16(pSSM, & r->sr);1412 SSMR3GetU16(pSSM, & r->picb);1413 SSMR3GetU8( pSSM, & r->piv);1414 SSMR3GetU8( pSSM, & r->cr);1415 SSMR3GetS32(pSSM, & r->bd_valid);1416 SSMR3GetU32(pSSM, & r->bd.addr);1417 SSMR3GetU32(pSSM, & r->bd.ctl_len);1418 } 1419 1420 SSMR3GetMem(pSSM, s->mixer_data, sizeof(s->mixer_data));1399 SSMR3GetU32(pSSM, &pThis->glob_cnt); 1400 SSMR3GetU32(pSSM, &pThis->glob_sta); 1401 SSMR3GetU32(pSSM, &pThis->cas); 1402 1403 for (unsigned i = 0; i < RT_ELEMENTS(pThis->bm_regs); i++) 1404 { 1405 PAC97BMREG pReg = &pThis->bm_regs[i]; 1406 SSMR3GetU32(pSSM, &pReg->bdbar); 1407 SSMR3GetU8( pSSM, &pReg->civ); 1408 SSMR3GetU8( pSSM, &pReg->lvi); 1409 SSMR3GetU16(pSSM, &pReg->sr); 1410 SSMR3GetU16(pSSM, &pReg->picb); 1411 SSMR3GetU8( pSSM, &pReg->piv); 1412 SSMR3GetU8( pSSM, &pReg->cr); 1413 SSMR3GetS32(pSSM, &pReg->bd_valid); 1414 SSMR3GetU32(pSSM, &pReg->bd.addr); 1415 SSMR3GetU32(pSSM, &pReg->bd.ctl_len); 1416 } 1417 1418 SSMR3GetMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data)); 1421 1419 uint8_t active[LAST_INDEX]; 1422 1420 SSMR3GetMem(pSSM, active, sizeof(active)); 1423 1421 1424 1422 #ifdef USE_MIXER 1425 record_select( s, mixer_load(s, AC97_Record_Select));1426 # define V_(a, b) set_volume( s, a, b, mixer_load(s, a))1423 record_select(pThis, mixer_load(pThis, AC97_Record_Select)); 1424 # define V_(a, b) set_volume(pThis, a, b, mixer_load(pThis, a)) 1427 1425 V_(AC97_Master_Volume_Mute, AUD_MIXER_VOLUME); 1428 1426 V_(AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM); … … 1430 1428 # undef V_ 1431 1429 #endif /* USE_MIXER */ 1432 reset_voices( s, active);1433 1434 s->bup_flag = 0;1435 s->last_samp = 0;1430 reset_voices(pThis, active); 1431 1432 pThis->bup_flag = 0; 1433 pThis->last_samp = 0; 1436 1434 1437 1435 return VINF_SUCCESS; … … 1444 1442 static DECLCALLBACK(void *) ichac97QueryInterface(struct PDMIBASE *pInterface, const char *pszIID) 1445 1443 { 1446 AC97LinkState *pThis = RT_FROM_MEMBER(pInterface, AC97LinkState, IBase);1444 PAC97STATE pThis = RT_FROM_MEMBER(pInterface, AC97STATE, IBase); 1447 1445 Assert(&pThis->IBase == pInterface); 1448 1446 … … 1460 1458 static DECLCALLBACK(void) ac97Reset(PPDMDEVINS pDevIns) 1461 1459 { 1462 AC97LinkState *pThis = PDMINS_2_DATA(pDevIns, AC97LinkState*);1460 PAC97STATE pThis = PDMINS_2_DATA(pDevIns, AC97STATE *); 1463 1461 1464 1462 /* … … 1483 1481 static DECLCALLBACK(int) ichac97Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 1484 1482 { 1485 AC97 LinkState *pThis = PDMINS_2_DATA(pDevIns, AC97LinkState*);1483 AC97STATE *pThis = PDMINS_2_DATA(pDevIns, AC97STATE *); 1486 1484 int rc; 1487 1485 … … 1628 1626 1, 1629 1627 /* cbInstance */ 1630 sizeof(AC97 LinkState),1628 sizeof(AC97STATE), 1631 1629 /* pfnConstruct */ 1632 1630 ichac97Construct,
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