Changeset 44634 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Feb 11, 2013 3:13:48 PM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 83722
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
r44633 r44634 1920 1920 PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb) 1921 1921 { 1922 int rc = VINF_SUCCESS;1923 1922 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *); 1924 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg; 1925 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg); 1923 uint32_t offReg = GCPhysAddr - pThis->hda.addrMMReg; 1924 int idxReg = hdaMMIORegLookup(&pThis->hda, offReg); 1925 int rc; 1926 Assert(!(offReg & 3)); Assert(cb == 4); 1927 1926 1928 if (pThis->hda.fInReset && idxReg != ICH6_HDA_REG_GCTL) 1927 1929 Log(("hda: access to registers except GCTL is blocked while reset\n")); … … 1932 1934 if (idxReg != -1) 1933 1935 { 1934 /** @todo r=bird: Accesses crossing register boundraries aren't handled 1935 * right from what I can tell? If they are, please explain 1936 * what the rules are. */ 1937 uint32_t mask = 0; 1938 uint32_t shift = (g_aIchIntelHDRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8; 1939 uint32_t u32Value = 0; 1940 switch(cb) 1941 { 1942 case 1: mask = 0x000000ff; break; 1943 case 2: mask = 0x0000ffff; break; 1944 case 4: 1945 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */ 1946 case 8: 1947 mask = 0xffffffff; 1948 cb = 4; 1949 break; 1950 } 1951 #if 0 1952 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL 1953 */ 1954 //Assert((cb <= g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset))); 1955 if (cb > g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset)) 1956 { 1957 int off = cb - (g_aIchIntelHDRegMap[idxReg].size - (offReg - g_aIchIntelHDRegMap[idxReg].offset)); 1958 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off); 1959 if (RT_FAILURE(rc)) 1960 AssertRCReturn (rc, rc); 1961 } 1962 //Assert(((offReg - g_aIchIntelHDRegMap[idxReg].offset) == 0)); 1963 #endif 1964 mask <<= shift; 1965 rc = g_aIchIntelHDRegMap[idxReg].pfnRead(&pThis->hda, offReg, idxReg, &u32Value); 1966 *(uint32_t *)pv |= (u32Value & mask); 1967 Log(("hda: read %s[%x/%x]\n", g_aIchIntelHDRegMap[idxReg].abbrev, u32Value, *(uint32_t *)pv)); 1968 return rc; 1969 } 1970 *(uint32_t *)pv = 0xFF; 1971 Log(("hda: hole at %x is accessed for read\n", offReg)); 1936 rc = g_aIchIntelHDRegMap[idxReg].pfnRead(&pThis->hda, offReg, idxReg, (uint32_t *)pv); 1937 Log(("hda: read %s[%x/%x]\n", g_aIchIntelHDRegMap[idxReg].abbrev, *(uint32_t *)pv)); 1938 } 1939 else 1940 { 1941 rc = VINF_IOM_MMIO_UNUSED_FF; 1942 Log(("hda: hole at %x is accessed for read\n", offReg)); 1943 } 1972 1944 return rc; 1973 1945 } … … 2068 2040 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev); 2069 2041 2042 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */ 2070 2043 Assert(enmType == PCI_ADDRESS_SPACE_MEM); 2071 2044 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/, 2072 IOMMMIO_FLAGS_READ_ PASSTHRU| IOMMMIO_FLAGS_WRITE_PASSTHRU,2045 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU, 2073 2046 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA"); 2074 2047 … … 2485 2458 * @interface_method_impl{PDMDEVREG,pfnConstruct} 2486 2459 */ 2487 static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance, 2488 PCFGMNODE pCfgHandle) 2460 static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle) 2489 2461 { 2490 2462 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
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