Changeset 44636 in vbox

Timestamp:

Feb 11, 2013 3:19:44 PM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

83724

Message:

DevIchIntelHDA.cpp: Let IOM handle unaligned and odd sized write accesses.

File:

• trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp (modified) (4 diffs)

trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp

@@ -1207 +1207 @@
             case ICH6_HDA_REG_SD0CTL:
                 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
-            break;
+                break;
             case ICH6_HDA_REG_SD4CTL:
                 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
-            break;
+                break;
             default:
                 Log(("hda: changing RUN bit on non-attached stream\n"));
@@ -1329 +1329 @@
             Log(("hda: %s requested 8-bit\n", __FUNCTION__));
             pAudSetting->fmt = AUD_FMT_S8;
-        break;
+            break;
         case 1:
             Log(("hda: %s requested 16-bit\n", __FUNCTION__));
             pAudSetting->fmt = AUD_FMT_S16;
-        break;
+            break;
         case 2:
             Log(("hda: %s requested 20-bit\n", __FUNCTION__));
-        break;
+            break;
         case 3:
             Log(("hda: %s requested 24-bit\n", __FUNCTION__));
-        break;
+            break;
         case 4:
             Log(("hda: %s requested 32-bit\n", __FUNCTION__));
             pAudSetting->fmt = AUD_FMT_S32;
-        break;
+            break;
         default:
             AssertMsgFailed(("Unsupported"));
@@ -1473 +1473 @@
             pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
             pState->u64CORBBase |= pState->au32Regs[index];
-        break;
+            break;
         case ICH6_HDA_REG_CORBUBASE:
             pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
             pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
-        break;
+            break;
         case ICH6_HDA_REG_RIRLBASE:
             pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
             pState->u64RIRBBase |= pState->au32Regs[index];
-        break;
+            break;
         case ICH6_HDA_REG_RIRUBASE:
             pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
             pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
-        break;
+            break;
         case ICH6_HDA_REG_DPLBASE:
             /* @todo: first bit has special meaning */
             pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
             pState->u64DPBase |= pState->au32Regs[index];
-        break;
+            break;
         case ICH6_HDA_REG_DPUBASE:
             pState->u64DPBase &= 0x00000000FFFFFFFFULL;
             pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
-        break;
+            break;
         default:
             AssertMsgFailed(("Invalid index"));
@@ -1962 +1962 @@
     if (idxReg != -1)
     {
-        rc = g_aIchIntelHDRegMap[idxReg].pfnWrite(&pThis->hda, offReg, idxReg, u32NewValue);
-        Log(("hda: write %s:(%x) %x => %x\n", g_aIchIntelHDRegMap[idxReg].abbrev, u32NewValue,
+#ifdef LOG_ENABLED
+        uint32_t const u32CurValue = pThis->hda.au32Regs[idxReg];
+#endif
+        rc = g_aIchIntelHDRegMap[idxReg].pfnWrite(&pThis->hda, offReg, idxReg, *(uint32_t const *)pv);
+        Log(("hda: write %s:(%x) %x => %x\n", g_aIchIntelHDRegMap[idxReg].abbrev, *(uint32_t const *)pv,
              u32CurValue, pThis->hda.au32Regs[idxReg]));
     }