VirtualBox

Changeset 44641 in vbox for trunk/src/VBox/Devices


Ignore:
Timestamp:
Feb 11, 2013 7:39:36 PM (12 years ago)
Author:
vboxsync
Message:

DevIchIntelHDA.cpp: s & pState -> pThis like everywhere else.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp

    r44640 r44641  
    6262#define HDA_NREGS 112
    6363/* Registers */
    64 #define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
    65 #define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
    66 #define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
    67 #define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
    68 #define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
    69 #define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
    70 #define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
    71 #define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
    72 #define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
    73 #define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
     64#define HDA_REG_IND_NAME(x)                 ICH6_HDA_REG_##x
     65#define HDA_REG_FIELD_NAME(reg, x)          ICH6_HDA_##reg##_##x
     66#define HDA_REG_FIELD_MASK(reg, x)          ICH6_HDA_##reg##_##x##_MASK
     67#define HDA_REG_FIELD_FLAG_MASK(reg, x)     RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
     68#define HDA_REG_FIELD_SHIFT(reg, x)         ICH6_HDA_##reg##_##x##_SHIFT
     69#define HDA_REG_IND(pThis, x)               ((pThis)->au32Regs[(x)])
     70#define HDA_REG(pThis, x)                   (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
     71#define HDA_REG_VALUE(pThis, reg, val)      (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
     72#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
     73#define HDA_REG_SVALUE(pThis, reg, val)     (HDA_REG_VALUE(pThis, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
    7474
    7575#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
    76 #define GCAP(pState) (HDA_REG((pState), GCAP))
     76#define GCAP(pThis) (HDA_REG((pThis), GCAP))
    7777/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
    7878 * oss (15:12) - number of output streams supported
    … …  
    8989     | ((b64sup) & 1))
    9090#define ICH6_HDA_REG_VMIN           1 /* range 0x02 */
    91 #define VMIN(pState)                (HDA_REG((pState), VMIN))
     91#define VMIN(pThis)                 (HDA_REG((pThis), VMIN))
    9292
    9393#define ICH6_HDA_REG_VMAJ           2 /* range 0x03 */
    94 #define VMAJ(pState)                (HDA_REG((pState), VMAJ))
     94#define VMAJ(pThis)                 (HDA_REG((pThis), VMAJ))
    9595
    9696#define ICH6_HDA_REG_OUTPAY         3 /* range 0x04-0x05 */
    97 #define OUTPAY(pState)              (HDA_REG((pState), OUTPAY))
     97#define OUTPAY(pThis)               (HDA_REG((pThis), OUTPAY))
    9898
    9999#define ICH6_HDA_REG_INPAY          4 /* range 0x06-0x07 */
    100 #define INPAY(pState)               (HDA_REG((pState), INPAY))
     100#define INPAY(pThis)                (HDA_REG((pThis), INPAY))
    101101
    102102#define ICH6_HDA_REG_GCTL           (5)
    … …  
    104104#define ICH6_HDA_GCTL_FSH_SHIFT     (1)
    105105#define ICH6_HDA_GCTL_UR_SHIFT      (8)
    106 #define GCTL(pState)                (HDA_REG((pState), GCTL))
     106#define GCTL(pThis)                 (HDA_REG((pThis), GCTL))
    107107
    108108#define ICH6_HDA_REG_WAKEEN         6 /* 0x0C */
    109 #define WAKEEN(pState)              (HDA_REG((pState), WAKEEN))
     109#define WAKEEN(pThis)               (HDA_REG((pThis), WAKEEN))
    110110
    111111#define ICH6_HDA_REG_STATESTS       7 /* range 0x0E */
    112 #define STATESTS(pState)            (HDA_REG((pState), STATESTS))
     112#define STATESTS(pThis)             (HDA_REG((pThis), STATESTS))
    113113#define ICH6_HDA_STATES_SCSF        0x7
    114114
    115115#define ICH6_HDA_REG_GSTS           8 /* range 0x10-0x11*/
    116116#define ICH6_HDA_GSTS_FSH_SHIFT     (1)
    117 #define GSTS(pState)                (HDA_REG(pState, GSTS))
     117#define GSTS(pThis)                 (HDA_REG(pThis, GSTS))
    118118
    119119#define ICH6_HDA_REG_INTCTL         9 /* 0x20 */
    … …  
    128128#define ICH6_HDA_INTCTL_S6_SHIFT    (6)
    129129#define ICH6_HDA_INTCTL_S7_SHIFT    (7)
    130 #define INTCTL(pState)              (HDA_REG((pState), INTCTL))
    131 #define INTCTL_GIE(pState)          (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
    132 #define INTCTL_CIE(pState)          (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
    133 #define INTCTL_SX(pState, X)        (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
    134 #define INTCTL_SALL(pState)         (INTCTL((pState)) & 0xFF)
     130#define INTCTL(pThis)               (HDA_REG((pThis), INTCTL))
     131#define INTCTL_GIE(pThis)           (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
     132#define INTCTL_CIE(pThis)           (HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE))
     133#define INTCTL_SX(pThis, X)         (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
     134#define INTCTL_SALL(pThis)          (INTCTL((pThis)) & 0xFF)
    135135
    136136/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
    … …  
    139139 */
    140140#define ICH6_HDA_REG_SSYNC          12 /* 0x34 */
    141 #define SSYNC(pState)               (HDA_REG((pState), SSYNC))
     141#define SSYNC(pThis)                (HDA_REG((pThis), SSYNC))
    142142
    143143#define ICH6_HDA_REG_INTSTS         10 /* 0x24 */
    … …  
    153153#define ICH6_HDA_INTSTS_S7_SHIFT    (7)
    154154#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
    155 #define INTSTS(pState)              (HDA_REG((pState), INTSTS))
    156 #define INTSTS_GIS(pState)          (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
    157 #define INTSTS_CIS(pState)          (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
    158 #define INTSTS_SX(pState, X)        (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
    159 #define INTSTS_SANY(pState)         (INTSTS((pState)) & 0xFF)
     155#define INTSTS(pThis)               (HDA_REG((pThis), INTSTS))
     156#define INTSTS_GIS(pThis)           (HDA_REG_FLAG_VALUE((pThis), INTSTS, GIS)
     157#define INTSTS_CIS(pThis)           (HDA_REG_FLAG_VALUE((pThis), INTSTS, CIS)
     158#define INTSTS_SX(pThis, X)         (HDA_REG_FLAG_VALUE(pThis), INTSTS, S##X)
     159#define INTSTS_SANY(pThis)          (INTSTS((pThis)) & 0xFF)
    160160
    161161#define ICH6_HDA_REG_CORBLBASE      13 /* 0x40 */
    162 #define CORBLBASE(pState)           (HDA_REG((pState), CORBLBASE))
     162#define CORBLBASE(pThis)            (HDA_REG((pThis), CORBLBASE))
    163163#define ICH6_HDA_REG_CORBUBASE      14 /* 0x44 */
    164 #define CORBUBASE(pState)           (HDA_REG((pState), CORBUBASE))
     164#define CORBUBASE(pThis)            (HDA_REG((pThis), CORBUBASE))
    165165#define ICH6_HDA_REG_CORBWP         15 /* 48 */
    166166#define ICH6_HDA_REG_CORBRP         16 /* 4A */
    … …  
    169169#define ICH6_HDA_CORBRP_WP_MASK     0xFF
    170170
    171 #define CORBRP(pState)              (HDA_REG(pState, CORBRP))
    172 #define CORBWP(pState)              (HDA_REG(pState, CORBWP))
     171#define CORBRP(pThis)               (HDA_REG(pThis, CORBRP))
     172#define CORBWP(pThis)               (HDA_REG(pThis, CORBWP))
    173173
    174174#define ICH6_HDA_REG_CORBCTL        17 /* 0x4C */
    … …  
    176176#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
    177177
    178 #define CORBCTL(pState)             (HDA_REG(pState, CORBCTL))
     178#define CORBCTL(pThis)              (HDA_REG(pThis, CORBCTL))
    179179
    180180
    181181#define ICH6_HDA_REG_CORBSTS        18 /* 0x4D */
    182 #define CORBSTS(pState)             (HDA_REG(pState, CORBSTS))
     182#define CORBSTS(pThis)              (HDA_REG(pThis, CORBSTS))
    183183#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
    184184
    … …  
    186186#define ICH6_HDA_CORBSIZE_SZ_CAP    0xF0
    187187#define ICH6_HDA_CORBSIZE_SZ        0x3
    188 #define CORBSIZE_SZ(pState)         (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
    189 #define CORBSIZE_SZ_CAP(pState)     (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
     188#define CORBSIZE_SZ(pThis)          (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
     189#define CORBSIZE_SZ_CAP(pThis)      (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
    190190/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
    191191
    192192#define ICH6_HDA_REG_RIRLBASE       20 /* 0x50 */
    193 #define RIRLBASE(pState)            (HDA_REG((pState), RIRLBASE))
     193#define RIRLBASE(pThis)             (HDA_REG((pThis), RIRLBASE))
    194194
    195195#define ICH6_HDA_REG_RIRUBASE       21 /* 0x54 */
    196 #define RIRUBASE(pState)            (HDA_REG((pState), RIRUBASE))
     196#define RIRUBASE(pThis)             (HDA_REG((pThis), RIRUBASE))
    197197
    198198#define ICH6_HDA_REG_RIRBWP         22 /* 0x58 */
    199199#define ICH6_HDA_RIRBWP_RST_SHIFT   (15)
    200200#define ICH6_HDA_RIRBWP_WP_MASK     0xFF
    201 #define RIRBWP(pState)              (HDA_REG(pState, RIRBWP))
     201#define RIRBWP(pThis)              (HDA_REG(pThis, RIRBWP))
    202202
    203203#define ICH6_HDA_REG_RINTCNT        23 /* 0x5A */
    204 #define RINTCNT(pState)             (HDA_REG((pState), RINTCNT))
    205 #define RINTCNT_N(pState)           (RINTCNT((pState)) & 0xff)
     204#define RINTCNT(pThis)              (HDA_REG((pThis), RINTCNT))
     205#define RINTCNT_N(pThis)            (RINTCNT((pThis)) & 0xff)
    206206
    207207#define ICH6_HDA_REG_RIRBCTL        24 /* 0x5C */
    … …  
    209209#define ICH6_HDA_RIRBCTL_DMA_SHIFT  (1)
    210210#define ICH6_HDA_ROI_DMA_SHIFT      (2)
    211 #define RIRBCTL(pState)             (HDA_REG((pState), RIRBCTL))
    212 #define RIRBCTL_RIRB_RIC(pState)    (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
    213 #define RIRBCTL_RIRB_DMA(pState)    (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
    214 #define RIRBCTL_ROI(pState)         (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
     211#define RIRBCTL(pThis)              (HDA_REG((pThis), RIRBCTL))
     212#define RIRBCTL_RIRB_RIC(pThis)     (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
     213#define RIRBCTL_RIRB_DMA(pThis)     (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, DMA)
     214#define RIRBCTL_ROI(pThis)          (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, ROI))
    215215
    216216#define ICH6_HDA_REG_RIRBSTS        25 /* 0x5D */
    217217#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
    218218#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
    219 #define RIRBSTS(pState)             (HDA_REG(pState, RIRBSTS))
    220 #define RIRBSTS_RINTFL(pState)      (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
    221 #define RIRBSTS_RIRBOIS(pState)     (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
     219#define RIRBSTS(pThis)              (HDA_REG(pThis, RIRBSTS))
     220#define RIRBSTS_RINTFL(pThis)       (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL))
     221#define RIRBSTS_RIRBOIS(pThis)      (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS))
    222222
    223223#define ICH6_HDA_REG_RIRBSIZE       26 /* 0x5E */
    … …  
    225225#define ICH6_HDA_RIRBSIZE_SZ        0x3
    226226
    227 #define RIRBSIZE_SZ(pState)         (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
    228 #define RIRBSIZE_SZ_CAP(pState)     (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
     227#define RIRBSIZE_SZ(pThis)          (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
     228#define RIRBSIZE_SZ_CAP(pThis)      (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
    229229
    230230
    231231#define ICH6_HDA_REG_IC             27 /* 0x60 */
    232 #define IC(pState)                  (HDA_REG(pState, IC))
     232#define IC(pThis)                   (HDA_REG(pThis, IC))
    233233#define ICH6_HDA_REG_IR             28 /* 0x64 */
    234 #define IR(pState)                  (HDA_REG(pState, IR))
     234#define IR(pThis)                   (HDA_REG(pThis, IR))
    235235#define ICH6_HDA_REG_IRS            29 /* 0x68 */
    236236#define ICH6_HDA_IRS_ICB_SHIFT      (0)
    237237#define ICH6_HDA_IRS_IRV_SHIFT      (1)
    238 #define IRS(pState)                 (HDA_REG(pState, IRS))
    239 #define IRS_ICB(pState)             (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
    240 #define IRS_IRV(pState)             (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
     238#define IRS(pThis)                  (HDA_REG(pThis, IRS))
     239#define IRS_ICB(pThis)              (HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
     240#define IRS_IRV(pThis)              (HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
    241241
    242242#define ICH6_HDA_REG_DPLBASE        30 /* 0x70 */
    243 #define DPLBASE(pState)             (HDA_REG((pState), DPLBASE))
     243#define DPLBASE(pThis)              (HDA_REG((pThis), DPLBASE))
    244244#define ICH6_HDA_REG_DPUBASE        31 /* 0x74 */
    245 #define DPUBASE(pState)             (HDA_REG((pState), DPUBASE))
     245#define DPUBASE(pThis)              (HDA_REG((pThis), DPUBASE))
    246246#define DPBASE_ENABLED              1
    247247#define DPBASE_ADDR_MASK            (~(uint64_t)0x7f)
    248248
    249249#define HDA_STREAM_REG_DEF(name, num)           (ICH6_HDA_REG_SD##num##name)
    250 #define HDA_STREAM_REG(pState, name, num)       (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
     250#define HDA_STREAM_REG(pThis, name, num)        (HDA_REG((pThis), N_(HDA_STREAM_REG_DEF(name, num))))
    251251/* Note: sdnum here _MUST_ be stream reg number [0,7] */
    252 #define HDA_STREAM_REG2(pState, name, sdnum)    (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
     252#define HDA_STREAM_REG2(pThis, name, sdnum)     (HDA_REG_IND((pThis), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
    253253
    254254#define ICH6_HDA_REG_SD0CTL         32 /* 0x80 */
    … …  
    262262
    263263#define SD(func, num)               SD##num##func
    264 #define SDCTL(pState, num)          HDA_REG((pState), SD(CTL, num))
    265 #define SDCTL_NUM(pState, num)      ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
     264#define SDCTL(pThis, num)           HDA_REG((pThis), SD(CTL, num))
     265#define SDCTL_NUM(pThis, num)       ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
    266266#define ICH6_HDA_SDCTL_NUM_MASK     (0xF)
    267267#define ICH6_HDA_SDCTL_NUM_SHIFT    (20)
    … …  
    285285#define ICH6_HDA_REG_SD7STS         (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
    286286
    287 #define SDSTS(pState, num)          HDA_REG((pState), SD(STS, num))
     287#define SDSTS(pThis, num)           HDA_REG((pThis), SD(STS, num))
    288288#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
    289289#define ICH6_HDA_SDSTS_DE_SHIFT     (4)
    … …  
    300300#define ICH6_HDA_REG_SD7LPIB        (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
    301301
    302 #define SDLPIB(pState, num)         HDA_REG((pState), SD(LPIB, num))
     302#define SDLPIB(pThis, num)          HDA_REG((pThis), SD(LPIB, num))
    303303
    304304#define ICH6_HDA_REG_SD0CBL         35 /* 0x88 */
    … …  
    311311#define ICH6_HDA_REG_SD7CBL         (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
    312312
    313 #define SDLCBL(pState, num)         HDA_REG((pState), SD(CBL, num))
     313#define SDLCBL(pThis, num)          HDA_REG((pThis), SD(CBL, num))
    314314
    315315#define ICH6_HDA_REG_SD0LVI         36 /* 0x8C */
    … …  
    322322#define ICH6_HDA_REG_SD7LVI         (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
    323323
    324 #define SDLVI(pState, num)          HDA_REG((pState), SD(LVI, num))
     324#define SDLVI(pThis, num)           HDA_REG((pThis), SD(LVI, num))
    325325
    326326#define ICH6_HDA_REG_SD0FIFOW       37 /* 0x8E */
    … …  
    339339#define HDA_SDFIFOW_16B             (0x3)
    340340#define HDA_SDFIFOW_32B             (0x4)
    341 #define SDFIFOW(pState, num)        HDA_REG((pState), SD(FIFOW, num))
     341#define SDFIFOW(pThis, num)         HDA_REG((pThis), SD(FIFOW, num))
    342342
    343343#define ICH6_HDA_REG_SD0FIFOS       38 /* 0x90 */
    … …  
    363363#define HDA_SDINFIFO_120B           (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
    364364#define HDA_SDINFIFO_160B           (0x9F) /* 20-, 24-bit Input Streams Streams */
    365 #define SDFIFOS(pState, num)        HDA_REG((pState), SD(FIFOS, num))
     365#define SDFIFOS(pThis, num)         HDA_REG((pThis), SD(FIFOS, num))
    366366
    367367#define ICH6_HDA_REG_SD0FMT         39 /* 0x92 */
    … …  
    374374#define ICH6_HDA_REG_SD7FMT         (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
    375375
    376 #define SDFMT(pState, num)          (HDA_REG((pState), SD(FMT, num)))
     376#define SDFMT(pThis, num)           (HDA_REG((pThis), SD(FMT, num)))
    377377#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
    378378#define ICH6_HDA_SDFMT_MULT_SHIFT   (11)
    … …  
    382382#define ICH6_HDA_SDFMT_BITS_SHIFT   (4)
    383383#define ICH6_HDA_SDFMT_BITS_MASK    (0x7)
    384 #define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
    385 #define SDFMT_MULT(pState, num)     ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
    386 #define SDFMT_DIV(pState, num)      ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
     384#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
     385#define SDFMT_MULT(pThis, num)      ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
     386#define SDFMT_DIV(pThis, num)       ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
    387387
    388388#define ICH6_HDA_REG_SD0BDPL        40 /* 0x98 */
    … …  
    395395#define ICH6_HDA_REG_SD7BDPL        (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
    396396
    397 #define SDBDPL(pState, num)         HDA_REG((pState), SD(BDPL, num))
     397#define SDBDPL(pThis, num)          HDA_REG((pThis), SD(BDPL, num))
    398398
    399399#define ICH6_HDA_REG_SD0BDPU        41 /* 0x9C */
    … …  
    406406#define ICH6_HDA_REG_SD7BDPU        (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
    407407
    408 #define SDBDPU(pState, num)         HDA_REG((pState), SD(BDPU, num))
     408#define SDBDPU(pThis, num)          HDA_REG((pThis), SD(BDPU, num))
    409409
    410410
    … …  
    447447    /** The base interface for LUN\#0. */
    448448    PDMIBASE                IBase;
    449     RTGCPHYS                addrMMReg;
     449    RTGCPHYS                MMIOBaseAddr;
    450450    uint32_t                au32Regs[HDA_NREGS];
    451451    HDABDLEDESC             StInBdle;
    … …  
    468468    bool                    fInReset;
    469469    CODECState              Codec;
     470    /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
    470471    uint8_t                 u8Counter;
    471472    uint64_t                u64BaseTS;
    … …  
    479480#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PHDASTATE)(pPciDev))
    480481
    481 #define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In,    \
    482                 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
    483 #define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out,    \
    484                 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
     482#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
     483    ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
     484#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
     485    ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
    485486
    486487
    … …  
    492493/** @todo r=bird: Why aren't these static? And why use DECLCALLBACK for
    493494 *        internal functions? */
    494 DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    495 DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    496 DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    497 DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    498 DECLCALLBACK(int) hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    499 DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    500 DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    501 DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    502 DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    503 DECLCALLBACK(int) hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    504 DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    505 DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    506 DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    507 DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    508 DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    509 DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    510 DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    511 DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    512 DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    513 DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    514 
    515 DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    516 DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    517 DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    518 DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    519 DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    520 DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    521 DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    522 DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
    523 DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    524 DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    525 DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    526 DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    527 DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    528 DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    529 DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    530 DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
    531 
    532 DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm,
     495DECLCALLBACK(int) hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     496DECLCALLBACK(int) hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     497DECLCALLBACK(int) hdaRegReadGCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     498DECLCALLBACK(int) hdaRegWriteGCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     499DECLCALLBACK(int) hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     500DECLCALLBACK(int) hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     501DECLCALLBACK(int) hdaRegReadGCAP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     502DECLCALLBACK(int) hdaRegReadINTSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     503DECLCALLBACK(int) hdaRegReadWALCLK(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     504DECLCALLBACK(int) hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     505DECLCALLBACK(int) hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     506DECLCALLBACK(int) hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     507DECLCALLBACK(int) hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     508DECLCALLBACK(int) hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     509DECLCALLBACK(int) hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     510DECLCALLBACK(int) hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     511DECLCALLBACK(int) hdaRegWriteIRS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     512DECLCALLBACK(int) hdaRegReadIRS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     513DECLCALLBACK(int) hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     514DECLCALLBACK(int) hdaRegReadSDCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     515
     516DECLCALLBACK(int) hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     517DECLCALLBACK(int) hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     518DECLCALLBACK(int) hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     519DECLCALLBACK(int) hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     520DECLCALLBACK(int) hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     521DECLCALLBACK(int) hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     522DECLCALLBACK(int) hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     523DECLCALLBACK(int) hdaRegWriteBase(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
     524DECLCALLBACK(int) hdaRegReadU32(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     525DECLCALLBACK(int) hdaRegWriteU32(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     526DECLCALLBACK(int) hdaRegReadU24(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     527DECLCALLBACK(int) hdaRegWriteU24(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     528DECLCALLBACK(int) hdaRegReadU16(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     529DECLCALLBACK(int) hdaRegWriteU16(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     530DECLCALLBACK(int) hdaRegReadU8(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     531DECLCALLBACK(int) hdaRegWriteU8(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t pu32Value);
     532
     533DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
    533534                                           PHDASTREAMTRANSFERDESC pStreamDesc);
    534 static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t offReg);
    535 static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
     535static int hdaMMIORegLookup(PHDASTATE pThis, uint32_t offReg);
     536static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
    536537#ifdef LOG_ENABLED
    537 static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
     538static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
    538539#endif
    539540
    … …  
    554555    uint32_t    writable;
    555556    /** Read callback. */
    556     int       (*pfnRead)(INTELHDLinkState *pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
     557    int       (*pfnRead)(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
    557558    /** Write callback. */
    558     int       (*pfnWrite)(INTELHDLinkState *pState, uint32_t offset, uint32_t index, uint32_t u32Value);
     559    int       (*pfnWrite)(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
    559560    /** Abbreviated name. */
    560561    const char *abbrev;
    … …  
    718719
    719720
    720 DECLINLINE(void) hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
    721 {
    722     if (pState->u64DPBase & DPBASE_ENABLED)
    723         PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
    724                        (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
    725 }
    726 DECLINLINE(uint32_t) hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
     721DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
     722{
     723    if (pThis->u64DPBase & DPBASE_ENABLED)
     724        PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pThis),
     725                           (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
     726                           pStreamDesc->pu32Lpib, sizeof(uint32_t));
     727}
     728DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
    727729{
    728730#if 0
    729     switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
     731    switch(HDA_STREAM_REG2(pThis, FIFOW, pStreamDesc->u8Strm))
    730732    {
    731733        case HDA_SDFIFOW_8B: return 8;
    … …  
    733735        case HDA_SDFIFOW_32B: return 32;
    734736        default:
    735             AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
     737            AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
    736738    }
    737739#endif
    … …  
    739741}
    740742
    741 static int hdaProcessInterrupt(INTELHDLinkState* pState)
    742 {
    743 #define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num)                      \
    744         (   INTCTL_SX((pState), num)                                        \
    745          && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
     743static int hdaProcessInterrupt(PHDASTATE pThis)
     744{
     745#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
     746        (   INTCTL_SX((pThis), num) \
     747         && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
    746748    bool fIrq = false;
    747     if (   INTCTL_CIE(pState)
    748        && (   RIRBSTS_RINTFL(pState)
    749            || RIRBSTS_RIRBOIS(pState)
    750            || (STATESTS(pState) & WAKEEN(pState))))
     749    if (   INTCTL_CIE(pThis)
     750       && (   RIRBSTS_RINTFL(pThis)
     751           || RIRBSTS_RIRBOIS(pThis)
     752           || (STATESTS(pThis) & WAKEEN(pThis))))
    751753        fIrq = true;
    752754
    753     if (   IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
    754         || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
     755    if (   IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
     756        || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
    755757        fIrq = true;
    756758
    757     if (INTCTL_GIE(pState))
     759    if (INTCTL_GIE(pThis))
    758760    {
    759761        Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
    760         PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
     762        PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pThis), 0 , fIrq);
    761763    }
    762764    return VINF_SUCCESS;
    763765}
    764766
    765 static int hdaMMIORegLookup(INTELHDLinkState* pState, uint32_t offReg)
     767static int hdaMMIORegLookup(PHDASTATE pThis, uint32_t offReg)
    766768{
    767769    /*
    … …  
    814816}
    815817
    816 static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
     818static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
    817819{
    818820    int rc = VINF_SUCCESS;
    819821    if (fLocal)
    820822    {
    821         Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
    822         rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
     823        Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
     824        rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
    823825        if (RT_FAILURE(rc))
    824826            AssertRCReturn(rc, rc);
    … …  
    832834            {
    833835                const char *prefix;
    834                 if ((i + j) == CORBRP(pState))
     836                if ((i + j) == CORBRP(pThis))
    835837                    prefix = "[R]";
    836                 else if ((i + j) == CORBWP(pState))
     838                else if ((i + j) == CORBWP(pThis))
    837839                    prefix = "[W]";
    838840                else
    839841                    prefix = "   "; /* three spaces */
    840                 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
     842                Log(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
    841843                j++;
    842844            } while (j < 8);
    … …  
    848850    else
    849851    {
    850         Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
    851         rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
     852        Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
     853        rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pThis), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
    852854        if (RT_FAILURE(rc))
    853855            AssertRCReturn(rc, rc);
    … …  
    859861            do {
    860862                const char *prefix;
    861                 if ((i + j) == RIRBWP(pState))
     863                if ((i + j) == RIRBWP(pThis))
    862864                    prefix = "[W]";
    863865                else
    864866                    prefix = "   ";
    865                 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
     867                Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
    866868            } while (++j < 8);
    867869            Log(("\n"));
    … …  
    873875}
    874876
    875 static int hdaCORBCmdProcess(INTELHDLinkState *pState)
     877static int hdaCORBCmdProcess(PHDASTATE pThis)
    876878{
    877879    int rc;
    … …  
    882884    PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
    883885
    884     rc = hdaCmdSync(pState, true);
     886    rc = hdaCmdSync(pThis, true);
    885887    if (RT_FAILURE(rc))
    886888        AssertRCReturn(rc, rc);
    887     corbRp = CORBRP(pState);
    888     corbWp = CORBWP(pState);
    889     rirbWp = RIRBWP(pState);
     889    corbRp = CORBRP(pThis);
     890    corbWp = CORBWP(pThis);
     891    rirbWp = RIRBWP(pThis);
    890892    Assert((corbWp != corbRp));
    891     Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
     893    Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
    892894    while (corbRp != corbWp)
    893895    {
    … …  
    896898        pfn = (PFNCODECVERBPROCESSOR)NULL;
    897899        corbRp++;
    898         cmd = pState->pu32CorbBuf[corbRp];
    899         rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
     900        cmd = pThis->pu32CorbBuf[corbRp];
     901        rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
    900902        if (RT_FAILURE(rc))
    901903            AssertRCReturn(rc, rc);
    … …  
    904906
    905907        if (RT_LIKELY(pfn))
    906             rc = pfn(&pState->Codec, cmd, &resp);
     908            rc = pfn(&pThis->Codec, cmd, &resp);
    907909        else
    908910            rc = VERR_INVALID_FUNCTION;
    … …  
    912914        Log(("hda: verb:%08x->%016lx\n", cmd, resp));
    913915        if (   (resp & CODEC_RESPONSE_UNSOLICITED)
    914             && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
     916            && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
    915917        {
    916918            Log(("hda: unexpected unsolicited response.\n"));
    917             pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
     919            pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
    918920            return rc;
    919921        }
    920         pState->pu64RirbBuf[rirbWp] = resp;
    921         pState->u8Counter++;
    922         if (pState->u8Counter == RINTCNT_N(pState))
     922        pThis->pu64RirbBuf[rirbWp] = resp;
     923        pThis->u8Counter++;
     924        if (pThis->u8Counter == RINTCNT_N(pThis))
    923925            break;
    924926    }
    925     pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
    926     pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
    927     rc = hdaCmdSync(pState, false);
    928     Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
    929     if (RIRBCTL_RIRB_RIC(pState))
    930     {
    931         RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
    932         pState->u8Counter = 0;
    933         rc = hdaProcessInterrupt(pState);
     927    pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
     928    pThis->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
     929    rc = hdaCmdSync(pThis, false);
     930    Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
     931    if (RIRBCTL_RIRB_RIC(pThis))
     932    {
     933        RIRBSTS((pThis)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
     934        pThis->u8Counter = 0;
     935        rc = hdaProcessInterrupt(pThis);
    934936    }
    935937    if (RT_FAILURE(rc))
    … …  
    938940}
    939941
    940 static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
     942static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
    941943{
    942944    Log(("hda: reset of stream (%d) started\n", u8Strm));
    943     Assert((   pState
     945    Assert((   pThis
    944946            && pBdle
    945947            && pStreamDesc
    … …  
    950952    /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
    951953     * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
    952     HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
     954    HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
    953955
    954956    /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
    955     HDA_STREAM_REG2(pState, FIFOS, u8Strm) =  u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
    956     HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
    957     HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
    958     HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
    959     HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
    960     HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
    961     HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
     957    HDA_STREAM_REG2(pThis, FIFOS, u8Strm) =  u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
     958    HDA_STREAM_REG2(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
     959    HDA_STREAM_REG2(pThis, CBL, u8Strm) = 0;
     960    HDA_STREAM_REG2(pThis, LVI, u8Strm) = 0;
     961    HDA_STREAM_REG2(pThis, FMT, u8Strm) = 0;
     962    HDA_STREAM_REG2(pThis, BDPU, u8Strm) = 0;
     963    HDA_STREAM_REG2(pThis, BDPL, u8Strm) = 0;
    962964    Log(("hda: reset of stream (%d) finished\n", u8Strm));
    963965}
    964966
    965967
    966 DECLCALLBACK(int) hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     968DECLCALLBACK(int) hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    967969{
    968970    *pu32Value = 0;
    969971    return VINF_SUCCESS;
    970972}
    971 DECLCALLBACK(int) hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     973DECLCALLBACK(int) hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    972974{
    973975    return VINF_SUCCESS;
    974976}
    975977/* U8 */
    976 DECLCALLBACK(int) hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    977 {
    978     Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffffff00) == 0);
    979     return hdaRegReadU32(pState, offset, index, pu32Value);
    980 }
    981 
    982 DECLCALLBACK(int) hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     978DECLCALLBACK(int) hdaRegReadU8(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     979{
     980    Assert(((pThis->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffffff00) == 0);
     981    return hdaRegReadU32(pThis, offset, index, pu32Value);
     982}
     983
     984DECLCALLBACK(int) hdaRegWriteU8(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    983985{
    984986    Assert(((u32Value & 0xffffff00) == 0));
    985     return hdaRegWriteU32(pState, offset, index, u32Value);
     987    return hdaRegWriteU32(pThis, offset, index, u32Value);
    986988}
    987989/* U16 */
    988 DECLCALLBACK(int) hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    989 {
    990     Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffff0000) == 0);
    991     return hdaRegReadU32(pState, offset, index, pu32Value);
    992 }
    993 
    994 DECLCALLBACK(int) hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     990DECLCALLBACK(int) hdaRegReadU16(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     991{
     992    Assert(((pThis->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xffff0000) == 0);
     993    return hdaRegReadU32(pThis, offset, index, pu32Value);
     994}
     995
     996DECLCALLBACK(int) hdaRegWriteU16(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    995997{
    996998    Assert(((u32Value & 0xffff0000) == 0));
    997     return hdaRegWriteU32(pState, offset, index, u32Value);
     999    return hdaRegWriteU32(pThis, offset, index, u32Value);
    9981000}
    9991001
    10001002/* U24 */
    1001 DECLCALLBACK(int) hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    1002 {
    1003     Assert(((pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xff000000) == 0);
    1004     return hdaRegReadU32(pState, offset, index, pu32Value);
    1005 }
    1006 
    1007 DECLCALLBACK(int) hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1003DECLCALLBACK(int) hdaRegReadU24(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1004{
     1005    Assert(((pThis->au32Regs[index] & g_aIchIntelHDRegMap[index].readable) & 0xff000000) == 0);
     1006    return hdaRegReadU32(pThis, offset, index, pu32Value);
     1007}
     1008
     1009DECLCALLBACK(int) hdaRegWriteU24(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    10081010{
    10091011    Assert(((u32Value & 0xff000000) == 0));
    1010     return hdaRegWriteU32(pState, offset, index, u32Value);
     1012    return hdaRegWriteU32(pThis, offset, index, u32Value);
    10111013}
    10121014/* U32 */
    1013 DECLCALLBACK(int) hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    1014 {
    1015     *pu32Value = pState->au32Regs[index] & g_aIchIntelHDRegMap[index].readable;
     1015DECLCALLBACK(int) hdaRegReadU32(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1016{
     1017    *pu32Value = pThis->au32Regs[index] & g_aIchIntelHDRegMap[index].readable;
    10161018    return VINF_SUCCESS;
    10171019}
    10181020
    1019 DECLCALLBACK(int) hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1020 {
    1021     pState->au32Regs[index]  = (u32Value & g_aIchIntelHDRegMap[index].writable)
    1022                                   | (pState->au32Regs[index] & ~g_aIchIntelHDRegMap[index].writable);
     1021DECLCALLBACK(int) hdaRegWriteU32(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1022{
     1023    pThis->au32Regs[index]  = (u32Value & g_aIchIntelHDRegMap[index].writable)
     1024                                  | (pThis->au32Regs[index] & ~g_aIchIntelHDRegMap[index].writable);
    10231025    return VINF_SUCCESS;
    10241026}
    10251027
    1026 DECLCALLBACK(int) hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    1027 {
    1028     return hdaRegReadU32(pState, offset, index, pu32Value);
    1029 }
    1030 
    1031 DECLCALLBACK(int) hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1028DECLCALLBACK(int) hdaRegReadGCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1029{
     1030    return hdaRegReadU32(pThis, offset, index, pu32Value);
     1031}
     1032
     1033DECLCALLBACK(int) hdaRegWriteGCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    10321034{
    10331035    if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
    10341036    {
    10351037        /* exit reset state */
    1036         GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
    1037         pState->fInReset = false;
     1038        GCTL(pThis) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
     1039        pThis->fInReset = false;
    10381040    }
    10391041    else
    10401042    {
    10411043        /* enter reset state*/
    1042         if (   HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
    1043             || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
     1044        if (   HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
     1045            || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
    10441046        {
    10451047            Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
    1046                 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
    1047                 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
     1048                HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
     1049                HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
    10481050        }
    1049         hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
    1050         GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
    1051         pState->fInReset = true;
     1051        hdaReset(ICH6_HDASTATE_2_DEVINS(pThis));
     1052        GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
     1053        pThis->fInReset = true;
    10521054    }
    10531055    if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
    10541056    {
    10551057        /* Flush: GSTS:1 set,  see 6.2.6*/
    1056         GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
     1058        GSTS(pThis) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
    10571059        /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
    10581060    }
    … …  
    10601062}
    10611063
    1062 DECLCALLBACK(int) hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1063 {
    1064     uint32_t v = pState->au32Regs[index];
     1064DECLCALLBACK(int) hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1065{
     1066    uint32_t v = pThis->au32Regs[index];
    10651067    uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
    1066     pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
     1068    pThis->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
    10671069    return VINF_SUCCESS;
    10681070}
    10691071
    1070 DECLCALLBACK(int) hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1072DECLCALLBACK(int) hdaRegReadINTSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    10711073{
    10721074    uint32_t v = 0;
    1073     if (   RIRBSTS_RIRBOIS(pState)
    1074         || RIRBSTS_RINTFL(pState)
    1075         || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
    1076         || STATESTS(pState))
     1075    if (   RIRBSTS_RIRBOIS(pThis)
     1076        || RIRBSTS_RINTFL(pThis)
     1077        || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
     1078        || STATESTS(pThis))
    10771079        v |= RT_BIT(30);
    1078 #define HDA_IS_STREAM_EVENT(pState, stream)             \
    1079        (   (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))  \
    1080         || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))  \
    1081         || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
    1082 #define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
    1083     MARK_STREAM(pState, 0, v);
    1084     MARK_STREAM(pState, 1, v);
    1085     MARK_STREAM(pState, 2, v);
    1086     MARK_STREAM(pState, 3, v);
    1087     MARK_STREAM(pState, 4, v);
    1088     MARK_STREAM(pState, 5, v);
    1089     MARK_STREAM(pState, 6, v);
    1090     MARK_STREAM(pState, 7, v);
     1080#define HDA_IS_STREAM_EVENT(pThis, stream)             \
     1081       (   (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))  \
     1082        || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))  \
     1083        || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
     1084#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
     1085    MARK_STREAM(pThis, 0, v);
     1086    MARK_STREAM(pThis, 1, v);
     1087    MARK_STREAM(pThis, 2, v);
     1088    MARK_STREAM(pThis, 3, v);
     1089    MARK_STREAM(pThis, 4, v);
     1090    MARK_STREAM(pThis, 5, v);
     1091    MARK_STREAM(pThis, 6, v);
     1092    MARK_STREAM(pThis, 7, v);
    10911093    v |= v ? RT_BIT(31) : 0;
    10921094    *pu32Value = v;
    … …  
    10941096}
    10951097
    1096 DECLCALLBACK(int) hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1098DECLCALLBACK(int) hdaRegReadWALCLK(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    10971099{
    10981100    /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
    1099     *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState))
    1100                                                    - pState->u64BaseTS, 24, 1000);
     1101    *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pThis))
     1102                                                   - pThis->u64BaseTS, 24, 1000);
    11011103    return VINF_SUCCESS;
    11021104}
    11031105
    1104 DECLCALLBACK(int) hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    1105 {
    1106     return hdaRegReadU16(pState, offset, index, pu32Value);
    1107 }
    1108 
    1109 DECLCALLBACK(int) hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1106DECLCALLBACK(int) hdaRegReadGCAP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1107{
     1108    return hdaRegReadU16(pThis, offset, index, pu32Value);
     1109}
     1110
     1111DECLCALLBACK(int) hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    11101112{
    11111113    if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
    1112         CORBRP(pState) = 0;
     1114        CORBRP(pThis) = 0;
    11131115    else
    1114         return hdaRegWriteU8(pState, offset, index, u32Value);
     1116        return hdaRegWriteU8(pThis, offset, index, u32Value);
    11151117    return VINF_SUCCESS;
    11161118}
    11171119
    1118 DECLCALLBACK(int) hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1119 {
    1120     int rc = hdaRegWriteU8(pState, offset, index, u32Value);
     1120DECLCALLBACK(int) hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1121{
     1122    int rc = hdaRegWriteU8(pThis, offset, index, u32Value);
    11211123    AssertRC(rc);
    1122     if (   CORBWP(pState) != CORBRP(pState)
    1123         && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
    1124         return hdaCORBCmdProcess(pState);
     1124    if (   CORBWP(pThis) != CORBRP(pThis)
     1125        && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
     1126        return hdaCORBCmdProcess(pThis);
    11251127    return rc;
    11261128}
    11271129
    1128 DECLCALLBACK(int) hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1129 {
    1130     uint32_t v = CORBSTS(pState);
    1131     CORBSTS(pState) &= ~(v & u32Value);
     1130DECLCALLBACK(int) hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1131{
     1132    uint32_t v = CORBSTS(pThis);
     1133    CORBSTS(pThis) &= ~(v & u32Value);
    11321134    return VINF_SUCCESS;
    11331135}
    11341136
    1135 DECLCALLBACK(int) hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1137DECLCALLBACK(int) hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    11361138{
    11371139    int rc;
    1138     rc = hdaRegWriteU16(pState, offset, index, u32Value);
     1140    rc = hdaRegWriteU16(pThis, offset, index, u32Value);
    11391141    if (RT_FAILURE(rc))
    11401142        AssertRCReturn(rc, rc);
    1141     if (CORBWP(pState) == CORBRP(pState))
     1143    if (CORBWP(pThis) == CORBRP(pThis))
    11421144        return VINF_SUCCESS;
    1143     if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
     1145    if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
    11441146        return VINF_SUCCESS;
    1145     rc = hdaCORBCmdProcess(pState);
     1147    rc = hdaCORBCmdProcess(pThis);
    11461148    return rc;
    11471149}
    11481150
    1149 DECLCALLBACK(int) hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    1150 {
    1151     return hdaRegReadU24(pState, offset, index, pu32Value);
    1152 }
    1153 
    1154 DECLCALLBACK(int) hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1155 {
    1156     bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
    1157     bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
    1158     bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
    1159     bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
     1151DECLCALLBACK(int) hdaRegReadSDCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1152{
     1153    return hdaRegReadU24(pThis, offset, index, pu32Value);
     1154}
     1155
     1156DECLCALLBACK(int) hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1157{
     1158    bool fRun     = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
     1159    bool fInRun   = RT_BOOL(HDA_REG_IND(pThis, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
     1160    bool fReset   = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
     1161    bool fInReset = RT_BOOL(HDA_REG_IND(pThis, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
    11601162    int rc = VINF_SUCCESS;
    11611163    if (fInReset)
    … …  
    11811183            case ICH6_HDA_REG_SD0CTL:
    11821184                u8Strm = 0;
    1183                 pBdle = &pState->StInBdle;
     1185                pBdle = &pThis->StInBdle;
    11841186                break;
    11851187            case ICH6_HDA_REG_SD4CTL:
    11861188                u8Strm = 4;
    1187                 pBdle = &pState->StOutBdle;
     1189                pBdle = &pThis->StOutBdle;
    11881190                break;
    11891191            default:
    … …  
    11921194        }
    11931195        Log(("hda: guest initiated enter to stream reset.\n"));
    1194         hdaInitTransferDescriptor(pState, pBdle, u8Strm, &StreamDesc);
    1195         hdaStreamReset(pState, pBdle, &StreamDesc, u8Strm);
     1196        hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
     1197        hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
    11961198        goto l_done;
    11971199    }
    … …  
    12051207        {
    12061208            case ICH6_HDA_REG_SD0CTL:
    1207                 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
     1209                AUD_set_active_in(pThis->Codec.SwVoiceIn, fRun);
    12081210                break;
    12091211            case ICH6_HDA_REG_SD4CTL:
    1210                 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
     1212                AUD_set_active_out(pThis->Codec.SwVoiceOut, fRun);
    12111213                break;
    12121214            default:
    … …  
    12171219
    12181220l_done:
    1219     rc = hdaRegWriteU24(pState, offset, index, u32Value);
     1221    rc = hdaRegWriteU24(pThis, offset, index, u32Value);
    12201222    if (RT_FAILURE(rc))
    12211223        AssertRCReturn(rc, VINF_SUCCESS);
    … …  
    12231225}
    12241226
    1225 DECLCALLBACK(int) hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1226 {
    1227     uint32_t v = HDA_REG_IND(pState, index);
     1227DECLCALLBACK(int) hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1228{
     1229    uint32_t v = HDA_REG_IND(pThis, index);
    12281230    v &= ~(u32Value & v);
    1229     HDA_REG_IND(pState, index) = v;
    1230     hdaProcessInterrupt(pState);
     1231    HDA_REG_IND(pThis, index) = v;
     1232    hdaProcessInterrupt(pThis);
    12311233    return VINF_SUCCESS;
    12321234}
    12331235
    1234 DECLCALLBACK(int) hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1235 {
    1236     int rc = hdaRegWriteU32(pState, offset, index, u32Value);
     1236DECLCALLBACK(int) hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1237{
     1238    int rc = hdaRegWriteU32(pThis, offset, index, u32Value);
    12371239    if (RT_FAILURE(rc))
    12381240        AssertRCReturn(rc, VINF_SUCCESS);
    … …  
    12401242}
    12411243
    1242 DECLCALLBACK(int) hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1244DECLCALLBACK(int) hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    12431245{
    12441246    switch (u32Value)
    … …  
    12471249        case HDA_SDFIFOW_16B:
    12481250        case HDA_SDFIFOW_32B:
    1249             return hdaRegWriteU16(pState, offset, index, u32Value);
     1251            return hdaRegWriteU16(pThis, offset, index, u32Value);
    12501252        default:
    12511253            Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
    1252             return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
     1254            return hdaRegWriteU16(pThis, offset, index, HDA_SDFIFOW_32B);
    12531255    }
    12541256    return VINF_SUCCESS;
    … …  
    12581260 *
    12591261 */
    1260 DECLCALLBACK(int) hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1262DECLCALLBACK(int) hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    12611263{
    12621264    switch (index)
    … …  
    12801282                case HDA_SDONFIFO_128B:
    12811283                case HDA_SDONFIFO_192B:
    1282                     return hdaRegWriteU16(pState, offset, index, u32Value);
     1284                    return hdaRegWriteU16(pThis, offset, index, u32Value);
    12831285
    12841286                case HDA_SDONFIFO_256B:
    12851287                    Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
    12861288                default:
    1287                     return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
     1289                    return hdaRegWriteU16(pThis, offset, index, HDA_SDONFIFO_192B);
    12881290            }
    12891291            return VINF_SUCCESS;
    … …  
    13521354}
    13531355
    1354 DECLCALLBACK(int) hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1356DECLCALLBACK(int) hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    13551357{
    13561358#ifdef VBOX_WITH_HDA_CODEC_EMU
    … …  
    13591361    audsettings_t as;
    13601362    /* no reason to reopen voice with same settings */
    1361     if (u32Value == HDA_REG_IND(pState, index))
     1363    if (u32Value == HDA_REG_IND(pThis, index))
    13621364        return VINF_SUCCESS;
    13631365    hdaSdFmtToAudSettings(u32Value, &as);
    … …  
    13651367    {
    13661368        case ICH6_HDA_REG_SD0FMT:
    1367             rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
     1369            rc = codecOpenVoice(&pThis->Codec, PI_INDEX, &as);
    13681370            break;
    13691371        case ICH6_HDA_REG_SD4FMT:
    1370             rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
     1372            rc = codecOpenVoice(&pThis->Codec, PO_INDEX, &as);
    13711373            break;
    13721374        default:
    … …  
    13741376            rc = 0;
    13751377    }
    1376     return hdaRegWriteU16(pState, offset, index, u32Value);
     1378    return hdaRegWriteU16(pThis, offset, index, u32Value);
    13771379#else
    1378     return hdaRegWriteU16(pState, offset, index, u32Value);
     1380    return hdaRegWriteU16(pThis, offset, index, u32Value);
    13791381#endif
    13801382}
    13811383
    1382 DECLCALLBACK(int) hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1383 {
    1384     int rc = hdaRegWriteU32(pState, offset, index, u32Value);
     1384DECLCALLBACK(int) hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1385{
     1386    int rc = hdaRegWriteU32(pThis, offset, index, u32Value);
    13851387    if (RT_FAILURE(rc))
    13861388        AssertRCReturn(rc, VINF_SUCCESS);
    … …  
    13881390}
    13891391
    1390 DECLCALLBACK(int) hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1391 {
    1392     int rc = hdaRegWriteU32(pState, offset, index, u32Value);
     1392DECLCALLBACK(int) hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1393{
     1394    int rc = hdaRegWriteU32(pThis, offset, index, u32Value);
    13931395    if (RT_FAILURE(rc))
    13941396        AssertRCReturn(rc, VINF_SUCCESS);
    … …  
    13961398}
    13971399
    1398 DECLCALLBACK(int) hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
     1400DECLCALLBACK(int) hdaRegReadIRS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
    13991401{
    14001402    int rc = VINF_SUCCESS;
    14011403    /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
    1402     if (   CORBWP(pState) != CORBRP(pState)
    1403         || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
    1404         IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB);  /* busy */
    1405 
    1406     rc = hdaRegReadU32(pState, offset, index, pu32Value);
     1404    if (   CORBWP(pThis) != CORBRP(pThis)
     1405        || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
     1406        IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB);  /* busy */
     1407
     1408    rc = hdaRegReadU32(pThis, offset, index, pu32Value);
    14071409    return rc;
    14081410}
    14091411
    1410 DECLCALLBACK(int) hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1412DECLCALLBACK(int) hdaRegWriteIRS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    14111413{
    14121414    int rc = VINF_SUCCESS;
    … …  
    14181420     */
    14191421    if (   u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
    1420         && !IRS_ICB(pState))
    1421     {
    1422         uint32_t cmd = IC(pState);
    1423         if (CORBWP(pState) != CORBRP(pState))
     1422        && !IRS_ICB(pThis))
     1423    {
     1424        uint32_t cmd = IC(pThis);
     1425        if (CORBWP(pThis) != CORBRP(pThis))
    14241426        {
    14251427            /*
    … …  
    14291431            return rc;
    14301432        }
    1431         IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB);  /* busy */
     1433        IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB);  /* busy */
    14321434        Log(("hda: IC:%x\n", cmd));
    1433         rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
     1435        rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
    14341436        if (RT_FAILURE(rc))
    14351437            AssertRCReturn(rc, rc);
    1436         rc = pfn(&pState->Codec, cmd, &resp);
     1438        rc = pfn(&pThis->Codec, cmd, &resp);
    14371439        if (RT_FAILURE(rc))
    14381440            AssertRCReturn(rc, rc);
    1439         IR(pState) = (uint32_t)resp;
    1440         Log(("hda: IR:%x\n", IR(pState)));
    1441         IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV);  /* result is ready  */
    1442         IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
     1441        IR(pThis) = (uint32_t)resp;
     1442        Log(("hda: IR:%x\n", IR(pThis)));
     1443        IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV);  /* result is ready  */
     1444        IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
    14431445        return rc;
    14441446    }
    … …  
    14471449     */
    14481450    if (   u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
    1449         && IRS_IRV(pState))
    1450         IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
     1451        && IRS_IRV(pThis))
     1452        IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
    14511453    return rc;
    14521454}
    14531455
    1454 DECLCALLBACK(int) hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
     1456DECLCALLBACK(int) hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
    14551457{
    14561458    if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
    14571459    {
    1458         RIRBWP(pState) = 0;
     1460        RIRBWP(pThis) = 0;
    14591461    }
    14601462    /* The remaining bits are O, see 6.2.22 */
    … …  
    14621464}
    14631465
    1464 DECLCALLBACK(int) hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1465 {
    1466     int rc = hdaRegWriteU32(pState, offset, index, u32Value);
     1466DECLCALLBACK(int) hdaRegWriteBase(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1467{
     1468    int rc = hdaRegWriteU32(pThis, offset, index, u32Value);
    14671469    if (RT_FAILURE(rc))
    14681470        AssertRCReturn(rc, rc);
    … …  
    14701472    {
    14711473        case ICH6_HDA_REG_CORBLBASE:
    1472             pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
    1473             pState->u64CORBBase |= pState->au32Regs[index];
     1474            pThis->u64CORBBase &= 0xFFFFFFFF00000000ULL;
     1475            pThis->u64CORBBase |= pThis->au32Regs[index];
    14741476            break;
    14751477        case ICH6_HDA_REG_CORBUBASE:
    1476             pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
    1477             pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
     1478            pThis->u64CORBBase &= 0x00000000FFFFFFFFULL;
     1479            pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[index] << 32);
    14781480            break;
    14791481        case ICH6_HDA_REG_RIRLBASE:
    1480             pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
    1481             pState->u64RIRBBase |= pState->au32Regs[index];
     1482            pThis->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
     1483            pThis->u64RIRBBase |= pThis->au32Regs[index];
    14821484            break;
    14831485        case ICH6_HDA_REG_RIRUBASE:
    1484             pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
    1485             pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
     1486            pThis->u64RIRBBase &= 0x00000000FFFFFFFFULL;
     1487            pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[index] << 32);
    14861488            break;
    14871489        case ICH6_HDA_REG_DPLBASE:
    14881490            /* @todo: first bit has special meaning */
    1489             pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
    1490             pState->u64DPBase |= pState->au32Regs[index];
     1491            pThis->u64DPBase &= 0xFFFFFFFF00000000ULL;
     1492            pThis->u64DPBase |= pThis->au32Regs[index];
    14911493            break;
    14921494        case ICH6_HDA_REG_DPUBASE:
    1493             pState->u64DPBase &= 0x00000000FFFFFFFFULL;
    1494             pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
     1495            pThis->u64DPBase &= 0x00000000FFFFFFFFULL;
     1496            pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[index] << 32);
    14951497            break;
    14961498        default:
    14971499            AssertMsgFailed(("Invalid index"));
    14981500    }
    1499     Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
     1501    Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
    15001502    return rc;
    15011503}
    15021504
    1503 DECLCALLBACK(int) hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
    1504 {
    1505     uint8_t v = RIRBSTS(pState);
    1506     RIRBSTS(pState) &= ~(v & u32Value);
    1507 
    1508     return hdaProcessInterrupt(pState);
     1505DECLCALLBACK(int) hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value)
     1506{
     1507    uint8_t v = RIRBSTS(pThis);
     1508    RIRBSTS(pThis) &= ~(v & u32Value);
     1509
     1510    return hdaProcessInterrupt(pThis);
    15091511}
    15101512
    15111513#ifdef LOG_ENABLED
    1512 static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
     1514static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
    15131515{
    15141516#if 0
    … …  
    15231525    for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
    15241526    {
    1525         PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
     1527        PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), u64BaseDMA + i*16, bdle, 16);
    15261528        addr = *(uint64_t *)bdle;
    15271529        len = *(uint32_t *)&bdle[8];
    … …  
    15331535    for (i = 0; i < 8; ++i)
    15341536    {
    1535         PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
    1536         Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": "   ",
     1537        PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
     1538        Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": "   ",
    15371539             i , counter));
    15381540    }
    … …  
    15411543#endif
    15421544
    1543 static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
     1545static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
    15441546{
    15451547    uint8_t  bdle[16];
    … …  
    15471549            && pBdle
    15481550            && pBdle->u32BdleMaxCvi));
    1549     PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
     1551    PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
    15501552    pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
    15511553    pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
    15521554    pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
    15531555#ifdef LOG_ENABLED
    1554     dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
     1556    dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
    15551557#endif
    15561558}
    … …  
    16251627}
    16261628
    1627 DECLINLINE(void) hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
     1629DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
    16281630                                              uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
    16291631{
    … …  
    16351637        *pu32BackendBufferCapacity -= cbCopied;
    16361638    Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
    1637     Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
    1638 }
    1639 
    1640 DECLINLINE(bool) hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
     1639    Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
     1640}
     1641
     1642DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
    16411643{
    16421644    bool fOnBufferEdge = (   *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
    … …  
    16471649    if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
    16481650        *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
    1649     hdaUpdatePosBuf(pState, pStreamDesc);
     1651    hdaUpdatePosBuf(pThis, pStreamDesc);
    16501652
    16511653    /* don't touch BdleCvi counter on uninitialized descriptor */
    … …  
    16611663}
    16621664
    1663 DECLINLINE(void) hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
     1665DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
    16641666                                        uint32_t cbInc)
    16651667{
    … …  
    16771679        Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
    16781680
    1679         hdaUpdatePosBuf(pState, pStreamDesc);
    1680 
    1681     }
    1682 }
    1683 
    1684 static bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
     1681        hdaUpdatePosBuf(pThis, pStreamDesc);
     1682
     1683    }
     1684}
     1685
     1686static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
    16851687{
    16861688    bool fDoNextTransferLoop = true;
    … …  
    17021704             */
    17031705            if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
    1704                 hdaProcessInterrupt(pState);
     1706                hdaProcessInterrupt(pThis);
    17051707        }
    17061708        fDoNextTransferLoop = false;
    … …  
    17131715 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
    17141716 */
    1715 static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
    1716 {
    1717     PHDABDLEDESC pBdle = &pState->StInBdle;
     1717static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
     1718{
     1719    PHDABDLEDESC pBdle = &pThis->StInBdle;
    17181720    uint32_t cbTransferred = 0;
    17191721    uint32_t cb2Copy = 0;
    … …  
    17341736     * read from backend input line to the last unreported position or at the begining.
    17351737     */
    1736     cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
     1738    cbBackendCopy = AUD_read(pThis->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
    17371739    /*
    17381740     * write the HDA DMA buffer
    17391741     */
    1740     PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
     1742    PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pThis), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
    17411743
    17421744    /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
    17431745    Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
    17441746
    1745     if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
     1747    if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
    17461748        hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
    17471749    else
    17481750    {
    1749         hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
     1751        hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
    17501752        *fStop = true;
    17511753    }
    17521754l_done:
    1753     Assert((cbTransferred <= (SDFIFOS(pState, 0) + 1)));
     1755    Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
    17541756    Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
    17551757    return cbTransferred;
    17561758}
    17571759
    1758 static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
    1759 {
    1760     PHDABDLEDESC pBdle = &pState->StOutBdle;
     1760static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
     1761{
     1762    PHDABDLEDESC pBdle = &pThis->StOutBdle;
    17611763    uint32_t cbTransferred = 0;
    17621764    uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
    … …  
    17761778    }
    17771779
    1778     PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
     1780    PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
    17791781    /*
    17801782     * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
    17811783     */
    1782     if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
     1784    if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
    17831785    {
    17841786        /*
    17851787         * Feed the newly fetched samples, including unreported ones, to the backend.
    17861788         */
    1787         cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
     1789        cbBackendCopy = AUD_write (pThis->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
    17881790        hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
    17891791    }
    … …  
    17911793    {
    17921794        /* Not enough bytes to be processed and reported, we'll try our luck next time around */
    1793         hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
     1795        hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
    17941796        *fStop = true;
    17951797    }
    17961798
    17971799l_done:
    1798     Assert((cbTransferred <= (SDFIFOS(pState, 4) + 1)));
     1800    Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
    17991801    Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
    18001802    return cbTransferred;
    … …  
    18061808DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
    18071809{
    1808     INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pvHDAState;
     1810    PHDASTATE pThis = (INTELHDLinkState *)pCodecState->pvHDAState;
    18091811    return VINF_SUCCESS;
    18101812}
    18111813
    1812 DECLINLINE(void) hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm,
     1814DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
    18131815                                           PHDASTREAMTRANSFERDESC pStreamDesc)
    18141816{
    1815     Assert(pState); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
     1817    Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
    18161818
    18171819    memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
    18181820    pStreamDesc->u8Strm     = u8Strm;
    1819     pStreamDesc->u32Ctl     = HDA_STREAM_REG2(pState, CTL, u8Strm);
    1820     pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
    1821                                           HDA_STREAM_REG2(pState, BDPU, u8Strm));
    1822     pStreamDesc->pu32Lpib   = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
    1823     pStreamDesc->pu32Sts    = &HDA_STREAM_REG2(pState, STS, u8Strm);
    1824     pStreamDesc->u32Cbl     = HDA_STREAM_REG2(pState, CBL, u8Strm);
    1825     pStreamDesc->u32Fifos   = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
    1826 
    1827     pBdle->u32BdleMaxCvi    = HDA_STREAM_REG2(pState, LVI, u8Strm);
     1821    pStreamDesc->u32Ctl     = HDA_STREAM_REG2(pThis, CTL, u8Strm);
     1822    pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pThis, BDPL, u8Strm),
     1823                                          HDA_STREAM_REG2(pThis, BDPU, u8Strm));
     1824    pStreamDesc->pu32Lpib   = &HDA_STREAM_REG2(pThis, LPIB, u8Strm);
     1825    pStreamDesc->pu32Sts    = &HDA_STREAM_REG2(pThis, STS, u8Strm);
     1826    pStreamDesc->u32Cbl     = HDA_STREAM_REG2(pThis, CBL, u8Strm);
     1827    pStreamDesc->u32Fifos   = HDA_STREAM_REG2(pThis, FIFOS, u8Strm);
     1828
     1829    pBdle->u32BdleMaxCvi    = HDA_STREAM_REG2(pThis, LVI, u8Strm);
    18281830
    18291831#ifdef LOG_ENABLED
    … …  
    18321834    {
    18331835        Log(("Initialization of transfer descriptor:\n"));
    1834         dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
     1836        dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
    18351837    }
    18361838#endif
    … …  
    18431845static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
    18441846{
    1845     INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pvHDAState;
     1847    PHDASTATE pThis = (INTELHDLinkState *)pCodecState->pvHDAState;
    18461848    uint8_t                 u8Strm = 0;
    18471849    PHDABDLEDESC            pBdle = NULL;
    … …  
    18521854        {
    18531855            u8Strm = 4;
    1854             pBdle = &pState->StOutBdle;
     1856            pBdle = &pThis->StOutBdle;
    18551857            break;
    18561858        }
    … …  
    18581860        {
    18591861            u8Strm = 0;
    1860             pBdle = &pState->StInBdle;
     1862            pBdle = &pThis->StInBdle;
    18611863            break;
    18621864        }
    … …  
    18661868
    18671869    HDASTREAMTRANSFERDESC StreamDesc;
    1868     hdaInitTransferDescriptor(pState, pBdle, u8Strm, &StreamDesc);
     1870    hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
    18691871
    18701872    bool fStop = false;
    … …  
    18771879        /* Fetch the Buffer Descriptor Entry (BDE). */
    18781880
    1879         if (hdaIsTransferCountersOverlapped(pState, pBdle, &StreamDesc))
    1880             hdaFetchBdle(pState, pBdle, &StreamDesc);
     1881        if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
     1882            hdaFetchBdle(pThis, pBdle, &StreamDesc);
    18811883        *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
    18821884        Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
    18831885        uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
    1884         Assert((u32CblLimit > hdaFifoWToSz(pState, &StreamDesc)));
     1886        Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
    18851887        Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
    18861888        uint32_t cb;
    … …  
    18881890        {
    18891891            case PO_INDEX:
    1890                 cb = hdaWriteAudio(pState, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
     1892                cb = hdaWriteAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
    18911893                break;
    18921894            case PI_INDEX:
    1893                 cb = hdaReadAudio(pState, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
     1895                cb = hdaReadAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
    18941896                break;
    18951897            default:
    … …  
    19021904
    19031905        /* Process end of buffer condition. */
    1904         hdaStreamCounterUpdate(pState, pBdle, &StreamDesc, cb);
    1905         fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &StreamDesc) : fStop;
     1906        hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cb);
     1907        fStop = !fStop ? !hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc) : fStop;
    19061908    }
    19071909}
    … …  
    19201922{
    19211923    PHDASTATE   pThis  = PDMINS_2_DATA(pDevIns, PHDASTATE);
    1922     uint32_t    offReg = GCPhysAddr - pThis->addrMMReg;
     1924    uint32_t    offReg = GCPhysAddr - pThis->MMIOBaseAddr;
    19231925    int         idxReg = hdaMMIORegLookup(pThis, offReg);
    19241926    int         rc;
    … …  
    19511953{
    19521954    PHDASTATE   pThis  = PDMINS_2_DATA(pDevIns, PHDASTATE);
    1953     uint32_t    offReg = GCPhysAddr - pThis->addrMMReg;
     1955    uint32_t    offReg = GCPhysAddr - pThis->MMIOBaseAddr;
    19541956    int         idxReg = hdaMMIORegLookup(pThis, offReg);
    19551957    int         rc;
    … …  
    20012003        return rc;
    20022004
    2003     pThis->addrMMReg = GCPhysAddress;
     2005    pThis->MMIOBaseAddr = GCPhysAddress;
    20042006    return VINF_SUCCESS;
    20052007}
    … …  
    22102212
    22112213
    2212 static int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
     2214static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
    22132215{
    22142216    int iReg = 0;
    … …  
    22202222
    22212223
    2222 static void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
    2223 {
    2224     Assert(   pState
     2224static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
     2225{
     2226    Assert(   pThis
    22252227           && iHdaIndex >= 0
    22262228           && iHdaIndex < HDA_NREGS);
    2227     pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aIchIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
     2229    pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aIchIntelHDRegMap[iHdaIndex].abbrev, pThis->au32Regs[iHdaIndex]);
    22282230}
    22292231
    … …  
    22442246
    22452247
    2246 static void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
    2247 {
    2248     Assert(   pState
     2248static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
     2249{
     2250    Assert(   pThis
    22492251           && iHdaStrmIndex >= 0
    22502252           && iHdaStrmIndex < 7);
    22512253    pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
    2252     pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
    2253     pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
    2254     pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
    2255     pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
    2256 }
    2257 
    2258 
    2259 static int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
     2254    pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, CTL, iHdaStrmIndex));
     2255    pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, STS, iHdaStrmIndex));
     2256    pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOS, iHdaStrmIndex));
     2257    pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOW, iHdaStrmIndex));
     2258}
     2259
     2260
     2261static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
    22602262{
    22612263    /* todo: add args parsing */
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