Changeset 44645 in vbox for trunk/src/VBox/Devices/Audio
- Timestamp:
- Feb 11, 2013 8:04:41 PM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 83733
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
r44644 r44645 587 587 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" }, 588 588 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" }, 589 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 ,hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },589 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" }, 590 590 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" }, 591 591 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" }, … … 796 796 { 797 797 #ifdef DEBUG_vvl 798 799 798 Assert( idxHigh >= 0 799 && idxLow >= 0); 800 800 #endif 801 802 803 804 805 806 807 808 809 810 && offReg <g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size)811 801 if ( idxHigh < idxLow 802 || idxHigh < 0) 803 break; 804 int idxMiddle = idxLow + (idxHigh - idxLow) / 2; 805 if (offReg < g_aIchIntelHDRegMap[idxMiddle].offset) 806 idxHigh = idxMiddle - 1; 807 else if (offReg >= g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size) 808 idxLow = idxMiddle + 1; 809 else if ( offReg >= g_aIchIntelHDRegMap[idxMiddle].offset 810 && offReg < g_aIchIntelHDRegMap[idxMiddle].offset + g_aIchIntelHDRegMap[idxMiddle].size) 811 return idxMiddle; 812 812 } 813 813 return -1; … … 1362 1362 { 1363 1363 #ifdef VBOX_WITH_HDA_CODEC_EMU 1364 /* @todo a bit more investigation is required here. */1364 /** @todo a bit more investigation is required here. */ 1365 1365 int rc = 0; 1366 1366 audsettings_t as; … … 1477 1477 { 1478 1478 case ICH6_HDA_REG_CORBLBASE: 1479 pThis->u64CORBBase &= 0xFFFFFFFF00000000ULL;1479 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000); 1480 1480 pThis->u64CORBBase |= pThis->au32Regs[iReg]; 1481 1481 break; 1482 1482 case ICH6_HDA_REG_CORBUBASE: 1483 pThis->u64CORBBase &= 0x00000000FFFFFFFFULL;1483 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF); 1484 1484 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32); 1485 1485 break; 1486 1486 case ICH6_HDA_REG_RIRLBASE: 1487 pThis->u64RIRBBase &= 0xFFFFFFFF00000000ULL;1487 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000); 1488 1488 pThis->u64RIRBBase |= pThis->au32Regs[iReg]; 1489 1489 break; 1490 1490 case ICH6_HDA_REG_RIRUBASE: 1491 pThis->u64RIRBBase &= 0x00000000FFFFFFFFULL;1491 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF); 1492 1492 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32); 1493 1493 break; 1494 1494 case ICH6_HDA_REG_DPLBASE: 1495 /* @todo: first bit has special meaning */1496 pThis->u64DPBase &= 0xFFFFFFFF00000000ULL;1495 /** @todo: first bit has special meaning */ 1496 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000); 1497 1497 pThis->u64DPBase |= pThis->au32Regs[iReg]; 1498 1498 break; 1499 1499 case ICH6_HDA_REG_DPUBASE: 1500 pThis->u64DPBase &= 0x00000000FFFFFFFFULL;1500 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF); 1501 1501 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iReg] << 32); 1502 1502 break; … … 1698 1698 && pBdle->fBdleCviIoc) 1699 1699 { 1700 /* 1700 /** 1701 1701 * @todo - more carefully investigate BCIS flag. 1702 1702 * Speech synthesis works fine on Mac Guest if this bit isn't set … … 2432 2432 N_ ("Invalid configuration for the Intel HDA device")); 2433 2433 2434 // **@todo r=michaln: This device may need R0/RC enabling, especially if guests2435 // poll some register(pThis).2434 /// @todo r=michaln: This device may need R0/RC enabling, especially if guests 2435 /// poll some register(pThis). 2436 2436 2437 2437 /*
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