VirtualBox

Changeset 44890 in vbox for trunk


Ignore:
Timestamp:
Mar 1, 2013 4:14:47 PM (12 years ago)
Author:
vboxsync
Message:

DevPCNet.cpp: Started cleanups.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Network/DevPCNet.cpp

    r44528 r44890  
    7070#include "VBoxDD.h"
    7171
     72
     73/*******************************************************************************
     74*   Defined Constants And Macros                                               *
     75*******************************************************************************/
    7276/* Enable this to catch writes to the ring descriptors instead of using excessive polling */
    7377/* #define PCNET_NO_POLLING */
    … …  
    9599#define CSR_MAX_REG                     128
    96100
    97 /* Maximum number of times we report a link down to the guest (failure to send frame) */
     101/** Maximum number of times we report a link down to the guest (failure to send frame) */
    98102#define PCNET_MAX_LINKDOWN_REPORTED     3
    99103
    100 /* Maximum frame size we handle */
     104/** Maximum frame size we handle */
    101105#define MAX_FRAME                       1536
    102106
    103 
    104 typedef struct PCNetState_st PCNetState;
    105 
     107#define PCNETSTATE_2_DEVINS(pPCNet)            ((pPCNet)->CTX_SUFF(pDevIns))
     108#define PCIDEV_2_PCNETSTATE(pPciDev)           RT_FROM_MEMBER((pPciDev), PCNETSTATE, PciDev)
     109#define PCNET_INST_NR                          (PCNETSTATE_2_DEVINS(pThis)->iInstance)
     110
     111/** @name Bus configuration registers
     112 * @{ */
     113#define BCR_MSRDA       0
     114#define BCR_MSWRA       1
     115#define BCR_MC          2
     116#define BCR_RESERVED3   3
     117#define BCR_LNKST       4
     118#define BCR_LED1        5
     119#define BCR_LED2        6
     120#define BCR_LED3        7
     121#define BCR_RESERVED8   8
     122#define BCR_FDC         9
     123/* 10 - 15 = reserved */
     124#define BCR_IOBASEL     16  /* Reserved */
     125#define BCR_IOBASEU     16  /* Reserved */
     126#define BCR_BSBC        18
     127#define BCR_EECAS       19
     128#define BCR_SWS         20
     129#define BCR_INTCON      21  /* Reserved */
     130#define BCR_PLAT        22
     131#define BCR_PCISVID     23
     132#define BCR_PCISID      24
     133#define BCR_SRAMSIZ     25
     134#define BCR_SRAMB       26
     135#define BCR_SRAMIC      27
     136#define BCR_EBADDRL     28
     137#define BCR_EBADDRU     29
     138#define BCR_EBD         30
     139#define BCR_STVAL       31
     140#define BCR_MIICAS      32
     141#define BCR_MIIADDR     33
     142#define BCR_MIIMDR      34
     143#define BCR_PCIVID      35
     144#define BCR_PMC_A       36
     145#define BCR_DATA0       37
     146#define BCR_DATA1       38
     147#define BCR_DATA2       39
     148#define BCR_DATA3       40
     149#define BCR_DATA4       41
     150#define BCR_DATA5       42
     151#define BCR_DATA6       43
     152#define BCR_DATA7       44
     153#define BCR_PMR1        45
     154#define BCR_PMR2        46
     155#define BCR_PMR3        47
     156/** @}  */
     157
     158/** @name Bus configuration sub register accessors.
     159 * @{ */
     160#define BCR_DWIO(S)      !!((S)->aBCR[BCR_BSBC] & 0x0080)
     161#define BCR_SSIZE32(S)   !!((S)->aBCR[BCR_SWS ] & 0x0100)
     162#define BCR_SWSTYLE(S)     ((S)->aBCR[BCR_SWS ] & 0x00FF)
     163/** @} */
     164
     165/** @name CSR subregister accessors.
     166 * @{ */
     167#define CSR_INIT(S)      !!((S)->aCSR[0] & 0x0001)  /**< Init assertion */
     168#define CSR_STRT(S)      !!((S)->aCSR[0] & 0x0002)  /**< Start assertion */
     169#define CSR_STOP(S)      !!((S)->aCSR[0] & 0x0004)  /**< Stop assertion */
     170#define CSR_TDMD(S)      !!((S)->aCSR[0] & 0x0008)  /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */
     171#define CSR_TXON(S)      !!((S)->aCSR[0] & 0x0010)  /**< Transmit on (readonly) */
     172#define CSR_RXON(S)      !!((S)->aCSR[0] & 0x0020)  /**< Receive On */
     173#define CSR_INEA(S)      !!((S)->aCSR[0] & 0x0040)  /**< Interrupt Enable */
     174#define CSR_LAPPEN(S)    !!((S)->aCSR[3] & 0x0020)  /**< Look Ahead Packet Processing Enable */
     175#define CSR_DXSUFLO(S)   !!((S)->aCSR[3] & 0x0040)  /**< Disable Transmit Stop on Underflow error */
     176#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400)  /**< Auto Strip Receive */
     177#define CSR_DPOLL(S)     !!((S)->aCSR[4] & 0x1000)  /**< Disable Transmit Polling */
     178#define CSR_SPND(S)      !!((S)->aCSR[5] & 0x0001)  /**< Suspend */
     179#define CSR_LTINTEN(S)   !!((S)->aCSR[5] & 0x4000)  /**< Last Transmit Interrupt Enable */
     180#define CSR_TOKINTD(S)   !!((S)->aCSR[5] & 0x8000)  /**< Transmit OK Interrupt Disable */
     181
     182#define CSR_STINT        !!((S)->aCSR[7] & 0x0800)  /**< Software Timer Interrupt */
     183#define CSR_STINTE       !!((S)->aCSR[7] & 0x0400)  /**< Software Timer Interrupt Enable */
     184
     185#define CSR_DRX(S)       !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */
     186#define CSR_DTX(S)       !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */
     187#define CSR_LOOP(S)      !!((S)->aCSR[15] & 0x0004) /**< Loopback Enable */
     188#define CSR_DRCVPA(S)    !!((S)->aCSR[15] & 0x2000) /**< Disable Receive Physical Address */
     189#define CSR_DRCVBC(S)    !!((S)->aCSR[15] & 0x4000) /**< Disable Receive Broadcast */
     190#define CSR_PROM(S)      !!((S)->aCSR[15] & 0x8000) /**< Promiscuous Mode */
     191/** @} */
     192
     193#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
     194# error fix macros (and more in this file) for big-endian machines
     195#endif
     196
     197/** @name CSR register accessors.
     198 * @{ */
     199#define CSR_IADR(S)  (*(uint32_t*)((S)->aCSR +  1)) /**< Initialization Block Address */
     200#define CSR_CRBA(S)  (*(uint32_t*)((S)->aCSR + 18)) /**< Current Receive Buffer Address */
     201#define CSR_CXBA(S)  (*(uint32_t*)((S)->aCSR + 20)) /**< Current Transmit Buffer Address */
     202#define CSR_NRBA(S)  (*(uint32_t*)((S)->aCSR + 22)) /**< Next Receive Buffer Address */
     203#define CSR_BADR(S)  (*(uint32_t*)((S)->aCSR + 24)) /**< Base Address of Receive Ring */
     204#define CSR_NRDA(S)  (*(uint32_t*)((S)->aCSR + 26)) /**< Next Receive Descriptor Address */
     205#define CSR_CRDA(S)  (*(uint32_t*)((S)->aCSR + 28)) /**< Current Receive Descriptor Address */
     206#define CSR_BADX(S)  (*(uint32_t*)((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */
     207#define CSR_NXDA(S)  (*(uint32_t*)((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */
     208#define CSR_CXDA(S)  (*(uint32_t*)((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */
     209#define CSR_NNRD(S)  (*(uint32_t*)((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */
     210#define CSR_NNXD(S)  (*(uint32_t*)((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */
     211#define CSR_CRBC(S)  ((S)->aCSR[40])                /**< Current Receive Byte Count */
     212#define CSR_CRST(S)  ((S)->aCSR[41])                /**< Current Receive Status */
     213#define CSR_CXBC(S)  ((S)->aCSR[42])                /**< Current Transmit Byte Count */
     214#define CSR_CXST(S)  ((S)->aCSR[43])                /**< Current transmit status */
     215#define CSR_NRBC(S)  ((S)->aCSR[44])                /**< Next Receive Byte Count */
     216#define CSR_NRST(S)  ((S)->aCSR[45])                /**< Next Receive Status */
     217#define CSR_POLL(S)  ((S)->aCSR[46])                /**< Transmit Poll Time Counter */
     218#define CSR_PINT(S)  ((S)->aCSR[47])                /**< Transmit Polling Interval */
     219#define CSR_PXDA(S)  (*(uint32_t*)((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/
     220#define CSR_PXBC(S)  ((S)->aCSR[62])                /**< Previous Transmit Byte Count */
     221#define CSR_PXST(S)  ((S)->aCSR[63])                /**< Previous Transmit Status */
     222#define CSR_NXBA(S)  (*(uint32_t*)((S)->aCSR + 64)) /**< Next Transmit Buffer Address */
     223#define CSR_NXBC(S)  ((S)->aCSR[66])                /**< Next Transmit Byte Count */
     224#define CSR_NXST(S)  ((S)->aCSR[67])                /**< Next Transmit Status */
     225#define CSR_RCVRC(S) ((S)->aCSR[72])                /**< Receive Descriptor Ring Counter */
     226#define CSR_XMTRC(S) ((S)->aCSR[74])                /**< Transmit Descriptor Ring Counter */
     227#define CSR_RCVRL(S) ((S)->aCSR[76])                /**< Receive Descriptor Ring Length */
     228#define CSR_XMTRL(S) ((S)->aCSR[78])                /**< Transmit Descriptor Ring Length */
     229#define CSR_MISSC(S) ((S)->aCSR[112])               /**< Missed Frame Count */
     230/** @} */
     231
     232/** @name Version for the PCnet/FAST III 79C973 card
     233 * @{ */
     234#define CSR_VERSION_LOW_79C973  0x5003  /* the lower two bits must be 11b for AMD */
     235#define CSR_VERSION_LOW_79C970A 0x1003  /* the lower two bits must be 11b for AMD */
     236#define CSR_VERSION_HIGH        0x0262
     237/** @}  */
     238
     239/** Calculates the full physical address.  */
     240#define PHYSADDR(S,A) ((A) | (S)->GCUpperPhys)
     241
     242
     243/*******************************************************************************
     244*   Structures and Typedefs                                                    *
     245*******************************************************************************/
    106246/**
    107247 * PCNET state.
    … …  
    113253 * @implements  PDMILEDPORTS
    114254 */
    115 struct PCNetState_st
     255typedef struct PCNetState_st
    116256{
    117257    PCIDEVICE                           PciDev;
    … …  
    328468# endif
    329469#endif /* VBOX_WITH_STATISTICS */
    330 };
     470} PCNetState, PCNETSTATE;
    331471//AssertCompileMemberAlignment(PCNetState, StatReceiveBytes, 8);
    332 
    333 #define PCNETSTATE_2_DEVINS(pPCNet)            ((pPCNet)->CTX_SUFF(pDevIns))
    334 #define PCIDEV_2_PCNETSTATE(pPciDev)           ((PCNetState *)(pPciDev))
    335 #define PCNET_INST_NR                          (PCNETSTATE_2_DEVINS(pThis)->iInstance)
    336 
    337 /* BUS CONFIGURATION REGISTERS */
    338 #define BCR_MSRDA       0
    339 #define BCR_MSWRA       1
    340 #define BCR_MC          2
    341 #define BCR_RESERVED3   3
    342 #define BCR_LNKST       4
    343 #define BCR_LED1        5
    344 #define BCR_LED2        6
    345 #define BCR_LED3        7
    346 #define BCR_RESERVED8   8
    347 #define BCR_FDC         9
    348 /* 10 - 15 = reserved */
    349 #define BCR_IOBASEL     16  /* Reserved */
    350 #define BCR_IOBASEU     16  /* Reserved */
    351 #define BCR_BSBC        18
    352 #define BCR_EECAS       19
    353 #define BCR_SWS         20
    354 #define BCR_INTCON      21  /* Reserved */
    355 #define BCR_PLAT        22
    356 #define BCR_PCISVID     23
    357 #define BCR_PCISID      24
    358 #define BCR_SRAMSIZ     25
    359 #define BCR_SRAMB       26
    360 #define BCR_SRAMIC      27
    361 #define BCR_EBADDRL     28
    362 #define BCR_EBADDRU     29
    363 #define BCR_EBD         30
    364 #define BCR_STVAL       31
    365 #define BCR_MIICAS      32
    366 #define BCR_MIIADDR     33
    367 #define BCR_MIIMDR      34
    368 #define BCR_PCIVID      35
    369 #define BCR_PMC_A       36
    370 #define BCR_DATA0       37
    371 #define BCR_DATA1       38
    372 #define BCR_DATA2       39
    373 #define BCR_DATA3       40
    374 #define BCR_DATA4       41
    375 #define BCR_DATA5       42
    376 #define BCR_DATA6       43
    377 #define BCR_DATA7       44
    378 #define BCR_PMR1        45
    379 #define BCR_PMR2        46
    380 #define BCR_PMR3        47
    381 
    382 #define BCR_DWIO(S)      !!((S)->aBCR[BCR_BSBC] & 0x0080)
    383 #define BCR_SSIZE32(S)   !!((S)->aBCR[BCR_SWS ] & 0x0100)
    384 #define BCR_SWSTYLE(S)     ((S)->aBCR[BCR_SWS ] & 0x00FF)
    385 
    386 #define CSR_INIT(S)      !!((S)->aCSR[0] & 0x0001)  /**< Init assertion */
    387 #define CSR_STRT(S)      !!((S)->aCSR[0] & 0x0002)  /**< Start assertion */
    388 #define CSR_STOP(S)      !!((S)->aCSR[0] & 0x0004)  /**< Stop assertion */
    389 #define CSR_TDMD(S)      !!((S)->aCSR[0] & 0x0008)  /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */
    390 #define CSR_TXON(S)      !!((S)->aCSR[0] & 0x0010)  /**< Transmit on (readonly) */
    391 #define CSR_RXON(S)      !!((S)->aCSR[0] & 0x0020)  /**< Receive On */
    392 #define CSR_INEA(S)      !!((S)->aCSR[0] & 0x0040)  /**< Interrupt Enable */
    393 #define CSR_LAPPEN(S)    !!((S)->aCSR[3] & 0x0020)  /**< Look Ahead Packet Processing Enable */
    394 #define CSR_DXSUFLO(S)   !!((S)->aCSR[3] & 0x0040)  /**< Disable Transmit Stop on Underflow error */
    395 #define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400)  /**< Auto Strip Receive */
    396 #define CSR_DPOLL(S)     !!((S)->aCSR[4] & 0x1000)  /**< Disable Transmit Polling */
    397 #define CSR_SPND(S)      !!((S)->aCSR[5] & 0x0001)  /**< Suspend */
    398 #define CSR_LTINTEN(S)   !!((S)->aCSR[5] & 0x4000)  /**< Last Transmit Interrupt Enable */
    399 #define CSR_TOKINTD(S)   !!((S)->aCSR[5] & 0x8000)  /**< Transmit OK Interrupt Disable */
    400 
    401 #define CSR_STINT        !!((S)->aCSR[7] & 0x0800)  /**< Software Timer Interrupt */
    402 #define CSR_STINTE       !!((S)->aCSR[7] & 0x0400)  /**< Software Timer Interrupt Enable */
    403 
    404 #define CSR_DRX(S)       !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */
    405 #define CSR_DTX(S)       !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */
    406 #define CSR_LOOP(S)      !!((S)->aCSR[15] & 0x0004) /**< Loopback Enable */
    407 #define CSR_DRCVPA(S)    !!((S)->aCSR[15] & 0x2000) /**< Disable Receive Physical Address */
    408 #define CSR_DRCVBC(S)    !!((S)->aCSR[15] & 0x4000) /**< Disable Receive Broadcast */
    409 #define CSR_PROM(S)      !!((S)->aCSR[15] & 0x8000) /**< Promiscuous Mode */
    410 
    411 #if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
    412 #error fix macros (and more in this file) for big-endian machines
    413 #endif
    414 
    415 #define CSR_IADR(S)  (*(uint32_t*)((S)->aCSR +  1)) /**< Initialization Block Address */
    416 #define CSR_CRBA(S)  (*(uint32_t*)((S)->aCSR + 18)) /**< Current Receive Buffer Address */
    417 #define CSR_CXBA(S)  (*(uint32_t*)((S)->aCSR + 20)) /**< Current Transmit Buffer Address */
    418 #define CSR_NRBA(S)  (*(uint32_t*)((S)->aCSR + 22)) /**< Next Receive Buffer Address */
    419 #define CSR_BADR(S)  (*(uint32_t*)((S)->aCSR + 24)) /**< Base Address of Receive Ring */
    420 #define CSR_NRDA(S)  (*(uint32_t*)((S)->aCSR + 26)) /**< Next Receive Descriptor Address */
    421 #define CSR_CRDA(S)  (*(uint32_t*)((S)->aCSR + 28)) /**< Current Receive Descriptor Address */
    422 #define CSR_BADX(S)  (*(uint32_t*)((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */
    423 #define CSR_NXDA(S)  (*(uint32_t*)((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */
    424 #define CSR_CXDA(S)  (*(uint32_t*)((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */
    425 #define CSR_NNRD(S)  (*(uint32_t*)((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */
    426 #define CSR_NNXD(S)  (*(uint32_t*)((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */
    427 #define CSR_CRBC(S)  ((S)->aCSR[40])                /**< Current Receive Byte Count */
    428 #define CSR_CRST(S)  ((S)->aCSR[41])                /**< Current Receive Status */
    429 #define CSR_CXBC(S)  ((S)->aCSR[42])                /**< Current Transmit Byte Count */
    430 #define CSR_CXST(S)  ((S)->aCSR[43])                /**< Current transmit status */
    431 #define CSR_NRBC(S)  ((S)->aCSR[44])                /**< Next Receive Byte Count */
    432 #define CSR_NRST(S)  ((S)->aCSR[45])                /**< Next Receive Status */
    433 #define CSR_POLL(S)  ((S)->aCSR[46])                /**< Transmit Poll Time Counter */
    434 #define CSR_PINT(S)  ((S)->aCSR[47])                /**< Transmit Polling Interval */
    435 #define CSR_PXDA(S)  (*(uint32_t*)((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/
    436 #define CSR_PXBC(S)  ((S)->aCSR[62])                /**< Previous Transmit Byte Count */
    437 #define CSR_PXST(S)  ((S)->aCSR[63])                /**< Previous Transmit Status */
    438 #define CSR_NXBA(S)  (*(uint32_t*)((S)->aCSR + 64)) /**< Next Transmit Buffer Address */
    439 #define CSR_NXBC(S)  ((S)->aCSR[66])                /**< Next Transmit Byte Count */
    440 #define CSR_NXST(S)  ((S)->aCSR[67])                /**< Next Transmit Status */
    441 #define CSR_RCVRC(S) ((S)->aCSR[72])                /**< Receive Descriptor Ring Counter */
    442 #define CSR_XMTRC(S) ((S)->aCSR[74])                /**< Transmit Descriptor Ring Counter */
    443 #define CSR_RCVRL(S) ((S)->aCSR[76])                /**< Receive Descriptor Ring Length */
    444 #define CSR_XMTRL(S) ((S)->aCSR[78])                /**< Transmit Descriptor Ring Length */
    445 #define CSR_MISSC(S) ((S)->aCSR[112])               /**< Missed Frame Count */
    446 
    447 #define PHYSADDR(S,A) ((A) | (S)->GCUpperPhys)
    448 
    449 /* Version for the PCnet/FAST III 79C973 card */
    450 #define CSR_VERSION_LOW_79C973  0x5003  /* the lower two bits must be 11b for AMD */
    451 #define CSR_VERSION_LOW_79C970A 0x1003  /* the lower two bits must be 11b for AMD */
    452 #define CSR_VERSION_HIGH        0x0262
     472/** Pointer to a PC-Net state structure. */
     473typedef PCNETSTATE *PPCNETSTATE;
    453474
    454475/** @todo All structs: big endian? */
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