VirtualBox

Changeset 44897 in vbox


Ignore:
Timestamp:
Mar 1, 2013 9:44:24 PM (12 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
84067
Message:

Cleanups related to pci bus master memory access (#1871).

Location:
trunk
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/err.h

    r44528 r44897  
    12271227 * misconfiguration or in rare cases a buggy pci device. */
    12281228#define VERR_PDM_NO_PCI_BUS                         (-2833)
    1229 /** PCI physical read with bus mastering disabled. */
    1230 #define VINF_PDM_PCI_PHYS_READ_BM_DISABLED          (2833)
    12311229/** The device is not a registered PCI device and thus cannot
    12321230 * perform any PCI operations. The device forgot to register it self. */
    12331231#define VERR_PDM_NOT_PCI_DEVICE                     (-2834)
    1234 /** PCI physical write with bus mastering disabled. */
    1235 #define VINF_PDM_PCI_PHYS_WRITE_BM_DISABLED         (2834)
    12361232
    12371233/** The version of the device registration structure is unknown
    … …  
    14011397 *  present). */
    14021398#define VERR_PDM_CANNOT_TRANSFORM_REMOVED_DRIVER    (-2890)
     1399/** The PCI device isn't configured as a busmaster, physical memory access
     1400 * rejected. */
     1401#define VERR_PDM_NOT_PCI_BUS_MASTER                 (-2891)
    14031402/** @} */
    14041403

  • trunk/include/VBox/vmm/pdmdev.h

    r44896 r44897  
    28812881
    28822882    /**
    2883      * Reads data via bus mastering, if enabled. If no bus mastering is available,
    2884      * this function does nothing and returns VINF_PGM_PCI_PHYS_READ_BM_DISABLED.
    2885      *
    2886      * @return  IPRT status code.
    2887      */
    2888     DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
    2889 
    2890     /**
    2891      * Writes data via bus mastering, if enabled. If no bus mastering is available,
    2892      * this function does nothing and returns VINF_PGM_PCI_PHYS_WRITE_BM_DISABLED.
    2893      *
    2894      * @return  IPRT status code.
    2895      */
    2896     DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
    2897 
    2898     /**
    28992883     * Registers the device with the default PCI bus.
    29002884     *
    … …  
    29552939
    29562940    /**
     2941     * Bus master physical memory read.
     2942     *
     2943     * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
     2944     *          VERR_EM_MEMORY.  The informational status shall NOT be propagated!
     2945     * @param   pDevIns             The device instance.
     2946     * @param   GCPhys              Physical address start reading from.
     2947     * @param   pvBuf               Where to put the read bits.
     2948     * @param   cbRead              How many bytes to read.
     2949     * @thread  Any thread, but the call may involve the emulation thread.
     2950     */
     2951    DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
     2952
     2953    /**
     2954     * Bus master physical memory write.
     2955     *
     2956     * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
     2957     *          VERR_EM_MEMORY.  The informational status shall NOT be propagated!
     2958     * @param   pDevIns             The device instance.
     2959     * @param   GCPhys              Physical address to write to.
     2960     * @param   pvBuf               What to write.
     2961     * @param   cbWrite             How many bytes to write.
     2962     * @thread  Any thread, but the call may involve the emulation thread.
     2963     */
     2964    DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
     2965
     2966    /**
    29572967     * Set the IRQ for a PCI device.
    29582968     *
    … …  
    35813591
    35823592/** Current PDMDEVHLPR3 version number. */
    3583 #define PDM_DEVHLPR3_VERSION                    PDM_VERSION_MAKE(0xffe7, 10, 0)
     3593#define PDM_DEVHLPR3_VERSION                    PDM_VERSION_MAKE(0xffe7, 11, 0)
    35843594
    35853595
    … …  
    35933603
    35943604    /**
    3595      * Reads data via bus mastering, if enabled. If no bus mastering is available,
    3596      * this function does nothing and returns VINF_PGM_PCI_PHYS_READ_BM_DISABLED.
    3597      *
    3598      * @return  IPRT status code.
    3599      */
    3600     DECLRCCALLBACKMEMBER(int, pfnPCIDevPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
    3601 
    3602     /**
    3603      * Writes data via bus mastering, if enabled. If no bus mastering is available,
    3604      * this function does nothing and returns VINF_PGM_PCI_PHYS_WRITE_BM_DISABLED.
    3605      *
    3606      * @return  IPRT status code.
    3607      */
    3608     DECLRCCALLBACKMEMBER(int, pfnPCIDevPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
     3605     * Bus master physical memory read.
     3606     *
     3607     * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
     3608     *          VERR_EM_MEMORY.  The informational status shall NOT be propagated!
     3609     * @param   pDevIns             The device instance.
     3610     * @param   GCPhys              Physical address start reading from.
     3611     * @param   pvBuf               Where to put the read bits.
     3612     * @param   cbRead              How many bytes to read.
     3613     * @thread  Any thread, but the call may involve the emulation thread.
     3614     */
     3615    DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
     3616
     3617    /**
     3618     * Bus master physical memory write.
     3619     *
     3620     * @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
     3621     *          VERR_EM_MEMORY.  The informational status shall NOT be propagated!
     3622     * @param   pDevIns             The device instance.
     3623     * @param   GCPhys              Physical address to write to.
     3624     * @param   pvBuf               What to write.
     3625     * @param   cbWrite             How many bytes to write.
     3626     * @thread  Any thread, but the call may involve the emulation thread.
     3627     */
     3628    DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
    36093629
    36103630    /**
    … …  
    37883808
    37893809/** Current PDMDEVHLP version number. */
    3790 #define PDM_DEVHLPRC_VERSION                    PDM_VERSION_MAKE(0xffe6, 3, 0)
     3810#define PDM_DEVHLPRC_VERSION                    PDM_VERSION_MAKE(0xffe6, 3, 1)
    37913811
    37923812
    … …  
    38003820
    38013821    /**
    3802      * Reads data via bus mastering, if enabled. If no bus mastering is available,
    3803      * this function does nothing and returns VINF_PGM_PCI_PHYS_READ_BM_DISABLED.
    3804      *
    3805      * @return  IPRT status code.
     3822     * Bus master physical memory read.
     3823     *
     3824     * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
     3825     *          VERR_EM_MEMORY.
     3826     * @param   pDevIns             The device instance.
     3827     * @param   GCPhys              Physical address start reading from.
     3828     * @param   pvBuf               Where to put the read bits.
     3829     * @param   cbRead              How many bytes to read.
     3830     * @thread  Any thread, but the call may involve the emulation thread.
    38063831     */
    38073832    DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead));
    38083833
    38093834    /**
    3810      * Writes data via bus mastering, if enabled. If no bus mastering is available,
    3811      * this function does nothing and returns VINF_PGM_PCI_PHYS_WRITE_BM_DISABLED.
    3812      *
    3813      * @return  IPRT status code.
     3835     * Bus master physical memory write.
     3836     *
     3837     * @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
     3838     *          VERR_EM_MEMORY.
     3839     * @param   pDevIns             The device instance.
     3840     * @param   GCPhys              Physical address to write to.
     3841     * @param   pvBuf               What to write.
     3842     * @param   cbWrite             How many bytes to write.
     3843     * @thread  Any thread, but the call may involve the emulation thread.
    38143844     */
    38153845    DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite));
    … …  
    40034033
    40044034/** Current PDMDEVHLP version number. */
    4005 #define PDM_DEVHLPR0_VERSION                    PDM_VERSION_MAKE(0xffe5, 3, 0)
     4035#define PDM_DEVHLPR0_VERSION                    PDM_VERSION_MAKE(0xffe5, 3, 1)
    40064036
    40074037
    … …  
    47234753}
    47244754
    4725 /**
    4726  * Reads data via bus mastering, if enabled. If no bus mastering is available,
    4727  * this function does nothing and returns VINF_PGM_PCI_PHYS_READ_BM_DISABLED.
    4728  *
    4729  * @return  IPRT status code.
    4730  */
    4731 DECLINLINE(int) PDMDevHlpPCIDevPhysRead(PPCIDEVICE pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
    4732 {
    4733     AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
    4734     AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
    4735     AssertReturn(cbRead, VERR_INVALID_PARAMETER);
    4736 
    4737     if (!PCIDevIsBusmaster(pPciDev))
    4738     {
    4739 #ifdef DEBUG
    4740         Log2(("%s: %RU16:%RU16: No bus master (anymore), skipping read %p (%z)\n", __FUNCTION__,
    4741               PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbRead));
    4742 #endif
    4743         return VINF_PDM_PCI_PHYS_READ_BM_DISABLED;
    4744     }
    4745 
    4746     return PDMDevHlpPhysRead(pPciDev->pDevIns, GCPhys, pvBuf, cbRead);
    4747 }
    4748 
    4749 /**
    4750  * Writes data via bus mastering, if enabled. If no bus mastering is available,
    4751  * this function does nothing and returns VINF_PGM_PCI_PHYS_WRITE_BM_DISABLED.
    4752  *
    4753  * @return  IPRT status code.
    4754  */
    4755 DECLINLINE(int) PDMDevHlpPCIDevPhysWrite(PPCIDEVICE pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
    4756 {
    4757     AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
    4758     AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
    4759     AssertReturn(cbWrite, VERR_INVALID_PARAMETER);
    4760 
    4761     if (!PCIDevIsBusmaster(pPciDev))
    4762     {
    4763 #ifdef DEBUG
    4764         Log2(("%s: %RU16:%RU16: No bus master (anymore), skipping write %p (%z)\n", __FUNCTION__,
    4765               PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbWrite));
    4766 #endif
    4767         return VINF_PDM_PCI_PHYS_WRITE_BM_DISABLED;
    4768     }
    4769 
    4770     return PDMDevHlpPhysWrite(pPciDev->pDevIns, GCPhys, pvBuf, cbWrite);
    4771 }
    4772 
    47734755#endif /* IN_RING3 */
     4756
     4757/**
     4758 * @copydoc PDMDEVHLPR3::pfnPCIPhysRead
     4759 */
     4760DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
     4761{
     4762    return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
     4763}
     4764
     4765/**
     4766 * @copydoc PDMDEVHLPR3::pfnPCIPhysWrite
     4767 */
     4768DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
     4769{
     4770    return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
     4771}
    47744772
    47754773/**

  • trunk/src/VBox/Devices/Storage/DevATA.cpp

    r44516 r44897  
    48784878                AssertPtr(pATAState);
    48794879                if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
    4880                     PDMDevHlpPCIDevPhysWrite(&pATAState->dev, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
     4880                    PDMDevHlpPCIPhysWrite(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
    48814881                else
    4882                     PDMDevHlpPCIDevPhysRead(&pATAState->dev, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
     4882                    PDMDevHlpPCIPhysRead(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
    48834883
    48844884                iIOBufferCur += dmalen;

  • trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp

    r44528 r44897  
    55
    66/*
    7  * Copyright (C) 2006-2012 Oracle Corporation
     7 * Copyright (C) 2006-2013 Oracle Corporation
    88 *
    99 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    7878{
    7979    PDMDEV_ASSERT_DEVINS(pDevIns);
    80     LogFlow(("pdmR0DevHlp_PCIPhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
    81              pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
    82 
    83     PCIDevice *pPciDev = pDevIns->Internal.s.pPciDeviceR0;
    84     AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
     80
     81    /*
     82     * Just check the busmaster setting here and forward the request to the generic read helper.
     83     */
     84    PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
     85    AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
    8586
    8687    if (!PCIDevIsBusmaster(pPciDev))
    8788    {
    88 #ifdef DEBUG
    89         LogFlow(("%s: %RU16:%RU16: No bus master (anymore), skipping read %p (%z)\n", __FUNCTION__,
    90                  PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbRead));
    91 #endif
    92         return VINF_PDM_PCI_PHYS_READ_BM_DISABLED;
    93     }
    94 
    95     return pdmR0DevHlp_PhysRead(pDevIns, GCPhys, pvBuf, cbRead);
     89        Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#z\n",
     90             pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
     91        return VERR_PDM_NOT_PCI_BUS_MASTER;
     92    }
     93
     94    return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
    9695}
    9796
    … …  
    101100{
    102101    PDMDEV_ASSERT_DEVINS(pDevIns);
    103     LogFlow(("pdmR0DevHlp_PCIPhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
    104              pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
    105 
    106     PCIDevice *pPciDev = pDevIns->Internal.s.pPciDeviceR0;
    107     AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
     102
     103    /*
     104     * Just check the busmaster setting here and forward the request to the generic read helper.
     105     */
     106    PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
     107    AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
    108108
    109109    if (!PCIDevIsBusmaster(pPciDev))
    110110    {
    111 #ifdef DEBUG
    112         LogFlow(("%s: %RU16:%RU16: No bus master (anymore), skipping write %p (%z)\n", __FUNCTION__,
    113                  PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbWrite));
    114 #endif
    115         return VINF_PDM_PCI_PHYS_WRITE_BM_DISABLED;
    116     }
    117 
    118     return pdmR0DevHlp_PhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
     111        Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#z\n",
     112             pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
     113        return VERR_PDM_NOT_PCI_BUS_MASTER;
     114    }
     115
     116    return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
    119117}
    120118

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r44691 r44897  
    10821082
    10831083
    1084 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIDevPhysRead} */
    1085 static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
    1086 {
    1087     PDMDEV_ASSERT_DEVINS(pDevIns);
    1088     return PDMDevHlpPCIDevPhysRead(pDevIns->Internal.s.pPciDeviceR3, GCPhys, pvBuf, cbRead);
    1089 }
    1090 
    1091 
    1092 /** @interface_method_impl{PDMDEVHLPR3,pfnPCIDevPhysWrite} */
    1093 static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
    1094 {
    1095     PDMDEV_ASSERT_DEVINS(pDevIns);
    1096     return PDMDevHlpPCIDevPhysWrite(pDevIns->Internal.s.pPciDeviceR3, GCPhys, pvBuf, cbWrite);
    1097 }
    1098 
    1099 
    11001084/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister} */
    11011085static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev)
    … …  
    13651349
    13661350    LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
     1351}
     1352
     1353
     1354/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */
     1355static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
     1356{
     1357    PDMDEV_ASSERT_DEVINS(pDevIns);
     1358
     1359    /*
     1360     * Just check the busmaster setting here and forward the request to the generic read helper.
     1361     */
     1362    PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
     1363    AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
     1364
     1365    if (!PCIDevIsBusmaster(pPciDev))
     1366    {
     1367        Log(("pdmR3DevHlp_PCIPhysRead: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#z\n",
     1368             pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
     1369        return VERR_PDM_NOT_PCI_BUS_MASTER;
     1370    }
     1371
     1372    return pDevIns->pHlpR3->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
     1373}
     1374
     1375
     1376/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */
     1377static DECLCALLBACK(int) pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
     1378{
     1379    PDMDEV_ASSERT_DEVINS(pDevIns);
     1380
     1381    /*
     1382     * Just check the busmaster setting here and forward the request to the generic read helper.
     1383     */
     1384    PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
     1385    AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
     1386
     1387    if (!PCIDevIsBusmaster(pPciDev))
     1388    {
     1389        Log(("pdmR3DevHlp_PCIPhysWrite: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#z\n",
     1390             pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
     1391        return VERR_PDM_NOT_PCI_BUS_MASTER;
     1392    }
     1393
     1394    return pDevIns->pHlpR3->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
    13671395}
    13681396
    … …  
    33963424    pdmR3DevHlp_STAMRegisterF,
    33973425    pdmR3DevHlp_STAMRegisterV,
    3398     pdmR3DevHlp_PCIPhysRead,
    3399     pdmR3DevHlp_PCIPhysWrite,
    34003426    pdmR3DevHlp_PCIRegister,
    34013427    pdmR3DevHlp_PCIRegisterMsi,
    34023428    pdmR3DevHlp_PCIIORegionRegister,
    34033429    pdmR3DevHlp_PCISetConfigCallbacks,
     3430    pdmR3DevHlp_PCIPhysRead,
     3431    pdmR3DevHlp_PCIPhysWrite,
    34043432    pdmR3DevHlp_PCISetIrq,
    34053433    pdmR3DevHlp_PCISetIrqNoWait,
    … …  
    36273655    pdmR3DevHlp_STAMRegisterF,
    36283656    pdmR3DevHlp_STAMRegisterV,
    3629     pdmR3DevHlp_PCIPhysRead,
    3630     pdmR3DevHlp_PCIPhysWrite,
    36313657    pdmR3DevHlp_PCIRegister,
    36323658    pdmR3DevHlp_PCIRegisterMsi,
    36333659    pdmR3DevHlp_PCIIORegionRegister,
    36343660    pdmR3DevHlp_PCISetConfigCallbacks,
     3661    pdmR3DevHlp_PCIPhysRead,
     3662    pdmR3DevHlp_PCIPhysWrite,
    36353663    pdmR3DevHlp_PCISetIrq,
    36363664    pdmR3DevHlp_PCISetIrqNoWait,

  • trunk/src/VBox/VMM/VMMRC/PDMRCDevice.cpp

    r44362 r44897  
    7575{
    7676    PDMDEV_ASSERT_DEVINS(pDevIns);
    77     LogFlow(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
    78              pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
    79 
    80     PCIDevice *pPciDev = pDevIns->Internal.s.pPciDeviceRC;
    81     AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
     77
     78    /*
     79     * Just check the busmaster setting here and forward the request to the generic read helper.
     80     */
     81    PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceRC;
     82    AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
    8283
    8384    if (!PCIDevIsBusmaster(pPciDev))
    8485    {
    85 #ifdef DEBUG
    86         LogFlow(("%s: %RU16:%RU16: No bus master (anymore), skipping read %p (%z)\n", __FUNCTION__,
    87                  PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbRead));
    88 #endif
    89         return VINF_PDM_PCI_PHYS_READ_BM_DISABLED;
    90     }
    91 
    92     return pdmRCDevHlp_PhysRead(pDevIns, GCPhys, pvBuf, cbRead);
     86        Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#z\n",
     87             pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
     88        return VERR_PDM_NOT_PCI_BUS_MASTER;
     89    }
     90
     91    return pDevIns->pHlpRC->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
    9392}
    9493
    … …  
    9897{
    9998    PDMDEV_ASSERT_DEVINS(pDevIns);
    100     LogFlow(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
    101              pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
    102 
    103     PCIDevice *pPciDev = pDevIns->Internal.s.pPciDeviceRC;
    104     AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
     99
     100    /*
     101     * Just check the busmaster setting here and forward the request to the generic read helper.
     102     */
     103    PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceRC;
     104    AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
    105105
    106106    if (!PCIDevIsBusmaster(pPciDev))
    107107    {
    108 #ifdef DEBUG
    109         LogFlow(("%s: %RU16:%RU16: No bus master (anymore), skipping write %p (%z)\n", __FUNCTION__,
    110                  PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbWrite));
    111 #endif
    112         return VINF_PDM_PCI_PHYS_WRITE_BM_DISABLED;
    113     }
    114 
    115     return pdmRCDevHlp_PhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
     108        Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#z\n",
     109             pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
     110        return VERR_PDM_NOT_PCI_BUS_MASTER;
     111    }
     112
     113    return pDevIns->pHlpRC->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
    116114}
    117115
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette