Changeset 45103 in vbox for trunk/src/VBox/VMM/VMMR3
- Timestamp:
- Mar 20, 2013 11:13:27 AM (12 years ago)
- Location:
- trunk/src/VBox/VMM/VMMR3
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/PGMBth.h
r44528 r45103 153 153 # endif 154 154 155 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);155 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.pShwPageCR3R3, NIL_PGMPOOL_IDX, UINT32_MAX); 156 156 pVCpu->pgm.s.pShwPageCR3R3 = 0; 157 157 pVCpu->pgm.s.pShwPageCR3RC = 0; 158 158 pVCpu->pgm.s.pShwPageCR3R0 = 0; 159 pVCpu->pgm.s.iShwUser = 0;160 pVCpu->pgm.s.iShwUserTable = 0;161 159 } 162 160 163 161 /* construct a fake address. */ 164 162 GCPhysCR3 = RT_BIT_64(63); 165 pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;166 pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;167 163 int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu), 168 pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable, false /*fLockPage*/,164 NIL_PGMPOOL_IDX, UINT32_MAX, false /*fLockPage*/, 169 165 &pVCpu->pgm.s.pShwPageCR3R3); 170 166 if (rc == VERR_PGM_POOL_FLUSHED) -
trunk/src/VBox/VMM/VMMR3/PGMPool.cpp
r44399 r45103 284 284 pPool->HCPhysTree = 0; 285 285 286 /* The NIL entry. */ 286 /* 287 * The NIL entry. 288 */ 287 289 Assert(NIL_PGMPOOL_IDX == 0); 288 290 pPool->aPages[NIL_PGMPOOL_IDX].enmKind = PGMPOOLKIND_INVALID; 289 291 pPool->aPages[NIL_PGMPOOL_IDX].idx = NIL_PGMPOOL_IDX; 290 291 /* The Shadow 32-bit PD. (32 bits guest paging) */ 292 pPool->aPages[PGMPOOL_IDX_PD].enmKind = PGMPOOLKIND_32BIT_PD; 293 pPool->aPages[PGMPOOL_IDX_PD].idx = PGMPOOL_IDX_PD; 294 295 /* The Shadow PDPT. */ 296 pPool->aPages[PGMPOOL_IDX_PDPT].enmKind = PGMPOOLKIND_PAE_PDPT; 297 pPool->aPages[PGMPOOL_IDX_PDPT].idx = PGMPOOL_IDX_PDPT; 298 299 /* The Shadow AMD64 CR3. */ 300 pPool->aPages[PGMPOOL_IDX_AMD64_CR3].enmKind = PGMPOOLKIND_64BIT_PML4; 301 pPool->aPages[PGMPOOL_IDX_AMD64_CR3].idx = PGMPOOL_IDX_AMD64_CR3; 302 303 /* The Nested Paging CR3. */ 304 pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].enmKind = PGMPOOLKIND_ROOT_NESTED; 305 pPool->aPages[PGMPOOL_IDX_NESTED_ROOT].idx = PGMPOOL_IDX_NESTED_ROOT; 306 307 /* 308 * Set common stuff. 309 */ 310 for (unsigned iPage = 0; iPage < PGMPOOL_IDX_FIRST; iPage++) 311 { 312 pPool->aPages[iPage].Core.Key = NIL_RTHCPHYS; 313 pPool->aPages[iPage].GCPhys = NIL_RTGCPHYS; 314 pPool->aPages[iPage].iNext = NIL_PGMPOOL_IDX; 315 /* pPool->aPages[iPage].cLocked = INT32_MAX; - test this out... */ 316 pPool->aPages[iPage].pvPageR3 = 0; 317 pPool->aPages[iPage].iUserHead = NIL_PGMPOOL_USER_INDEX; 318 pPool->aPages[iPage].iModifiedNext = NIL_PGMPOOL_IDX; 319 pPool->aPages[iPage].iModifiedPrev = NIL_PGMPOOL_IDX; 320 pPool->aPages[iPage].iMonitoredNext = NIL_PGMPOOL_IDX; 321 pPool->aPages[iPage].iMonitoredNext = NIL_PGMPOOL_IDX; 322 pPool->aPages[iPage].iAgeNext = NIL_PGMPOOL_IDX; 323 pPool->aPages[iPage].iAgePrev = NIL_PGMPOOL_IDX; 324 325 Assert(pPool->aPages[iPage].idx == iPage); 326 Assert(pPool->aPages[iPage].GCPhys == NIL_RTGCPHYS); 327 Assert(!pPool->aPages[iPage].fSeenNonGlobal); 328 Assert(!pPool->aPages[iPage].fMonitored); 329 Assert(!pPool->aPages[iPage].fCached); 330 Assert(!pPool->aPages[iPage].fZeroed); 331 Assert(!pPool->aPages[iPage].fReusedFlushPending); 332 } 292 pPool->aPages[NIL_PGMPOOL_IDX].Core.Key = NIL_RTHCPHYS; 293 pPool->aPages[NIL_PGMPOOL_IDX].GCPhys = NIL_RTGCPHYS; 294 pPool->aPages[NIL_PGMPOOL_IDX].iNext = NIL_PGMPOOL_IDX; 295 /* pPool->aPages[NIL_PGMPOOL_IDX].cLocked = INT32_MAX; - test this out... */ 296 pPool->aPages[NIL_PGMPOOL_IDX].pvPageR3 = 0; 297 pPool->aPages[NIL_PGMPOOL_IDX].iUserHead = NIL_PGMPOOL_USER_INDEX; 298 pPool->aPages[NIL_PGMPOOL_IDX].iModifiedNext = NIL_PGMPOOL_IDX; 299 pPool->aPages[NIL_PGMPOOL_IDX].iModifiedPrev = NIL_PGMPOOL_IDX; 300 pPool->aPages[NIL_PGMPOOL_IDX].iMonitoredNext = NIL_PGMPOOL_IDX; 301 pPool->aPages[NIL_PGMPOOL_IDX].iMonitoredNext = NIL_PGMPOOL_IDX; 302 pPool->aPages[NIL_PGMPOOL_IDX].iAgeNext = NIL_PGMPOOL_IDX; 303 pPool->aPages[NIL_PGMPOOL_IDX].iAgePrev = NIL_PGMPOOL_IDX; 304 305 Assert(pPool->aPages[NIL_PGMPOOL_IDX].idx == NIL_PGMPOOL_IDX); 306 Assert(pPool->aPages[NIL_PGMPOOL_IDX].GCPhys == NIL_RTGCPHYS); 307 Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fSeenNonGlobal); 308 Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fMonitored); 309 Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fCached); 310 Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fZeroed); 311 Assert(!pPool->aPages[NIL_PGMPOOL_IDX].fReusedFlushPending); 333 312 334 313 #ifdef VBOX_WITH_STATISTICS … … 786 765 } 787 766 788 /* swipe the special pages too. */789 for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)790 {791 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];792 if (pPage->GCPhys != NIL_RTGCPHYS)793 {794 Assert(!pPage->cModifications || ++cModifiedPages);795 Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX || pPage->cModifications);796 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX || pPage->cModifications);797 pPage->iModifiedNext = NIL_PGMPOOL_IDX;798 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;799 pPage->cModifications = 0;800 }801 }802 803 767 #ifndef DEBUG_michael 804 768 AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages)); -
trunk/src/VBox/VMM/VMMR3/PGMShw.h
r44528 r45103 37 37 #undef SHW_PDPT_MASK 38 38 #undef SHW_PDPE_PG_MASK 39 #undef SHW_POOL_ROOT_IDX40 39 41 40 #if PGM_SHW_TYPE == PGM_TYPE_32BIT … … 55 54 # define SHW_PT_SHIFT X86_PT_SHIFT 56 55 # define SHW_PT_MASK X86_PT_MASK 57 # define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD58 56 59 57 #elif PGM_SHW_TYPE == PGM_TYPE_EPT … … 76 74 # define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK 77 75 # define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES) 78 # define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */79 76 80 77 #else … … 99 96 # define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK 100 97 # define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES) 101 # define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3102 98 103 99 # else /* 32 bits PAE mode */ … … 106 102 # define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK 107 103 # define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES) 108 # define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT109 104 # endif 110 105 #endif … … 195 190 196 191 int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu), 197 PGMPOOL_IDX_NESTED_ROOT, GCPhysCR3 >> PAGE_SHIFT, true /*fLockPage*/,192 NIL_PGMPOOL_IDX, UINT32_MAX, true /*fLockPage*/, 198 193 &pNewShwPageCR3); 199 194 AssertFatalRC(rc); 200 195 201 pVCpu->pgm.s.iShwUser = PGMPOOL_IDX_NESTED_ROOT;202 pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;203 196 pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3; 204 197 … … 245 238 { 246 239 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); 247 248 Assert(pVCpu->pgm.s.iShwUser == PGMPOOL_IDX_NESTED_ROOT);249 240 250 241 pgmLock(pVM); … … 257 248 /* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */ 258 249 259 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);250 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX); 260 251 pVCpu->pgm.s.pShwPageCR3R3 = 0; 261 252 pVCpu->pgm.s.pShwPageCR3R0 = 0; 262 253 pVCpu->pgm.s.pShwPageCR3RC = 0; 263 pVCpu->pgm.s.iShwUser = 0;264 pVCpu->pgm.s.iShwUserTable = 0;265 254 266 255 pgmUnlock(pVM);
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