VirtualBox

Changeset 45485 in vbox for trunk/src/recompiler


Ignore:
Timestamp:
Apr 11, 2013 2:46:04 PM (12 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
84947
Message:
  • *: Where possible, drop the #ifdef VBOX_WITH_RAW_RING1 when EMIsRawRing1Enabled is used.
  • SELM: Don't shadow TSS.esp1/ss1 unless ring-1 compression is enabled (also fixed a log statement there).
  • SELM: selmGuestToShadowDesc should not push ring-1 selectors into ring-2 unless EMIsRawRing1Enabled() holds true.
  • REM: Don't set CPU_INTERRUPT_EXTERNAL_EXIT in helper_ltr() for now.
Location:
trunk/src/recompiler
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/recompiler/VBoxRecompiler.c

    r45305 r45485  
    16331633        }
    16341634
    1635 # ifdef VBOX_WITH_RAW_RING1
    1636         /* Only ring 0 and 1 supervisor code. */
    16371635        if (EMIsRawRing1Enabled(env->pVM))
    16381636        {
    1639             if (((fFlags >> HF_CPL_SHIFT) & 3) == 2)   /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
     1637            /* Only ring 0 and 1 supervisor code. */
     1638            if (((fFlags >> HF_CPL_SHIFT) & 3) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
    16401639            {
    16411640                Log2(("raw r0 mode refused: CPL %d\n", (fFlags >> HF_CPL_SHIFT) & 3));
     
    16431642            }
    16441643        }
    1645         else
    1646 # endif
    1647         // Only R0
    1648         if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
     1644        /* Only R0. */
     1645        else if (((fFlags >> HF_CPL_SHIFT) & 3) != 0)
    16491646        {
    16501647            STAM_COUNTER_INC(&gStatRefuseRing1or2);
  • trunk/src/recompiler/target-i386/op_helper.c

    r45276 r45485  
    232232#ifdef VBOX
    233233    /* Trying to load a selector with CPL=1? */
    234     /* @todo this is a hack to correct the incorrect checking order for pending interrupts in the patm iret replacement code (corrected in the ring-1 version) */
    235     /* @todo in theory the iret could fault and we'd still need this. */
     234    /** @todo this is a hack to correct the incorrect checking order for pending interrupts in the patm iret replacement code (corrected in the ring-1 version) */
     235    /** @todo in theory the iret could fault and we'd still need this. */
    236236    if ((env->hflags & HF_CPL_MASK) == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0) && !EMIsRawRing1Enabled(env->pVM))
    237237    {
     
    25612561         (RTGCPTR)env->eip, (RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
    25622562         env->tr.flags, (RTSEL)(selector & 0xffff)));
     2563# if 0 /** @todo r=bird: This looks very fishy, need good reason to re-enable it. */
    25632564    ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request,
    25642565                    CPU_INTERRUPT_EXTERNAL_EXIT);
     2566# endif
    25652567#endif
    25662568    selector &= 0xffff;
     
    31863188        if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
    31873189        {
    3188 # ifdef VBOX_WITH_RAW_RING1
    31893190            if (   !EMIsRawRing1Enabled(env->pVM)
    31903191                ||  env->segs[R_CS].selector == (new_cs & 0xfffc))
     
    31983199                Log(("Genuine switch to ring-1 (iret)\n"));
    31993200            }
    3200 # else
    3201             Log(("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc));
    3202             new_cs = new_cs & 0xfffc;
    3203 # endif
    3204         }
    3205 # ifdef VBOX_WITH_RAW_RING1
    3206         else
    3207         if ((new_cs & 0x3) == 2 && (env->state & CPU_RAW_RING0) && EMIsRawRing1Enabled(env->pVM))
     3201        }
     3202        else if ((new_cs & 0x3) == 2 && (env->state & CPU_RAW_RING0) && EMIsRawRing1Enabled(env->pVM))
    32083203        {
    32093204            Log(("RPL 2 -> new_cs %04X -> %04X\n", new_cs, (new_cs & 0xfffc) | 1));
    32103205            new_cs = (new_cs & 0xfffc) | 1;
    32113206        }
    3212 # endif
    32133207#endif
    32143208    } else {
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