Changeset 45585 in vbox for trunk/src/VBox

Timestamp:

Apr 17, 2013 11:31:45 AM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

85079

Message:

VMMR0/HMVMXR0: Fix regression with EFER MSR write exits. Fixes NetBSD again.

Location:

trunk/src/VBox/VMM

Files:

• VMMR0/HMVMXR0.cpp (modified) (17 diffs)
• include/HMInternal.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -36 +36 @@
 #endif
 #ifdef DEBUG_ramshankar
+#define VBOX_ALWAYS_SAVE_FULL_VTX_STATE
+#define VBOX_ALWAYS_SYNC_FULL_VTX_STATE
 #define VBOX_ALWAYS_TRAP_ALL_EXCEPTIONS
 #endif
@@ -3530 +3532 @@
     }
 
-    /*
-     * Guest FS & GS base MSRs.
-     * We already initialized the FS & GS base as part of the guest segment registers, but the guest's FS/GS base
-     * MSRs might have changed (e.g. due to WRMSR) and we need to update the bases if that happened. These MSRs
-     * are only available in 64-bit mode.
-     */
-    /** @todo Avoid duplication of this code in assembly (see MYPUSHSEGS) - it
-     *        should not be necessary to do it in assembly again. */
-    if (CPUMIsGuestInLongModeEx(pCtx))
-    {
-        if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_FS_BASE_MSR)
-        {
-            rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_FS_BASE, pCtx->fs.u64Base);
-            AssertRCReturn(rc, rc);
-            pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_FS_BASE_MSR;
-        }
-
-        if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GS_BASE_MSR)
-        {
-            rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_GS_BASE, pCtx->gs.u64Base);
-            AssertRCReturn(rc, rc);
-            pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GS_BASE_MSR;
-        }
-    }
-    else
-        pVCpu->hm.s.fContextUseFlags &= ~(HM_CHANGED_GUEST_FS_BASE_MSR | HM_CHANGED_GUEST_GS_BASE_MSR);
-
     return VINF_SUCCESS;
 }
@@ -5147 +5122 @@
         switch (pMsr->u32IndexMSR)
         {
-            case MSR_K8_LSTAR:          pMixedCtx->msrLSTAR = pMsr->u64Value;                    break;
-            case MSR_K6_STAR:           pMixedCtx->msrSTAR = pMsr->u64Value;                     break;
+            case MSR_K8_LSTAR:          pMixedCtx->msrLSTAR  = pMsr->u64Value;                   break;
+            case MSR_K6_STAR:           pMixedCtx->msrSTAR   = pMsr->u64Value;                    break;
             case MSR_K8_SF_MASK:        pMixedCtx->msrSFMASK = pMsr->u64Value;                   break;
             case MSR_K8_TSC_AUX:        CPUMSetGuestMsr(pVCpu, MSR_K8_TSC_AUX, pMsr->u64Value);  break;
@@ -5440 +5415 @@
 
     VMMRZCallRing3Disable(pVCpu);
+    Assert(VMMR0IsLogFlushDisabled(pVCpu));
+    LogFunc(("\n"));
 
     int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
@@ -5738 +5715 @@
 {
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
+    Assert(VMMR0IsLogFlushDisabled(pVCpu));
 
     int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
@@ -5854 +5832 @@
 
     VMMRZCallRing3Disable(pVCpu);
-    Log(("hmR0VmxLongJmpToRing3\n"));
+    Assert(VMMR0IsLogFlushDisabled(pVCpu));
+    Log(("hmR0VmxCallRing3Callback->hmR0VmxLongJmpToRing3\n"));
     hmR0VmxLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser, VINF_VMM_UNKNOWN_RING3_CALL);
     VMMRZCallRing3Enable(pVCpu);
@@ -6593 +6572 @@
     Assert(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT));
     Log4(("LoadFlags=%#RX32\n", pVCpu->hm.s.fContextUseFlags));
+#ifdef VBOX_ALWAYS_SYNC_FULL_VTX_STATE
+    pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
+#endif
     int rc = VINF_SUCCESS;
     if (pVCpu->hm.s.fContextUseFlags == HM_CHANGED_GUEST_RIP)
@@ -6717 +6699 @@
         /* Update the guest interruptibility-state from the VMCS. */
         hmR0VmxSaveGuestIntrState(pVCpu, pMixedCtx);
-
+#if defined(VBOX_ALWAYS_SYNC_FULL_VTX_STATE) || defined(VBOX_ALWAYS_SAVE_FULL_VTX_STATE)
+        rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
+        AssertRC(rc);
+#endif
         /*
          * If the TPR was raised by the guest, it wouldn't cause a VM-exit immediately. Instead we sync the TPR lazily whenever
@@ -7661 +7646 @@
     rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
     AssertRCReturn(rc, rc);
+    Log(("ecx=%#RX32\n", pMixedCtx->ecx));
 
     rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
@@ -7678 +7664 @@
         }
         else if (pMixedCtx->ecx == MSR_K6_EFER)         /* EFER is the only MSR we auto-load but don't allow write-passthrough. */
+        {
+            rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
+            AssertRCReturn(rc, rc);
             pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_AUTO_MSRS;
+        }
 
         /* Update MSRs that are part of the VMCS when MSR-bitmaps are not supported. */
@@ -7688 +7678 @@
                 case MSR_IA32_SYSENTER_EIP: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_EIP_MSR; break;
                 case MSR_IA32_SYSENTER_ESP: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_ESP_MSR; break;
-                case MSR_K8_FS_BASE:        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_FS_BASE_MSR;      break;
-                case MSR_K8_GS_BASE:        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_GS_BASE_MSR;      break;
+                case MSR_K8_FS_BASE:        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SEGMENT_REGS;     break;
+                case MSR_K8_GS_BASE:        pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SEGMENT_REGS;     break;
                 case MSR_K8_KERNEL_GS_BASE: /* If we auto-load it, update HM_CHANGED_VMX_GUEST_AUTO_MSRS. */   break;
             }
@@ -7921 +7911 @@
     /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
     AssertRCReturn(rc, rc);
+    Log(("CS:RIP=%04x:%#RGv\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
 
     /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
@@ -8141 +8132 @@
 {
     VMX_VALIDATE_EXIT_HANDLER_PARAMS();
-    int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
 
     /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
-    rc = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
+    int rc = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
     if (RT_UNLIKELY(rc == VINF_VMX_DOUBLE_FAULT))
         return VINF_SUCCESS;
@@ -8160 +8150 @@
     rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
 #endif
+    rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
     AssertRCReturn(rc, rc);
 
@@ -8172 +8163 @@
                 && VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) == 0x80)
             {
-                AssertMsgFailed(("hmR0VmxExitApicAccess: can't touch TPR offset while using TPR shadowing.\n"));
+                AssertMsgFailed(("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
             }
 
@@ -8179 +8170 @@
             GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification);
             PVM pVM = pVCpu->CTX_SUFF(pVM);
+            Log(("ApicAccess uAccessType=%#x GCPhys=%RGp Off=%#x\n", uAccessType, GCPhys,
+                 VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification)));
+
             VBOXSTRICTRC rc2 = IOMMMIOPhysHandler(pVM, pVCpu,
                                                   (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW,
                                                   CPUMCTX2CORE(pMixedCtx), GCPhys);
             rc = VBOXSTRICTRC_VAL(rc2);
-            Log(("ApicAccess %RGp %#x rc=%d\n", GCPhys,
-                 VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification), rc));
+            Log(("ApicAccess rc=%d\n", rc));
             if (   rc == VINF_SUCCESS
                 || rc == VERR_PAGE_TABLE_NOT_PRESENT
@@ -8197 +8190 @@
 
         default:
+            Log(("ApicAccess uAccessType=%#x\n", uAccessType));
             rc = VINF_EM_RAW_EMULATE_INSTR;
             break;

trunk/src/VBox/VMM/include/HMInternal.h

@@ -111 +111 @@
 # define HM_CHANGED_GUEST_SEGMENT_REGS           RT_BIT(10)
 # define HM_CHANGED_GUEST_DEBUG                  RT_BIT(11)
-# define HM_CHANGED_GUEST_FS_BASE_MSR            RT_BIT(12)
-# define HM_CHANGED_GUEST_GS_BASE_MSR            RT_BIT(13)
-# define HM_CHANGED_GUEST_SYSENTER_CS_MSR        RT_BIT(14)
-# define HM_CHANGED_GUEST_SYSENTER_EIP_MSR       RT_BIT(15)
-# define HM_CHANGED_GUEST_SYSENTER_ESP_MSR       RT_BIT(16)
-# define HM_CHANGED_VMX_GUEST_AUTO_MSRS          RT_BIT(17)
-# define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE     RT_BIT(18)
-# define HM_CHANGED_VMX_GUEST_APIC_STATE         RT_BIT(19)
-# define HM_CHANGED_VMX_ENTRY_CTLS               RT_BIT(20)
-# define HM_CHANGED_VMX_EXIT_CTLS                RT_BIT(21)
-
-# define HM_CHANGED_HOST_CONTEXT                 RT_BIT(22)
+# define HM_CHANGED_GUEST_SYSENTER_CS_MSR        RT_BIT(12)
+# define HM_CHANGED_GUEST_SYSENTER_EIP_MSR       RT_BIT(13)
+# define HM_CHANGED_GUEST_SYSENTER_ESP_MSR       RT_BIT(14)
+# define HM_CHANGED_VMX_GUEST_AUTO_MSRS          RT_BIT(15)
+# define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE     RT_BIT(16)
+# define HM_CHANGED_VMX_GUEST_APIC_STATE         RT_BIT(17)
+# define HM_CHANGED_VMX_ENTRY_CTLS               RT_BIT(18)
+# define HM_CHANGED_VMX_EXIT_CTLS                RT_BIT(19)
+
+# define HM_CHANGED_HOST_CONTEXT                 RT_BIT(20)
 
 # define HM_CHANGED_ALL_GUEST   (  HM_CHANGED_GUEST_RIP                \
@@ -136 +134 @@
                                  | HM_CHANGED_GUEST_SEGMENT_REGS       \
                                  | HM_CHANGED_GUEST_DEBUG              \
-                                 | HM_CHANGED_GUEST_FS_BASE_MSR        \
-                                 | HM_CHANGED_GUEST_GS_BASE_MSR        \
                                  | HM_CHANGED_GUEST_SYSENTER_CS_MSR    \
                                  | HM_CHANGED_GUEST_SYSENTER_EIP_MSR   \