Index: trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45623)
+++ trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45637)
@@ -36,7 +36,7 @@
 #endif
 #ifdef DEBUG_ramshankar
-#define VBOX_ALWAYS_SAVE_FULL_VTX_STATE
-#define VBOX_ALWAYS_SYNC_FULL_VTX_STATE
-#define VBOX_ALWAYS_TRAP_ALL_EXCEPTIONS
+#define HMVMX_SAVE_FULL_GUEST_STATE
+#define HMVMX_SYNC_FULL_GUEST_STATE
+#define HMVMX_TRAP_ALL_EXCEPTIONS
 #endif
 
@@ -46,9 +46,9 @@
 *******************************************************************************/
 #if defined(RT_ARCH_AMD64)
-# define VMX_IS_64BIT_HOST_MODE()   (true)
+# define HMVMX_IS_64BIT_HOST_MODE()   (true)
 #elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-# define VMX_IS_64BIT_HOST_MODE()   (g_fVMXIs64bitHost != 0)
+# define HMVMX_IS_64BIT_HOST_MODE()   (g_fVMXIs64bitHost != 0)
 #else
-# define VMX_IS_64BIT_HOST_MODE()   (false)
+# define HMVMX_IS_64BIT_HOST_MODE()   (false)
 #endif
 
@@ -56,66 +56,69 @@
 #define HMVMX_USE_FUNCTION_TABLE
 
-
-#define VMX_SEL_UNUSABLE                       RT_BIT(16)
-#define VMX_FLUSH_TAGGED_TLB_EPT_VPID          0
-#define VMX_FLUSH_TAGGED_TLB_EPT               1
-#define VMX_FLUSH_TAGGED_TLB_VPID              2
-#define VMX_FLUSH_TAGGED_TLB_NONE              3
+/** This bit indicates the segment selector is unusable in VT-x. */
+#define HMVMX_SEL_UNUSABLE                       RT_BIT(16)
+
+/** Determine which tagged-TLB flush handler to use. */
+#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID          0
+#define HMVMX_FLUSH_TAGGED_TLB_EPT               1
+#define HMVMX_FLUSH_TAGGED_TLB_VPID              2
+#define HMVMX_FLUSH_TAGGED_TLB_NONE              3
 
 /**
  * Updated-guest-state flags.
  */
-#define VMX_UPDATED_GUEST_FPU                   RT_BIT(0)
-#define VMX_UPDATED_GUEST_RIP                   RT_BIT(1)
-#define VMX_UPDATED_GUEST_RSP                   RT_BIT(2)
-#define VMX_UPDATED_GUEST_RFLAGS                RT_BIT(3)
-#define VMX_UPDATED_GUEST_CR0                   RT_BIT(4)
-#define VMX_UPDATED_GUEST_CR3                   RT_BIT(5)
-#define VMX_UPDATED_GUEST_CR4                   RT_BIT(6)
-#define VMX_UPDATED_GUEST_GDTR                  RT_BIT(7)
-#define VMX_UPDATED_GUEST_IDTR                  RT_BIT(8)
-#define VMX_UPDATED_GUEST_LDTR                  RT_BIT(9)
-#define VMX_UPDATED_GUEST_TR                    RT_BIT(10)
-#define VMX_UPDATED_GUEST_SEGMENT_REGS          RT_BIT(11)
-#define VMX_UPDATED_GUEST_DEBUG                 RT_BIT(12)
-#define VMX_UPDATED_GUEST_FS_BASE_MSR           RT_BIT(13)
-#define VMX_UPDATED_GUEST_GS_BASE_MSR           RT_BIT(14)
-#define VMX_UPDATED_GUEST_SYSENTER_CS_MSR       RT_BIT(15)
-#define VMX_UPDATED_GUEST_SYSENTER_EIP_MSR      RT_BIT(16)
-#define VMX_UPDATED_GUEST_SYSENTER_ESP_MSR      RT_BIT(17)
-#define VMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS  RT_BIT(18)
-#define VMX_UPDATED_GUEST_ACTIVITY_STATE        RT_BIT(19)
-#define VMX_UPDATED_GUEST_APIC_STATE            RT_BIT(20)
-#define VMX_UPDATED_GUEST_ALL                   (  VMX_UPDATED_GUEST_FPU                   \
-                                                 | VMX_UPDATED_GUEST_RIP                   \
-                                                 | VMX_UPDATED_GUEST_RSP                   \
-                                                 | VMX_UPDATED_GUEST_RFLAGS                \
-                                                 | VMX_UPDATED_GUEST_CR0                   \
-                                                 | VMX_UPDATED_GUEST_CR3                   \
-                                                 | VMX_UPDATED_GUEST_CR4                   \
-                                                 | VMX_UPDATED_GUEST_GDTR                  \
-                                                 | VMX_UPDATED_GUEST_IDTR                  \
-                                                 | VMX_UPDATED_GUEST_LDTR                  \
-                                                 | VMX_UPDATED_GUEST_TR                    \
-                                                 | VMX_UPDATED_GUEST_SEGMENT_REGS          \
-                                                 | VMX_UPDATED_GUEST_DEBUG                 \
-                                                 | VMX_UPDATED_GUEST_FS_BASE_MSR           \
-                                                 | VMX_UPDATED_GUEST_GS_BASE_MSR           \
-                                                 | VMX_UPDATED_GUEST_SYSENTER_CS_MSR       \
-                                                 | VMX_UPDATED_GUEST_SYSENTER_EIP_MSR      \
-                                                 | VMX_UPDATED_GUEST_SYSENTER_ESP_MSR      \
-                                                 | VMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS  \
-                                                 | VMX_UPDATED_GUEST_ACTIVITY_STATE        \
-                                                 | VMX_UPDATED_GUEST_APIC_STATE)
-
-/**
- * Flags to skip redundant reads of some common VMCS fields.
- */
-#define VMX_TRANSIENT_IDT_VECTORING_INFO            RT_BIT(0)
-#define VMX_TRANSIENT_IDT_VECTORING_ERROR_CODE      RT_BIT(1)
-#define VMX_TRANSIENT_EXIT_QUALIFICATION            RT_BIT(2)
-#define VMX_TRANSIENT_EXIT_INSTR_LEN                RT_BIT(3)
-#define VMX_TRANSIENT_EXIT_INTERRUPTION_INFO        RT_BIT(4)
-#define VMX_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE  RT_BIT(5)
+#define HMVMX_UPDATED_GUEST_FPU                   RT_BIT(0)
+#define HMVMX_UPDATED_GUEST_RIP                   RT_BIT(1)
+#define HMVMX_UPDATED_GUEST_RSP                   RT_BIT(2)
+#define HMVMX_UPDATED_GUEST_RFLAGS                RT_BIT(3)
+#define HMVMX_UPDATED_GUEST_CR0                   RT_BIT(4)
+#define HMVMX_UPDATED_GUEST_CR3                   RT_BIT(5)
+#define HMVMX_UPDATED_GUEST_CR4                   RT_BIT(6)
+#define HMVMX_UPDATED_GUEST_GDTR                  RT_BIT(7)
+#define HMVMX_UPDATED_GUEST_IDTR                  RT_BIT(8)
+#define HMVMX_UPDATED_GUEST_LDTR                  RT_BIT(9)
+#define HMVMX_UPDATED_GUEST_TR                    RT_BIT(10)
+#define HMVMX_UPDATED_GUEST_SEGMENT_REGS          RT_BIT(11)
+#define HMVMX_UPDATED_GUEST_DEBUG                 RT_BIT(12)
+#define HMVMX_UPDATED_GUEST_FS_BASE_MSR           RT_BIT(13)
+#define HMVMX_UPDATED_GUEST_GS_BASE_MSR           RT_BIT(14)
+#define HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR       RT_BIT(15)
+#define HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR      RT_BIT(16)
+#define HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR      RT_BIT(17)
+#define HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS  RT_BIT(18)
+#define HMVMX_UPDATED_GUEST_ACTIVITY_STATE        RT_BIT(19)
+#define HMVMX_UPDATED_GUEST_APIC_STATE            RT_BIT(20)
+#define HMVMX_UPDATED_GUEST_ALL                   (  HMVMX_UPDATED_GUEST_FPU                   \
+                                                   | HMVMX_UPDATED_GUEST_RIP                   \
+                                                   | HMVMX_UPDATED_GUEST_RSP                   \
+                                                   | HMVMX_UPDATED_GUEST_RFLAGS                \
+                                                   | HMVMX_UPDATED_GUEST_CR0                   \
+                                                   | HMVMX_UPDATED_GUEST_CR3                   \
+                                                   | HMVMX_UPDATED_GUEST_CR4                   \
+                                                   | HMVMX_UPDATED_GUEST_GDTR                  \
+                                                   | HMVMX_UPDATED_GUEST_IDTR                  \
+                                                   | HMVMX_UPDATED_GUEST_LDTR                  \
+                                                   | HMVMX_UPDATED_GUEST_TR                    \
+                                                   | HMVMX_UPDATED_GUEST_SEGMENT_REGS          \
+                                                   | HMVMX_UPDATED_GUEST_DEBUG                 \
+                                                   | HMVMX_UPDATED_GUEST_FS_BASE_MSR           \
+                                                   | HMVMX_UPDATED_GUEST_GS_BASE_MSR           \
+                                                   | HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR       \
+                                                   | HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR      \
+                                                   | HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR      \
+                                                   | HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS  \
+                                                   | HMVMX_UPDATED_GUEST_ACTIVITY_STATE        \
+                                                   | HMVMX_UPDATED_GUEST_APIC_STATE)
+
+/**
+ * Flags to skip redundant reads of some common VMCS fields that are not part of
+ * the guest-CPU state but are in the transient structure.
+ */
+#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO            RT_BIT(0)
+#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE      RT_BIT(1)
+#define HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION            RT_BIT(2)
+#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN                RT_BIT(3)
+#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO        RT_BIT(4)
+#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE  RT_BIT(5)
 
 /**
@@ -124,20 +127,20 @@
  * we have Nested Paging support.
  */
-#define VMX_REAL_MODE_XCPT_BITMAP  ( RT_BIT(X86_XCPT_DE)             | RT_BIT(X86_XCPT_DB)    | RT_BIT(X86_XCPT_NMI)   \
-                                   | RT_BIT(X86_XCPT_BP)             | RT_BIT(X86_XCPT_OF)    | RT_BIT(X86_XCPT_BR)    \
-                                   | RT_BIT(X86_XCPT_UD)            /* RT_BIT(X86_XCPT_NM) */ | RT_BIT(X86_XCPT_DF)    \
-                                   | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS)    | RT_BIT(X86_XCPT_NP)    \
-                                   | RT_BIT(X86_XCPT_SS)             | RT_BIT(X86_XCPT_GP)   /* RT_BIT(X86_XCPT_PF) */ \
-                                   | RT_BIT(X86_XCPT_MF)             | RT_BIT(X86_XCPT_AC)    | RT_BIT(X86_XCPT_MC)    \
-                                   | RT_BIT(X86_XCPT_XF))
+#define HMVMX_REAL_MODE_XCPT_MASK    (  RT_BIT(X86_XCPT_DE)             | RT_BIT(X86_XCPT_DB)    | RT_BIT(X86_XCPT_NMI)   \
+                                      | RT_BIT(X86_XCPT_BP)             | RT_BIT(X86_XCPT_OF)    | RT_BIT(X86_XCPT_BR)    \
+                                      | RT_BIT(X86_XCPT_UD)            /* RT_BIT(X86_XCPT_NM) */ | RT_BIT(X86_XCPT_DF)    \
+                                      | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS)    | RT_BIT(X86_XCPT_NP)    \
+                                      | RT_BIT(X86_XCPT_SS)             | RT_BIT(X86_XCPT_GP)   /* RT_BIT(X86_XCPT_PF) */ \
+                                      | RT_BIT(X86_XCPT_MF)             | RT_BIT(X86_XCPT_AC)    | RT_BIT(X86_XCPT_MC)    \
+                                      | RT_BIT(X86_XCPT_XF))
 
 /**
  * Exception bitmap mask for all contributory exceptions.
  */
-#define VMX_CONTRIBUTORY_XCPT_BITMAP  ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
-                                      | RT_BIT(X86_XCPT_DE))
+#define HMVMX_CONTRIBUTORY_XCPT_MASK  ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
+                                       | RT_BIT(X86_XCPT_DE))
 
 /** Maximum VM-instruction error number. */
-#define VMX_INSTR_ERROR_MAX     28
+#define HMVMX_INSTR_ERROR_MAX     28
 
 
@@ -184,5 +187,5 @@
     uint32_t        uIdtVectoringErrorCode;
 
-    /** Mask of currently read VMCS fields; VMX_TRANSIENT_*. */
+    /** Mask of currently read VMCS fields; HMVMX_UPDATED_TRANSIENT_*. */
     uint32_t        fVmcsFieldsRead;
     /** Whether TSC-offsetting should be setup before VM-entry. */
@@ -371,5 +374,5 @@
 
 #ifdef VBOX_STRICT
-static const char * const g_apszVmxInstrErrors[VMX_INSTR_ERROR_MAX + 1] =
+static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
 {
     /*  0 */ "(Not Used)",
@@ -493,9 +496,9 @@
 DECLINLINE(int) hmR0VmxReadExitIntrInfoVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    if (!(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_EXIT_INTERRUPTION_INFO))
+    if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO))
     {
         int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntrInfo);
         AssertRCReturn(rc, rc);
-        pVmxTransient->fVmcsFieldsRead |= VMX_TRANSIENT_EXIT_INTERRUPTION_INFO;
+        pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO;
     }
     return VINF_SUCCESS;
@@ -513,9 +516,9 @@
 DECLINLINE(int) hmR0VmxReadExitIntrErrorCodeVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    if (!(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE))
+    if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE))
     {
         int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntrErrorCode);
         AssertRCReturn(rc, rc);
-        pVmxTransient->fVmcsFieldsRead |= VMX_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE;
+        pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE;
     }
     return VINF_SUCCESS;
@@ -533,9 +536,9 @@
 DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    if (!(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_EXIT_INSTR_LEN))
+    if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN))
     {
         int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
         AssertRCReturn(rc, rc);
-        pVmxTransient->fVmcsFieldsRead |= VMX_TRANSIENT_EXIT_INSTR_LEN;
+        pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN;
     }
     return VINF_SUCCESS;
@@ -552,9 +555,9 @@
 DECLINLINE(int) hmR0VmxReadExitQualificationVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    if (!(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_EXIT_QUALIFICATION))
+    if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION))
     {
         int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQualification);
         AssertRCReturn(rc, rc);
-        pVmxTransient->fVmcsFieldsRead |= VMX_TRANSIENT_EXIT_QUALIFICATION;
+        pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION;
     }
     return VINF_SUCCESS;
@@ -573,9 +576,9 @@
 DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
 {
-    if (!(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_IDT_VECTORING_INFO))
+    if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO))
     {
         int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_INFO, &pVmxTransient->uIdtVectoringInfo);
         AssertRCReturn(rc, rc);
-        pVmxTransient->fVmcsFieldsRead |= VMX_TRANSIENT_IDT_VECTORING_INFO;
+        pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO;
     }
     return VINF_SUCCESS;
@@ -592,9 +595,9 @@
 DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
 {
-    if (!(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_IDT_VECTORING_ERROR_CODE))
+    if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE))
     {
         int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
         AssertRCReturn(rc, rc);
-        pVmxTransient->fVmcsFieldsRead |= VMX_TRANSIENT_IDT_VECTORING_ERROR_CODE;
+        pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE;
     }
     return VINF_SUCCESS;
@@ -1464,8 +1467,8 @@
     switch (pVM->hm.s.vmx.uFlushTaggedTlb)
     {
-        case VMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu); break;
-        case VMX_FLUSH_TAGGED_TLB_EPT:      hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu);  break;
-        case VMX_FLUSH_TAGGED_TLB_VPID:     hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu); break;
-        case VMX_FLUSH_TAGGED_TLB_NONE:     hmR0VmxFlushTaggedTlbNone(pVM, pVCpu); break;
+        case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu); break;
+        case HMVMX_FLUSH_TAGGED_TLB_EPT:      hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu);  break;
+        case HMVMX_FLUSH_TAGGED_TLB_VPID:     hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu); break;
+        case HMVMX_FLUSH_TAGGED_TLB_NONE:     hmR0VmxFlushTaggedTlbNone(pVM, pVCpu); break;
         default:
             AssertMsgFailed(("Invalid flush-tag function identifier\n"));
@@ -1555,11 +1558,11 @@
      */
     if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
-        pVM->hm.s.vmx.uFlushTaggedTlb = VMX_FLUSH_TAGGED_TLB_EPT_VPID;
+        pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT_VPID;
     else if (pVM->hm.s.fNestedPaging)
-        pVM->hm.s.vmx.uFlushTaggedTlb = VMX_FLUSH_TAGGED_TLB_EPT;
+        pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT;
     else if (pVM->hm.s.vmx.fVpid)
-        pVM->hm.s.vmx.uFlushTaggedTlb = VMX_FLUSH_TAGGED_TLB_VPID;
+        pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_VPID;
     else
-        pVM->hm.s.vmx.uFlushTaggedTlb = VMX_FLUSH_TAGGED_TLB_NONE;
+        pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_NONE;
     return VINF_SUCCESS;
 }
@@ -1873,5 +1876,5 @@
 {
     /* Initially the guest-state is up-to-date as there is nothing in the VMCS. */
-    pVCpu->hm.s.vmx.fUpdatedGuestState = VMX_UPDATED_GUEST_ALL;
+    pVCpu->hm.s.vmx.fUpdatedGuestState = HMVMX_UPDATED_GUEST_ALL;
     return VINF_SUCCESS;
 }
@@ -2044,5 +2047,5 @@
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
     /* For the darwin 32-bit hybrid kernel, we need the 64-bit CR3 as it uses 64-bit paging. */
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         uint64_t uReg = hmR0Get64bitCR3();
@@ -2086,5 +2089,5 @@
      */
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         uSelCS = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
@@ -2150,5 +2153,5 @@
     RT_ZERO(Gdtr);
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         X86XDTR64 Gtr64;
@@ -2183,5 +2186,5 @@
     PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         /* We need the 64-bit TR base for hybrid darwin. */
@@ -2208,5 +2211,5 @@
      */
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
@@ -2256,5 +2259,5 @@
 
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         pHostMsr->u32IndexMSR  = MSR_K6_STAR;
@@ -2294,5 +2297,5 @@
     rc |= VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS,    ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
-    if (VMX_IS_64BIT_HOST_MODE())
+    if (HMVMX_IS_64BIT_HOST_MODE())
     {
         rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP,   ASMRdMsr(MSR_IA32_SYSENTER_ESP));
@@ -2401,5 +2404,5 @@
         /* Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary. */
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-        if (VMX_IS_64BIT_HOST_MODE())
+        if (HMVMX_IS_64BIT_HOST_MODE())
             val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE;
         else
@@ -2523,6 +2526,6 @@
     {
         /* If inhibition is active, RIP & RFLAGS should've been accessed (i.e. read previously from the VMCS or from ring-3). */
-        AssertMsg((pVCpu->hm.s.vmx.fUpdatedGuestState & (VMX_UPDATED_GUEST_RIP | VMX_UPDATED_GUEST_RFLAGS))
-                   == (VMX_UPDATED_GUEST_RIP | VMX_UPDATED_GUEST_RFLAGS), ("%#x\n", pVCpu->hm.s.vmx.fUpdatedGuestState));
+        AssertMsg((pVCpu->hm.s.vmx.fUpdatedGuestState & (HMVMX_UPDATED_GUEST_RIP | HMVMX_UPDATED_GUEST_RFLAGS))
+                   == (HMVMX_UPDATED_GUEST_RIP | HMVMX_UPDATED_GUEST_RFLAGS), ("%#x\n", pVCpu->hm.s.vmx.fUpdatedGuestState));
         if (pMixedCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
         {
@@ -2757,10 +2760,10 @@
             Assert(PDMVmmDevHeapIsEnabled(pVM));
             Assert(pVM->hm.s.vmx.pRealModeTSS);
-            pVCpu->hm.s.vmx.u32XcptBitmap |= VMX_REAL_MODE_XCPT_BITMAP;
+            pVCpu->hm.s.vmx.u32XcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
             fInterceptNM = true;
             fInterceptMF = true;
         }
         else
-            pVCpu->hm.s.vmx.u32XcptBitmap &= ~VMX_REAL_MODE_XCPT_BITMAP;
+            pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
 
         if (fInterceptNM)
@@ -3155,5 +3158,5 @@
         Assert(   !(pCtx->cs.u32Limit & 0xfff00000)
                || (pCtx->cs.Attr.n.u1Granularity));
-        Assert(pCtx->cs.Attr.u && pCtx->cs.Attr.u != VMX_SEL_UNUSABLE);  /* CS cannot be loaded with NULL in protected mode. */
+        Assert(pCtx->cs.Attr.u && pCtx->cs.Attr.u != HMVMX_SEL_UNUSABLE);  /* CS cannot be loaded with NULL in protected mode. */
         if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
             Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
@@ -3163,5 +3166,5 @@
             AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
         /* SS */
-        if (pCtx->ss.Attr.u && pCtx->ss.Attr.u != VMX_SEL_UNUSABLE)
+        if (pCtx->ss.Attr.u && pCtx->ss.Attr.u != HMVMX_SEL_UNUSABLE)
         {
             Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
@@ -3182,5 +3185,5 @@
 #endif
         /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
-        if (pCtx->ds.Attr.u && pCtx->ds.Attr.u != VMX_SEL_UNUSABLE)
+        if (pCtx->ds.Attr.u && pCtx->ds.Attr.u != HMVMX_SEL_UNUSABLE)
         {
             Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
@@ -3196,5 +3199,5 @@
                    || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
         }
-        if (pCtx->es.Attr.u && pCtx->es.Attr.u != VMX_SEL_UNUSABLE)
+        if (pCtx->es.Attr.u && pCtx->es.Attr.u != HMVMX_SEL_UNUSABLE)
         {
             Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
@@ -3210,5 +3213,5 @@
                    || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
         }
-        if (pCtx->fs.Attr.u && pCtx->fs.Attr.u != VMX_SEL_UNUSABLE)
+        if (pCtx->fs.Attr.u && pCtx->fs.Attr.u != HMVMX_SEL_UNUSABLE)
         {
             Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
@@ -3224,5 +3227,5 @@
                    || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
         }
-        if (pCtx->gs.Attr.u && pCtx->gs.Attr.u != VMX_SEL_UNUSABLE)
+        if (pCtx->gs.Attr.u && pCtx->gs.Attr.u != HMVMX_SEL_UNUSABLE)
         {
             Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
@@ -3340,9 +3343,9 @@
          */
         if (!u32Access)
-            u32Access = VMX_SEL_UNUSABLE;
+            u32Access = HMVMX_SEL_UNUSABLE;
     }
 
     /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
-    AssertMsg((u32Access == VMX_SEL_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
+    AssertMsg((u32Access == HMVMX_SEL_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
               ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
 
@@ -3471,5 +3474,5 @@
         AssertMsg(   (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
                   || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
-        AssertMsg(!(u32AccessRights & VMX_SEL_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
+        AssertMsg(!(u32AccessRights & HMVMX_SEL_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
         Assert(!(u32AccessRights & RT_BIT(4)));           /* System MBZ.*/
         Assert(u32AccessRights & RT_BIT(7));              /* Present MB1.*/
@@ -3513,5 +3516,5 @@
         uint32_t u32Access = 0;
         if (!pCtx->ldtr.Attr.u)
-            u32Access = VMX_SEL_UNUSABLE;
+            u32Access = HMVMX_SEL_UNUSABLE;
         else
             u32Access = pCtx->ldtr.Attr.u;
@@ -3524,5 +3527,5 @@
 
         /* Validate. */
-        if (!(u32Access & VMX_SEL_UNUSABLE))
+        if (!(u32Access & HMVMX_SEL_UNUSABLE))
         {
             Assert(!(pCtx->ldtr.Sel & RT_BIT(2)));              /* TI MBZ. */
@@ -3805,8 +3808,8 @@
                 Log(("Exit Qualification %#x\n", pVmxTransient->uExitQualification));
                 Log(("InstrError         %#x\n", pVCpu->hm.s.vmx.lasterror.u32InstrError));
-                if (pVCpu->hm.s.vmx.lasterror.u32InstrError <= VMX_INSTR_ERROR_MAX)
+                if (pVCpu->hm.s.vmx.lasterror.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
                     Log(("InstrError Desc.  \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.lasterror.u32InstrError]));
                 else
-                    Log(("InstrError Desc.    Range exceeded %u\n", VMX_INSTR_ERROR_MAX));
+                    Log(("InstrError Desc.    Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
 
                 /* VMX control bits. */
@@ -3952,5 +3955,5 @@
                 Log(("Host RIP %#RHv\n", uHCReg));
 # if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
-                if (VMX_IS_64BIT_HOST_MODE())
+                if (HMVMX_IS_64BIT_HOST_MODE())
                 {
                     Log(("MSR_K6_EFER            = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
@@ -4749,5 +4752,5 @@
                 Log(("IDT: Vectoring #PF uCR2=%#RGv\n", pMixedCtx->cr2));
             }
-            else if (   (pVCpu->hm.s.vmx.u32XcptBitmap & VMX_CONTRIBUTORY_XCPT_BITMAP)
+            else if (   (pVCpu->hm.s.vmx.u32XcptBitmap & HMVMX_CONTRIBUTORY_XCPT_MASK)
                      && hmR0VmxIsContributoryXcpt(uExitVector)
                      && (   hmR0VmxIsContributoryXcpt(uIdtVector)
@@ -4828,6 +4831,6 @@
 {
     int rc = VINF_SUCCESS;
-    if (   !(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_CR0)
-        || !(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_FPU))
+    if (   !(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0)
+        || !(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_FPU))
     {
         RTGCUINTREG uVal    = 0;
@@ -4838,5 +4841,5 @@
         uVal = (uShadow & pVCpu->hm.s.vmx.cr0_mask) | (uVal & ~pVCpu->hm.s.vmx.cr0_mask);
         CPUMSetGuestCR0(pVCpu, uVal);
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_CR0 | VMX_UPDATED_GUEST_FPU;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR0 | HMVMX_UPDATED_GUEST_FPU;
     }
     return rc;
@@ -4858,5 +4861,5 @@
 {
     int rc = VINF_SUCCESS;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_CR4))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR4))
     {
         RTGCUINTREG uVal    = 0;
@@ -4867,5 +4870,5 @@
         uVal = (uShadow & pVCpu->hm.s.vmx.cr4_mask) | (uVal & ~pVCpu->hm.s.vmx.cr4_mask);
         CPUMSetGuestCR4(pVCpu, uVal);
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_CR4;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR4;
     }
     return rc;
@@ -4886,5 +4889,5 @@
 DECLINLINE(int) hmR0VmxSaveGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
 {
-    if (pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_RIP)
+    if (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RIP)
         return VINF_SUCCESS;
 
@@ -4893,5 +4896,5 @@
     AssertRCReturn(rc, rc);
     pMixedCtx->rip = uVal;
-    pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_RIP;
+    pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RIP;
     return rc;
 }
@@ -4911,5 +4914,5 @@
 DECLINLINE(int) hmR0VmxSaveGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
 {
-    if (pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_RSP)
+    if (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RSP)
         return VINF_SUCCESS;
 
@@ -4918,5 +4921,5 @@
     AssertRCReturn(rc, rc);
     pMixedCtx->rsp = uVal;
-    pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_RSP;
+    pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RSP;
     return rc;
 }
@@ -4936,5 +4939,5 @@
 DECLINLINE(int) hmR0VmxSaveGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
 {
-    if (pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_RFLAGS)
+    if (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS)
         return VINF_SUCCESS;
 
@@ -4954,5 +4957,5 @@
     }
 
-    pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_RFLAGS;
+    pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RFLAGS;
     return rc;
 }
@@ -5018,5 +5021,5 @@
 {
     /* Nothing to do for now until we make use of different guest-CPU activity state. Just update the flag. */
-    pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_ACTIVITY_STATE;
+    pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_ACTIVITY_STATE;
     return VINF_SUCCESS;
 }
@@ -5038,24 +5041,24 @@
 {
     int rc = VINF_SUCCESS;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_SYSENTER_CS_MSR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR))
     {
         uint32_t u32Val = 0;
         rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val);     AssertRCReturn(rc, rc);
         pMixedCtx->SysEnter.cs = u32Val;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_SYSENTER_CS_MSR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR;
     }
 
     RTGCUINTREG uGCVal = 0;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
     {
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &uGCVal);    AssertRCReturn(rc, rc);
         pMixedCtx->SysEnter.eip = uGCVal;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_SYSENTER_EIP_MSR;
-    }
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_SYSENTER_ESP_MSR))
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR;
+    }
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR))
     {
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &uGCVal);    AssertRCReturn(rc, rc);
         pMixedCtx->SysEnter.esp = uGCVal;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_SYSENTER_ESP_MSR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR;
     }
     return rc;
@@ -5079,9 +5082,9 @@
     RTGCUINTREG uVal = 0;
     int rc = VINF_SUCCESS;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_FS_BASE_MSR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_FS_BASE_MSR))
     {
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_FS_BASE, &uVal);   AssertRCReturn(rc, rc);
         pMixedCtx->fs.u64Base = uVal;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_FS_BASE_MSR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_FS_BASE_MSR;
     }
     return rc;
@@ -5105,9 +5108,9 @@
     RTGCUINTREG uVal = 0;
     int rc = VINF_SUCCESS;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_GS_BASE_MSR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GS_BASE_MSR))
     {
         rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GS_BASE, &uVal);   AssertRCReturn(rc, rc);
         pMixedCtx->gs.u64Base = uVal;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_GS_BASE_MSR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_GS_BASE_MSR;
     }
     return rc;
@@ -5129,5 +5132,5 @@
 static int hmR0VmxSaveGuestAutoLoadStoreMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
 {
-    if (pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS)
+    if (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS)
         return VINF_SUCCESS;
 
@@ -5154,5 +5157,5 @@
         }
     }
-    pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS;
+    pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS;
     return VINF_SUCCESS;
 }
@@ -5185,5 +5188,5 @@
 
     /* Guest CR3. Only changes with Nested Paging. This must be done -after- saving CR0 and CR4 from the guest! */
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_CR3))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR3))
     {
         PVM pVM = pVCpu->CTX_SUFF(pVM);
@@ -5215,5 +5218,5 @@
         }
 
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_CR3;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR3;
     }
     return rc;
@@ -5261,8 +5264,8 @@
      * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers.
      */
-    if (pSelReg->Attr.u & VMX_SEL_UNUSABLE)
+    if (pSelReg->Attr.u & HMVMX_SEL_UNUSABLE)
     {
         Assert(idxSel != VMX_VMCS16_GUEST_FIELD_TR);
-        pSelReg->Attr.u = VMX_SEL_UNUSABLE;
+        pSelReg->Attr.u = HMVMX_SEL_UNUSABLE;
     }
     return rc;
@@ -5297,5 +5300,5 @@
 
     /* Guest segment registers. */
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_SEGMENT_REGS))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SEGMENT_REGS))
     {
         rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
@@ -5318,13 +5321,13 @@
             pMixedCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.uAttrGS.u;
         }
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_SEGMENT_REGS;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SEGMENT_REGS;
     }
 
     /* Guest LDTR. */
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_LDTR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_LDTR))
     {
         rc = VMXLOCAL_READ_SEG(LDTR, ldtr);
         AssertRCReturn(rc, rc);
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_LDTR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_LDTR;
     }
 
@@ -5332,5 +5335,5 @@
     RTGCUINTREG uGCVal = 0;
     uint32_t    u32Val = 0;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_GDTR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GDTR))
     {
         rc  = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &uGCVal);
@@ -5338,9 +5341,9 @@
         pMixedCtx->gdtr.pGdt  = uGCVal;
         pMixedCtx->gdtr.cbGdt = u32Val;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_GDTR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_GDTR;
     }
 
     /* Guest IDTR. */
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_IDTR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_IDTR))
     {
         rc  = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &uGCVal);
@@ -5348,9 +5351,9 @@
         pMixedCtx->idtr.pIdt  = uGCVal;
         pMixedCtx->idtr.cbIdt = u32Val;
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_IDTR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_IDTR;
     }
 
     /* Guest TR. */
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_TR))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_TR))
     {
         rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
@@ -5360,5 +5363,5 @@
             rc |= VMXLOCAL_READ_SEG(TR, tr);
         AssertRCReturn(rc, rc);
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_TR;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_TR;
     }
     return rc;
@@ -5381,5 +5384,5 @@
 {
     int rc = VINF_SUCCESS;
-    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_DEBUG))
+    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_DEBUG))
     {
         RTGCUINTREG uVal;
@@ -5387,5 +5390,5 @@
         pMixedCtx->dr[7] = uVal;
 
-        pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_DEBUG;
+        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_DEBUG;
     }
     return rc;
@@ -5407,5 +5410,5 @@
 {
     /* Updating TPR is already done in hmR0VmxPostRunGuest(). Just update the flag. */
-    pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_APIC_STATE;
+    pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_APIC_STATE;
     return VINF_SUCCESS;
 }
@@ -5427,5 +5430,5 @@
     Assert(pMixedCtx);
 
-    if (pVCpu->hm.s.vmx.fUpdatedGuestState == VMX_UPDATED_GUEST_ALL)
+    if (pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL)
         return VINF_SUCCESS;
 
@@ -5464,5 +5467,5 @@
     AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestDebugRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
 
-    AssertMsg(pVCpu->hm.s.vmx.fUpdatedGuestState == VMX_UPDATED_GUEST_ALL,
+    AssertMsg(pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL,
               ("Missed guest state bits while saving state; residue %RX32\n", pVCpu->hm.s.vmx.fUpdatedGuestState));
 
@@ -5733,5 +5736,5 @@
 
     int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
-    Assert(pVCpu->hm.s.vmx.fUpdatedGuestState == VMX_UPDATED_GUEST_ALL);
+    Assert(pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL);
     AssertRC(rc);
 
@@ -5893,5 +5896,5 @@
     const bool fBlockSti   = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
 
-    Assert(!fBlockSti || (pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_RFLAGS));
+    Assert(!fBlockSti || (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS));
     Assert(   !(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI)      /* We don't support block-by-NMI and SMI yet.*/
            && !(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI));
@@ -6587,5 +6590,5 @@
     Assert(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT));
     Log4(("LoadFlags=%#RX32\n", pVCpu->hm.s.fContextUseFlags));
-#ifdef VBOX_ALWAYS_SYNC_FULL_VTX_STATE
+#ifdef HMVMX_SYNC_FULL_GUEST_STATE
     pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
 #endif
@@ -6714,5 +6717,5 @@
         /* Update the guest interruptibility-state from the VMCS. */
         hmR0VmxSaveGuestIntrState(pVCpu, pMixedCtx);
-#if defined(VBOX_ALWAYS_SYNC_FULL_VTX_STATE) || defined(VBOX_ALWAYS_SAVE_FULL_VTX_STATE)
+#if defined(HMVMX_SYNC_FULL_GUEST_STATE) || defined(HMVMX_SAVE_FULL_GUEST_STATE)
         rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
         AssertRC(rc);
@@ -7695,5 +7698,5 @@
             && pMixedCtx->ecx <= MSR_IA32_X2APIC_END)
         {
-            Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & VMX_UPDATED_GUEST_APIC_STATE);
+            Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_APIC_STATE);
             pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
         }
@@ -8839,5 +8842,5 @@
     rc    |= hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
     AssertRCReturn(rc, rc);
-    Assert(pVmxTransient->fVmcsFieldsRead & VMX_TRANSIENT_EXIT_INTERRUPTION_INFO);
+    Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
     hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
                            pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */);
