VirtualBox

Changeset 45907 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
May 6, 2013 12:54:22 PM (12 years ago)
Author:
vboxsync
Message:

VBOX_WITH_IEM bitrot and stuff.

Location:
trunk/src/VBox/VMM/VMMAll
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r45701 r45907  
    16311631
    16321632
     1633#ifdef LOG_ENABLED
     1634static const char *emMSRtoString(uint32_t uMsr)
     1635{
     1636    switch (uMsr)
     1637    {
     1638        case MSR_IA32_APICBASE:             return "MSR_IA32_APICBASE";
     1639        case MSR_IA32_CR_PAT:               return "MSR_IA32_CR_PAT";
     1640        case MSR_IA32_SYSENTER_CS:          return "MSR_IA32_SYSENTER_CS";
     1641        case MSR_IA32_SYSENTER_EIP:         return "MSR_IA32_SYSENTER_EIP";
     1642        case MSR_IA32_SYSENTER_ESP:         return "MSR_IA32_SYSENTER_ESP";
     1643        case MSR_K6_EFER:                   return "MSR_K6_EFER";
     1644        case MSR_K8_SF_MASK:                return "MSR_K8_SF_MASK";
     1645        case MSR_K6_STAR:                   return "MSR_K6_STAR";
     1646        case MSR_K8_LSTAR:                  return "MSR_K8_LSTAR";
     1647        case MSR_K8_CSTAR:                  return "MSR_K8_CSTAR";
     1648        case MSR_K8_FS_BASE:                return "MSR_K8_FS_BASE";
     1649        case MSR_K8_GS_BASE:                return "MSR_K8_GS_BASE";
     1650        case MSR_K8_KERNEL_GS_BASE:         return "MSR_K8_KERNEL_GS_BASE";
     1651        case MSR_K8_TSC_AUX:                return "MSR_K8_TSC_AUX";
     1652        case MSR_IA32_BIOS_SIGN_ID:         return "Unsupported MSR_IA32_BIOS_SIGN_ID";
     1653        case MSR_IA32_PLATFORM_ID:          return "Unsupported MSR_IA32_PLATFORM_ID";
     1654        case MSR_IA32_BIOS_UPDT_TRIG:       return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
     1655        case MSR_IA32_TSC:                  return "MSR_IA32_TSC";
     1656        case MSR_IA32_MISC_ENABLE:          return "MSR_IA32_MISC_ENABLE";
     1657        case MSR_IA32_MTRR_CAP:             return "MSR_IA32_MTRR_CAP";
     1658        case MSR_IA32_MCP_CAP:              return "Unsupported MSR_IA32_MCP_CAP";
     1659        case MSR_IA32_MCP_STATUS:           return "Unsupported MSR_IA32_MCP_STATUS";
     1660        case MSR_IA32_MCP_CTRL:             return "Unsupported MSR_IA32_MCP_CTRL";
     1661        case MSR_IA32_MTRR_DEF_TYPE:        return "MSR_IA32_MTRR_DEF_TYPE";
     1662        case MSR_K7_EVNTSEL0:               return "Unsupported MSR_K7_EVNTSEL0";
     1663        case MSR_K7_EVNTSEL1:               return "Unsupported MSR_K7_EVNTSEL1";
     1664        case MSR_K7_EVNTSEL2:               return "Unsupported MSR_K7_EVNTSEL2";
     1665        case MSR_K7_EVNTSEL3:               return "Unsupported MSR_K7_EVNTSEL3";
     1666        case MSR_IA32_MC0_CTL:              return "Unsupported MSR_IA32_MC0_CTL";
     1667        case MSR_IA32_MC0_STATUS:           return "Unsupported MSR_IA32_MC0_STATUS";
     1668        case MSR_IA32_PERFEVTSEL0:          return "Unsupported MSR_IA32_PERFEVTSEL0";
     1669        case MSR_IA32_PERFEVTSEL1:          return "Unsupported MSR_IA32_PERFEVTSEL1";
     1670        case MSR_IA32_PERF_STATUS:          return "MSR_IA32_PERF_STATUS";
     1671        case MSR_IA32_PLATFORM_INFO:        return "MSR_IA32_PLATFORM_INFO";
     1672        case MSR_IA32_PERF_CTL:             return "Unsupported MSR_IA32_PERF_CTL";
     1673        case MSR_K7_PERFCTR0:               return "Unsupported MSR_K7_PERFCTR0";
     1674        case MSR_K7_PERFCTR1:               return "Unsupported MSR_K7_PERFCTR1";
     1675        case MSR_K7_PERFCTR2:               return "Unsupported MSR_K7_PERFCTR2";
     1676        case MSR_K7_PERFCTR3:               return "Unsupported MSR_K7_PERFCTR3";
     1677        case MSR_IA32_PMC0:                 return "Unsupported MSR_IA32_PMC0";
     1678        case MSR_IA32_PMC1:                 return "Unsupported MSR_IA32_PMC1";
     1679        case MSR_IA32_PMC2:                 return "Unsupported MSR_IA32_PMC2";
     1680        case MSR_IA32_PMC3:                 return "Unsupported MSR_IA32_PMC3";
     1681    }
     1682    return "Unknown MSR";
     1683}
     1684#endif /* LOG_ENABLED */
     1685
     1686
     1687/**
     1688 * Interpret RDMSR
     1689 *
     1690 * @returns VBox status code.
     1691 * @param   pVM         Pointer to the VM.
     1692 * @param   pVCpu       Pointer to the VMCPU.
     1693 * @param   pRegFrame   The register frame.
     1694 */
     1695VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1696{
     1697    NOREF(pVM);
     1698
     1699    /* Get the current privilege level. */
     1700    if (CPUMGetGuestCPL(pVCpu) != 0)
     1701    {
     1702        Log4(("EM: Refuse RDMSR: CPL != 0\n"));
     1703        return VERR_EM_INTERPRETER; /* supervisor only */
     1704    }
     1705
     1706    uint64_t uValue;
     1707    int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
     1708    if (RT_UNLIKELY(rc != VINF_SUCCESS))
     1709    {
     1710        Assert(rc == VERR_CPUM_RAISE_GP_0);
     1711        Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
     1712        return VERR_EM_INTERPRETER;
     1713    }
     1714    pRegFrame->rax = (uint32_t) uValue;
     1715    pRegFrame->rdx = (uint32_t)(uValue >> 32);
     1716    LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
     1717    return rc;
     1718}
     1719
     1720
     1721/**
     1722 * Interpret WRMSR
     1723 *
     1724 * @returns VBox status code.
     1725 * @param   pVM         Pointer to the VM.
     1726 * @param   pVCpu       Pointer to the VMCPU.
     1727 * @param   pRegFrame   The register frame.
     1728 */
     1729VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1730{
     1731    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
     1732
     1733    /* Check the current privilege level, this instruction is supervisor only. */
     1734    if (CPUMGetGuestCPL(pVCpu) != 0)
     1735    {
     1736        Log4(("EM: Refuse WRMSR: CPL != 0\n"));
     1737        return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
     1738    }
     1739
     1740    int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
     1741    if (rc != VINF_SUCCESS)
     1742    {
     1743        Assert(rc == VERR_CPUM_RAISE_GP_0);
     1744        Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
     1745        return VERR_EM_INTERPRETER;
     1746    }
     1747    LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
     1748             RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
     1749    NOREF(pVM);
     1750    return rc;
     1751}
     1752
     1753
    16331754/**
    16341755 * Interpret CRx read.
    … …  
    34653586
    34663587
    3467 #ifdef LOG_ENABLED
    3468 static const char *emMSRtoString(uint32_t uMsr)
    3469 {
    3470     switch (uMsr)
    3471     {
    3472     case MSR_IA32_APICBASE:
    3473         return "MSR_IA32_APICBASE";
    3474     case MSR_IA32_CR_PAT:
    3475         return "MSR_IA32_CR_PAT";
    3476     case MSR_IA32_SYSENTER_CS:
    3477         return "MSR_IA32_SYSENTER_CS";
    3478     case MSR_IA32_SYSENTER_EIP:
    3479         return "MSR_IA32_SYSENTER_EIP";
    3480     case MSR_IA32_SYSENTER_ESP:
    3481         return "MSR_IA32_SYSENTER_ESP";
    3482     case MSR_K6_EFER:
    3483         return "MSR_K6_EFER";
    3484     case MSR_K8_SF_MASK:
    3485         return "MSR_K8_SF_MASK";
    3486     case MSR_K6_STAR:
    3487         return "MSR_K6_STAR";
    3488     case MSR_K8_LSTAR:
    3489         return "MSR_K8_LSTAR";
    3490     case MSR_K8_CSTAR:
    3491         return "MSR_K8_CSTAR";
    3492     case MSR_K8_FS_BASE:
    3493         return "MSR_K8_FS_BASE";
    3494     case MSR_K8_GS_BASE:
    3495         return "MSR_K8_GS_BASE";
    3496     case MSR_K8_KERNEL_GS_BASE:
    3497         return "MSR_K8_KERNEL_GS_BASE";
    3498     case MSR_K8_TSC_AUX:
    3499         return "MSR_K8_TSC_AUX";
    3500     case MSR_IA32_BIOS_SIGN_ID:
    3501         return "Unsupported MSR_IA32_BIOS_SIGN_ID";
    3502     case MSR_IA32_PLATFORM_ID:
    3503         return "Unsupported MSR_IA32_PLATFORM_ID";
    3504     case MSR_IA32_BIOS_UPDT_TRIG:
    3505         return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
    3506     case MSR_IA32_TSC:
    3507         return "MSR_IA32_TSC";
    3508     case MSR_IA32_MISC_ENABLE:
    3509         return "MSR_IA32_MISC_ENABLE";
    3510     case MSR_IA32_MTRR_CAP:
    3511         return "MSR_IA32_MTRR_CAP";
    3512     case MSR_IA32_MCP_CAP:
    3513         return "Unsupported MSR_IA32_MCP_CAP";
    3514     case MSR_IA32_MCP_STATUS:
    3515         return "Unsupported MSR_IA32_MCP_STATUS";
    3516     case MSR_IA32_MCP_CTRL:
    3517         return "Unsupported MSR_IA32_MCP_CTRL";
    3518     case MSR_IA32_MTRR_DEF_TYPE:
    3519         return "MSR_IA32_MTRR_DEF_TYPE";
    3520     case MSR_K7_EVNTSEL0:
    3521         return "Unsupported MSR_K7_EVNTSEL0";
    3522     case MSR_K7_EVNTSEL1:
    3523         return "Unsupported MSR_K7_EVNTSEL1";
    3524     case MSR_K7_EVNTSEL2:
    3525         return "Unsupported MSR_K7_EVNTSEL2";
    3526     case MSR_K7_EVNTSEL3:
    3527         return "Unsupported MSR_K7_EVNTSEL3";
    3528     case MSR_IA32_MC0_CTL:
    3529         return "Unsupported MSR_IA32_MC0_CTL";
    3530     case MSR_IA32_MC0_STATUS:
    3531         return "Unsupported MSR_IA32_MC0_STATUS";
    3532     case MSR_IA32_PERFEVTSEL0:
    3533         return "Unsupported MSR_IA32_PERFEVTSEL0";
    3534     case MSR_IA32_PERFEVTSEL1:
    3535         return "Unsupported MSR_IA32_PERFEVTSEL1";
    3536     case MSR_IA32_PERF_STATUS:
    3537         return "MSR_IA32_PERF_STATUS";
    3538     case MSR_IA32_PLATFORM_INFO:
    3539         return "MSR_IA32_PLATFORM_INFO";
    3540     case MSR_IA32_PERF_CTL:
    3541         return "Unsupported MSR_IA32_PERF_CTL";
    3542     case MSR_K7_PERFCTR0:
    3543         return "Unsupported MSR_K7_PERFCTR0";
    3544     case MSR_K7_PERFCTR1:
    3545         return "Unsupported MSR_K7_PERFCTR1";
    3546     case MSR_K7_PERFCTR2:
    3547         return "Unsupported MSR_K7_PERFCTR2";
    3548     case MSR_K7_PERFCTR3:
    3549         return "Unsupported MSR_K7_PERFCTR3";
    3550     case MSR_IA32_PMC0:
    3551         return "Unsupported MSR_IA32_PMC0";
    3552     case MSR_IA32_PMC1:
    3553         return "Unsupported MSR_IA32_PMC1";
    3554     case MSR_IA32_PMC2:
    3555         return "Unsupported MSR_IA32_PMC2";
    3556     case MSR_IA32_PMC3:
    3557         return "Unsupported MSR_IA32_PMC3";
    3558     }
    3559     return "Unknown MSR";
    3560 }
    3561 #endif /* LOG_ENABLED */
    3562 
    3563 
    3564 /**
    3565  * Interpret RDMSR
    3566  *
    3567  * @returns VBox status code.
    3568  * @param   pVM         Pointer to the VM.
    3569  * @param   pVCpu       Pointer to the VMCPU.
    3570  * @param   pRegFrame   The register frame.
    3571  */
    3572 VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    3573 {
    3574     NOREF(pVM);
    3575 
    3576     /* Get the current privilege level. */
    3577     if (CPUMGetGuestCPL(pVCpu) != 0)
    3578     {
    3579         Log4(("EM: Refuse RDMSR: CPL != 0\n"));
    3580         return VERR_EM_INTERPRETER; /* supervisor only */
    3581     }
    3582 
    3583     uint64_t uValue;
    3584     int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
    3585     if (RT_UNLIKELY(rc != VINF_SUCCESS))
    3586     {
    3587         Assert(rc == VERR_CPUM_RAISE_GP_0);
    3588         Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
    3589         return VERR_EM_INTERPRETER;
    3590     }
    3591     pRegFrame->rax = (uint32_t) uValue;
    3592     pRegFrame->rdx = (uint32_t)(uValue >> 32);
    3593     LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
    3594     return rc;
    3595 }
    3596 
    3597 
    35983588/**
    35993589 * RDMSR Emulation.
    … …  
    36063596    NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
    36073597    return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
    3608 }
    3609 
    3610 
    3611 /**
    3612  * Interpret WRMSR
    3613  *
    3614  * @returns VBox status code.
    3615  * @param   pVM         Pointer to the VM.
    3616  * @param   pVCpu       Pointer to the VMCPU.
    3617  * @param   pRegFrame   The register frame.
    3618  */
    3619 VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    3620 {
    3621     Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    3622 
    3623     /* Check the current privilege level, this instruction is supervisor only. */
    3624     if (CPUMGetGuestCPL(pVCpu) != 0)
    3625     {
    3626         Log4(("EM: Refuse WRMSR: CPL != 0\n"));
    3627         return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
    3628     }
    3629 
    3630     int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
    3631     if (rc != VINF_SUCCESS)
    3632     {
    3633         Assert(rc == VERR_CPUM_RAISE_GP_0);
    3634         Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
    3635         return VERR_EM_INTERPRETER;
    3636     }
    3637     LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
    3638              RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
    3639     NOREF(pVM);
    3640     return rc;
    36413598}
    36423599

  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r45276 r45907  
    843843    {
    844844        if (rc == VINF_SUCCESS)
    845             rc = rc2;
     845            rc = VBOXSTRICTRC_VAL(rc2);
    846846# ifndef IN_RING3
    847847        VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
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