Index: /trunk/include/VBox/vmm/em.h
===================================================================
--- /trunk/include/VBox/vmm/em.h	(revision 45906)
+++ /trunk/include/VBox/vmm/em.h	(revision 45907)
@@ -192,8 +192,6 @@
 VMM_INT_DECL(int)               EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
 VMM_INT_DECL(int)               EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
-#ifndef VBOX_WITH_IEM
 VMM_INT_DECL(int)               EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
 VMM_INT_DECL(int)               EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
-#endif /* !VBOX_WITH_IEM */
 VMM_INT_DECL(bool)              EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
 VMM_INT_DECL(int)               EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx);
Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 45906)
+++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 45907)
@@ -1631,4 +1631,125 @@
 
 
+#ifdef LOG_ENABLED
+static const char *emMSRtoString(uint32_t uMsr)
+{
+    switch (uMsr)
+    {
+        case MSR_IA32_APICBASE:             return "MSR_IA32_APICBASE";
+        case MSR_IA32_CR_PAT:               return "MSR_IA32_CR_PAT";
+        case MSR_IA32_SYSENTER_CS:          return "MSR_IA32_SYSENTER_CS";
+        case MSR_IA32_SYSENTER_EIP:         return "MSR_IA32_SYSENTER_EIP";
+        case MSR_IA32_SYSENTER_ESP:         return "MSR_IA32_SYSENTER_ESP";
+        case MSR_K6_EFER:                   return "MSR_K6_EFER";
+        case MSR_K8_SF_MASK:                return "MSR_K8_SF_MASK";
+        case MSR_K6_STAR:                   return "MSR_K6_STAR";
+        case MSR_K8_LSTAR:                  return "MSR_K8_LSTAR";
+        case MSR_K8_CSTAR:                  return "MSR_K8_CSTAR";
+        case MSR_K8_FS_BASE:                return "MSR_K8_FS_BASE";
+        case MSR_K8_GS_BASE:                return "MSR_K8_GS_BASE";
+        case MSR_K8_KERNEL_GS_BASE:         return "MSR_K8_KERNEL_GS_BASE";
+        case MSR_K8_TSC_AUX:                return "MSR_K8_TSC_AUX";
+        case MSR_IA32_BIOS_SIGN_ID:         return "Unsupported MSR_IA32_BIOS_SIGN_ID";
+        case MSR_IA32_PLATFORM_ID:          return "Unsupported MSR_IA32_PLATFORM_ID";
+        case MSR_IA32_BIOS_UPDT_TRIG:       return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
+        case MSR_IA32_TSC:                  return "MSR_IA32_TSC";
+        case MSR_IA32_MISC_ENABLE:          return "MSR_IA32_MISC_ENABLE";
+        case MSR_IA32_MTRR_CAP:             return "MSR_IA32_MTRR_CAP";
+        case MSR_IA32_MCP_CAP:              return "Unsupported MSR_IA32_MCP_CAP";
+        case MSR_IA32_MCP_STATUS:           return "Unsupported MSR_IA32_MCP_STATUS";
+        case MSR_IA32_MCP_CTRL:             return "Unsupported MSR_IA32_MCP_CTRL";
+        case MSR_IA32_MTRR_DEF_TYPE:        return "MSR_IA32_MTRR_DEF_TYPE";
+        case MSR_K7_EVNTSEL0:               return "Unsupported MSR_K7_EVNTSEL0";
+        case MSR_K7_EVNTSEL1:               return "Unsupported MSR_K7_EVNTSEL1";
+        case MSR_K7_EVNTSEL2:               return "Unsupported MSR_K7_EVNTSEL2";
+        case MSR_K7_EVNTSEL3:               return "Unsupported MSR_K7_EVNTSEL3";
+        case MSR_IA32_MC0_CTL:              return "Unsupported MSR_IA32_MC0_CTL";
+        case MSR_IA32_MC0_STATUS:           return "Unsupported MSR_IA32_MC0_STATUS";
+        case MSR_IA32_PERFEVTSEL0:          return "Unsupported MSR_IA32_PERFEVTSEL0";
+        case MSR_IA32_PERFEVTSEL1:          return "Unsupported MSR_IA32_PERFEVTSEL1";
+        case MSR_IA32_PERF_STATUS:          return "MSR_IA32_PERF_STATUS";
+        case MSR_IA32_PLATFORM_INFO:        return "MSR_IA32_PLATFORM_INFO";
+        case MSR_IA32_PERF_CTL:             return "Unsupported MSR_IA32_PERF_CTL";
+        case MSR_K7_PERFCTR0:               return "Unsupported MSR_K7_PERFCTR0";
+        case MSR_K7_PERFCTR1:               return "Unsupported MSR_K7_PERFCTR1";
+        case MSR_K7_PERFCTR2:               return "Unsupported MSR_K7_PERFCTR2";
+        case MSR_K7_PERFCTR3:               return "Unsupported MSR_K7_PERFCTR3";
+        case MSR_IA32_PMC0:                 return "Unsupported MSR_IA32_PMC0";
+        case MSR_IA32_PMC1:                 return "Unsupported MSR_IA32_PMC1";
+        case MSR_IA32_PMC2:                 return "Unsupported MSR_IA32_PMC2";
+        case MSR_IA32_PMC3:                 return "Unsupported MSR_IA32_PMC3";
+    }
+    return "Unknown MSR";
+}
+#endif /* LOG_ENABLED */
+
+
+/**
+ * Interpret RDMSR
+ *
+ * @returns VBox status code.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pRegFrame   The register frame.
+ */
+VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
+{
+    NOREF(pVM);
+
+    /* Get the current privilege level. */
+    if (CPUMGetGuestCPL(pVCpu) != 0)
+    {
+        Log4(("EM: Refuse RDMSR: CPL != 0\n"));
+        return VERR_EM_INTERPRETER; /* supervisor only */
+    }
+
+    uint64_t uValue;
+    int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
+    if (RT_UNLIKELY(rc != VINF_SUCCESS))
+    {
+        Assert(rc == VERR_CPUM_RAISE_GP_0);
+        Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
+        return VERR_EM_INTERPRETER;
+    }
+    pRegFrame->rax = (uint32_t) uValue;
+    pRegFrame->rdx = (uint32_t)(uValue >> 32);
+    LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
+    return rc;
+}
+
+
+/**
+ * Interpret WRMSR
+ *
+ * @returns VBox status code.
+ * @param   pVM         Pointer to the VM.
+ * @param   pVCpu       Pointer to the VMCPU.
+ * @param   pRegFrame   The register frame.
+ */
+VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
+{
+    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
+
+    /* Check the current privilege level, this instruction is supervisor only. */
+    if (CPUMGetGuestCPL(pVCpu) != 0)
+    {
+        Log4(("EM: Refuse WRMSR: CPL != 0\n"));
+        return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
+    }
+
+    int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
+    if (rc != VINF_SUCCESS)
+    {
+        Assert(rc == VERR_CPUM_RAISE_GP_0);
+        Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
+        return VERR_EM_INTERPRETER;
+    }
+    LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
+             RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
+    NOREF(pVM);
+    return rc;
+}
+
+
 /**
  * Interpret CRx read.
@@ -3465,135 +3586,4 @@
 
 
-#ifdef LOG_ENABLED
-static const char *emMSRtoString(uint32_t uMsr)
-{
-    switch (uMsr)
-    {
-    case MSR_IA32_APICBASE:
-        return "MSR_IA32_APICBASE";
-    case MSR_IA32_CR_PAT:
-        return "MSR_IA32_CR_PAT";
-    case MSR_IA32_SYSENTER_CS:
-        return "MSR_IA32_SYSENTER_CS";
-    case MSR_IA32_SYSENTER_EIP:
-        return "MSR_IA32_SYSENTER_EIP";
-    case MSR_IA32_SYSENTER_ESP:
-        return "MSR_IA32_SYSENTER_ESP";
-    case MSR_K6_EFER:
-        return "MSR_K6_EFER";
-    case MSR_K8_SF_MASK:
-        return "MSR_K8_SF_MASK";
-    case MSR_K6_STAR:
-        return "MSR_K6_STAR";
-    case MSR_K8_LSTAR:
-        return "MSR_K8_LSTAR";
-    case MSR_K8_CSTAR:
-        return "MSR_K8_CSTAR";
-    case MSR_K8_FS_BASE:
-        return "MSR_K8_FS_BASE";
-    case MSR_K8_GS_BASE:
-        return "MSR_K8_GS_BASE";
-    case MSR_K8_KERNEL_GS_BASE:
-        return "MSR_K8_KERNEL_GS_BASE";
-    case MSR_K8_TSC_AUX:
-        return "MSR_K8_TSC_AUX";
-    case MSR_IA32_BIOS_SIGN_ID:
-        return "Unsupported MSR_IA32_BIOS_SIGN_ID";
-    case MSR_IA32_PLATFORM_ID:
-        return "Unsupported MSR_IA32_PLATFORM_ID";
-    case MSR_IA32_BIOS_UPDT_TRIG:
-        return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
-    case MSR_IA32_TSC:
-        return "MSR_IA32_TSC";
-    case MSR_IA32_MISC_ENABLE:
-        return "MSR_IA32_MISC_ENABLE";
-    case MSR_IA32_MTRR_CAP:
-        return "MSR_IA32_MTRR_CAP";
-    case MSR_IA32_MCP_CAP:
-        return "Unsupported MSR_IA32_MCP_CAP";
-    case MSR_IA32_MCP_STATUS:
-        return "Unsupported MSR_IA32_MCP_STATUS";
-    case MSR_IA32_MCP_CTRL:
-        return "Unsupported MSR_IA32_MCP_CTRL";
-    case MSR_IA32_MTRR_DEF_TYPE:
-        return "MSR_IA32_MTRR_DEF_TYPE";
-    case MSR_K7_EVNTSEL0:
-        return "Unsupported MSR_K7_EVNTSEL0";
-    case MSR_K7_EVNTSEL1:
-        return "Unsupported MSR_K7_EVNTSEL1";
-    case MSR_K7_EVNTSEL2:
-        return "Unsupported MSR_K7_EVNTSEL2";
-    case MSR_K7_EVNTSEL3:
-        return "Unsupported MSR_K7_EVNTSEL3";
-    case MSR_IA32_MC0_CTL:
-        return "Unsupported MSR_IA32_MC0_CTL";
-    case MSR_IA32_MC0_STATUS:
-        return "Unsupported MSR_IA32_MC0_STATUS";
-    case MSR_IA32_PERFEVTSEL0:
-        return "Unsupported MSR_IA32_PERFEVTSEL0";
-    case MSR_IA32_PERFEVTSEL1:
-        return "Unsupported MSR_IA32_PERFEVTSEL1";
-    case MSR_IA32_PERF_STATUS:
-        return "MSR_IA32_PERF_STATUS";
-    case MSR_IA32_PLATFORM_INFO:
-        return "MSR_IA32_PLATFORM_INFO";
-    case MSR_IA32_PERF_CTL:
-        return "Unsupported MSR_IA32_PERF_CTL";
-    case MSR_K7_PERFCTR0:
-        return "Unsupported MSR_K7_PERFCTR0";
-    case MSR_K7_PERFCTR1:
-        return "Unsupported MSR_K7_PERFCTR1";
-    case MSR_K7_PERFCTR2:
-        return "Unsupported MSR_K7_PERFCTR2";
-    case MSR_K7_PERFCTR3:
-        return "Unsupported MSR_K7_PERFCTR3";
-    case MSR_IA32_PMC0:
-        return "Unsupported MSR_IA32_PMC0";
-    case MSR_IA32_PMC1:
-        return "Unsupported MSR_IA32_PMC1";
-    case MSR_IA32_PMC2:
-        return "Unsupported MSR_IA32_PMC2";
-    case MSR_IA32_PMC3:
-        return "Unsupported MSR_IA32_PMC3";
-    }
-    return "Unknown MSR";
-}
-#endif /* LOG_ENABLED */
-
-
-/**
- * Interpret RDMSR
- *
- * @returns VBox status code.
- * @param   pVM         Pointer to the VM.
- * @param   pVCpu       Pointer to the VMCPU.
- * @param   pRegFrame   The register frame.
- */
-VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
-{
-    NOREF(pVM);
-
-    /* Get the current privilege level. */
-    if (CPUMGetGuestCPL(pVCpu) != 0)
-    {
-        Log4(("EM: Refuse RDMSR: CPL != 0\n"));
-        return VERR_EM_INTERPRETER; /* supervisor only */
-    }
-
-    uint64_t uValue;
-    int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
-    if (RT_UNLIKELY(rc != VINF_SUCCESS))
-    {
-        Assert(rc == VERR_CPUM_RAISE_GP_0);
-        Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
-        return VERR_EM_INTERPRETER;
-    }
-    pRegFrame->rax = (uint32_t) uValue;
-    pRegFrame->rdx = (uint32_t)(uValue >> 32);
-    LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
-    return rc;
-}
-
-
 /**
  * RDMSR Emulation.
@@ -3606,37 +3596,4 @@
     NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
     return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
-}
-
-
-/**
- * Interpret WRMSR
- *
- * @returns VBox status code.
- * @param   pVM         Pointer to the VM.
- * @param   pVCpu       Pointer to the VMCPU.
- * @param   pRegFrame   The register frame.
- */
-VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
-{
-    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
-
-    /* Check the current privilege level, this instruction is supervisor only. */
-    if (CPUMGetGuestCPL(pVCpu) != 0)
-    {
-        Log4(("EM: Refuse WRMSR: CPL != 0\n"));
-        return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
-    }
-
-    int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
-    if (rc != VINF_SUCCESS)
-    {
-        Assert(rc == VERR_CPUM_RAISE_GP_0);
-        Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
-        return VERR_EM_INTERPRETER;
-    }
-    LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
-             RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
-    NOREF(pVM);
-    return rc;
 }
 
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 45906)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 45907)
@@ -843,5 +843,5 @@
     {
         if (rc == VINF_SUCCESS)
-            rc = rc2;
+            rc = VBOXSTRICTRC_VAL(rc2);
 # ifndef IN_RING3
         VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
