VirtualBox

Changeset 45912 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
May 6, 2013 3:01:23 PM (12 years ago)
Author:
vboxsync
Message:

VMM/HMVMXR0: Return of the AssertRCReturns!

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r45908 r45912  
    18141814    AssertPtr(pVCpu);
    18151815
     1816    /** @todo Shouldn't we able to avoid initializing with 0? */
    18161817    int rc = VERR_GENERAL_FAILURE;
    18171818
    18181819    /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxLoadGuestControlRegs())*/
    1819     rc  = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
    1820 
    1821     rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
     1820    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);           AssertRCReturn(rc, rc);
     1821    rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);            AssertRCReturn(rc, rc);
    18221822
    18231823    /*
    … …  
    18261826     * We thus use the exception bitmap to control it rather than use both.
    18271827     */
    1828     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
    1829     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
     1828    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);       AssertRCReturn(rc, rc);
     1829    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);      AssertRCReturn(rc, rc);
    18301830
    18311831    /** @todo Explore possibility of using IO-bitmaps. */
    18321832    /* All IO & IOIO instructions cause VM-exits. */
    1833     rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
    1834     rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
     1833    rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);           AssertRCReturn(rc, rc);
     1834    rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);           AssertRCReturn(rc, rc);
     1835
     1836    /* Initialize the MSR-bitmap area. */
     1837    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);       AssertRCReturn(rc, rc);
     1838    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);       AssertRCReturn(rc, rc);
     1839    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT,  0);       AssertRCReturn(rc, rc);
    18351840
    18361841#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
    1837     /* Setup MSR autoloading/autostoring. */
     1842    /* Setup MSR autoloading/storing. */
    18381843    Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
    18391844    Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf));    /* Lower 4 bits MBZ. */
    1840     rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
    1841     rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
    1842     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
    1843     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
     1845    rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
     1846    AssertRCReturn(rc, rc);
     1847    rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
     1848    AssertRCReturn(rc, rc);
    18441849
    18451850    Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
    18461851    Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf));     /* Lower 4 bits MBZ. */
    1847     rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL,  pVCpu->hm.s.vmx.HCPhysHostMsr);
    1848     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
    1849 #else
    1850     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
    1851     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
    1852     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT,  0);
     1852    rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL,  pVCpu->hm.s.vmx.HCPhysHostMsr);
     1853    AssertRCReturn(rc, rc);
    18531854#endif
    18541855
    18551856    /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
    1856     rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
     1857    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
     1858    AssertRCReturn(rc, rc);
    18571859
    18581860    /* Setup debug controls */
    1859     rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0);        /** @todo We don't support IA32_DEBUGCTL MSR. Should we? */
    1860     rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
     1861    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0);        /** @todo We don't support IA32_DEBUGCTL MSR. Should we? */
     1862    AssertRCReturn(rc, rc);
     1863    rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
    18611864    AssertRCReturn(rc, rc);
    18621865    return rc;
    … …  
    20552058    RTCCUINTREG uReg = ASMGetCR0();
    20562059    int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
     2060    AssertRCReturn(rc, rc);
    20572061
    20582062#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
    … …  
    20612065    {
    20622066        uint64_t uRegCR3 = hmR0Get64bitCR3();
    2063         rc |= VMXWriteVmcs64(VMX_VMCS_HOST_CR3, uRegCR3);
     2067        rc = VMXWriteVmcs64(VMX_VMCS_HOST_CR3, uRegCR3);
    20642068    }
    20652069    else
    … …  
    20672071    {
    20682072        uReg = ASMGetCR3();
    2069         rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
    2070     }
     2073        rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
     2074    }
     2075    AssertRCReturn(rc, rc);
    20712076
    20722077    uReg = ASMGetCR4();
    2073     rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
     2078    rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
    20742079    AssertRCReturn(rc, rc);
    20752080    return rc;
    … …  
    21382143
    21392144    /* Write these host selector fields into the host-state area in the VMCS. */
    2140     rc =  VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_CS, uSelCS);
    2141     rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_SS, uSelSS);
     2145    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_CS, uSelCS);
     2146    AssertRCReturn(rc, rc);
     2147    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_SS, uSelSS);
     2148    AssertRCReturn(rc, rc);
    21422149    /* Avoid the VMWRITEs as we set the following segments to 0 and the VMCS fields are already  0 (since g_HvmR0 is static) */
    21432150#if 0
    2144     rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_DS, uSelDS);
    2145     rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_ES, uSelES);
    2146     rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_FS, uSelFS);
    2147     rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_GS, uSelGS);
     2151    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_DS, uSelDS);
     2152    AssertRCReturn(rc, rc);
     2153    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_ES, uSelES);
     2154    AssertRCReturn(rc, rc);
     2155    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_FS, uSelFS);
     2156    AssertRCReturn(rc, rc);
     2157    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_GS, uSelGS);
     2158    AssertRCReturn(rc, rc);
    21482159#endif
    2149     rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_TR, uSelTR);
     2160    rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_TR, uSelTR);
    21502161    AssertRCReturn(rc, rc);
    21512162
    … …  
    21652176        X86XDTR64 Idtr64;
    21662177        hmR0Get64bitGdtrAndIdtr(&Gdtr64, &Idtr64);
    2167         rc  = VMXWriteVmcs64(VMX_VMCS_HOST_GDTR_BASE, Gdtr64.uAddr);
    2168         rc |= VMXWriteVmcs64(VMX_VMCS_HOST_IDTR_BASE, Idtr64.uAddr);
     2178
     2179        rc = VMXWriteVmcs64(VMX_VMCS_HOST_GDTR_BASE, Gdtr64.uAddr);
     2180        AssertRCReturn(rc, rc);
     2181        rc = VMXWriteVmcs64(VMX_VMCS_HOST_IDTR_BASE, Idtr64.uAddr);
     2182        AssertRCReturn(rc, rc);
     2183
    21692184        Gdtr.cbGdt = Gdtr64.cb;
    21702185        Gdtr.pGdt  = (uintptr_t)Gdtr64.uAddr;
    … …  
    21762191        ASMGetGDTR(&Gdtr);
    21772192        ASMGetIDTR(&Idtr);
    2178         rc  = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
    2179         rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
    2180     }
    2181     AssertRCReturn(rc, rc);
     2193
     2194        rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
     2195        AssertRCReturn(rc, rc);
     2196        rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
     2197        AssertRCReturn(rc, rc);
     2198    }
    21822199
    21832200    /*
    … …  
    22222239        uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
    22232240        uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
    2224         rc  = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
    2225         rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
     2241        rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
     2242        AssertRCReturn(rc, rc);
     2243        rc = VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
    22262244        AssertRCReturn(rc, rc);
    22272245    }
    … …  
    23022320     * Host Sysenter MSRs.
    23032321     */
    2304     rc |= VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS,        ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
     2322    rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS,        ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
     2323    AssertRCReturn(rc, rc);
    23052324# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
    23062325    if (HMVMX_IS_64BIT_HOST_MODE())
    23072326    {
    2308         rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP,     ASMRdMsr(MSR_IA32_SYSENTER_ESP));
    2309         rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP,     ASMRdMsr(MSR_IA32_SYSENTER_EIP));
     2327        rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP,     ASMRdMsr(MSR_IA32_SYSENTER_ESP));
     2328        AssertRCReturn(rc, rc);
     2329        rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP,     ASMRdMsr(MSR_IA32_SYSENTER_EIP));
    23102330    }
    23112331    else
    23122332    {
    2313         rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP,     ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
    2314         rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP,     ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
     2333        rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP,     ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
     2334        AssertRCReturn(rc, rc);
     2335        rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP,     ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
    23152336    }
    23162337# elif HC_ARCH_BITS == 32
    2317     rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP,         ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
    2318     rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP,         ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
     2338    rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP,         ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
     2339    AssertRCReturn(rc, rc);
     2340    rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP,         ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
    23192341# else
    2320     rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP,         ASMRdMsr(MSR_IA32_SYSENTER_ESP));
    2321     rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP,         ASMRdMsr(MSR_IA32_SYSENTER_EIP));
     2342    rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP,         ASMRdMsr(MSR_IA32_SYSENTER_ESP));
     2343    AssertRCReturn(rc, rc);
     2344    rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP,         ASMRdMsr(MSR_IA32_SYSENTER_EIP));
    23222345# endif
    23232346    AssertRCReturn(rc, rc);
    … …  
    26812704 * @remarks No-long-jump zone!!!
    26822705 */
    2683 static int hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
     2706DECLINLINE(int) hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
    26842707{
    26852708    int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
    2686     rc    |= hmR0VmxLoadGuestRsp(pVCpu, pMixedCtx);
    2687     rc    |= hmR0VmxLoadGuestRflags(pVCpu, pMixedCtx);
     2709    AssertRCReturn(rc, rc);
     2710    rc     = hmR0VmxLoadGuestRsp(pVCpu, pMixedCtx);
     2711    AssertRCReturn(rc, rc);
     2712    rc     = hmR0VmxLoadGuestRflags(pVCpu, pMixedCtx);
     2713    AssertRCReturn(rc, rc);
    26882714    return rc;
    26892715}
    … …  
    28232849
    28242850        /* Write VT-x's view of the guest CR0 into the VMCS and update the exception bitmap. */
    2825         rc  = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0);
    2826         rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
     2851        rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0);
     2852        AssertRCReturn(rc, rc);
     2853        rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
     2854        AssertRCReturn(rc, rc);
    28272855        Log(("Load: VMX_VMCS_GUEST_CR0=%#RX32 (uSetCR0=%#RX32 uZapCR0=%#RX32)\n", u32GuestCR0, uSetCR0, uZapCR0));
    28282856
    … …  
    28532881        /* Write the CR0 mask into the VMCS and update the VCPU's copy of the current CR0 mask. */
    28542882        pVCpu->hm.s.vmx.cr0_mask = u32CR0Mask;
    2855         rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
     2883        rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
    28562884        AssertRCReturn(rc, rc);
    28572885
    … …  
    28982926                if (CPUMIsGuestInPAEModeEx(pCtx))
    28992927                {
    2900                     rc  = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
    2901                     rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
    2902                     rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
    2903                     rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
    2904                     rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
     2928                    rc  = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);                         AssertRCReturn(rc, rc);
     2929                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);     AssertRCReturn(rc, rc);
     2930                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);     AssertRCReturn(rc, rc);
     2931                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);     AssertRCReturn(rc, rc);
     2932                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);     AssertRCReturn(rc, rc);
    29052933                    AssertRCReturn(rc, rc);
    29062934                }
    … …  
    30253053        Log(("Load: VMX_VMCS_GUEST_CR4=%#RX32 (Set=%#RX32 Zap=%#RX32)\n", u32GuestCR4, uSetCR4, uZapCR4));
    30263054        rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCR4);
     3055        AssertRCReturn(rc, rc);
    30273056
    30283057        /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM exit. */
    … …  
    30343063                    | X86_CR4_VMXE;
    30353064        pVCpu->hm.s.vmx.cr4_mask = u32CR4Mask;
    3036         rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
     3065        rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
    30373066        AssertRCReturn(rc, rc);
    30383067
    … …  
    31323161        pVCpu->hm.s.vmx.u32ProcCtls   &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
    31333162
    3134     rc  = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP,   pVCpu->hm.s.vmx.u32XcptBitmap);
    3135     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u32ProcCtls);
     3163    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP,   pVCpu->hm.s.vmx.u32XcptBitmap);
     3164    AssertRCReturn(rc, rc);
     3165    rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u32ProcCtls);
     3166    AssertRCReturn(rc, rc);
    31363167
    31373168    /* The guest's view of its DR7 is unblemished. */
    3138     rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
     3169    rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
     3170    AssertRCReturn(rc, rc);
    31393171
    31403172    pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
    … …  
    33343366                                       uint32_t idxAccess, PCPUMSELREG pSelReg, PCPUMCTX pCtx)
    33353367{
    3336     int rc;
    3337     rc  = VMXWriteVmcs32(idxSel,    pSelReg->Sel);       /* 16-bit guest selector field. */
    3338     rc |= VMXWriteVmcs32(idxLimit,  pSelReg->u32Limit);  /* 32-bit guest segment limit field. */
    3339     rc |= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base);   /* Natural width guest segment base field.*/
     3368    int rc = VMXWriteVmcs32(idxSel,    pSelReg->Sel);       /* 16-bit guest selector field. */
     3369    AssertRCReturn(rc, rc);
     3370    rc     = VMXWriteVmcs32(idxLimit,  pSelReg->u32Limit);  /* 32-bit guest segment limit field. */
     3371    AssertRCReturn(rc, rc);
     3372    rc     = VMXWriteVmcsGstN(idxBase, pSelReg->u64Base);   /* Natural width guest segment base field.*/
    33403373    AssertRCReturn(rc, rc);
    33413374
    … …  
    34213454        }
    34223455#endif
    3423         rc  = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_CS, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
     3456        rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_CS, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
    34243457                                     VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS, &pMixedCtx->cs, pMixedCtx);
    3425         rc |= hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_SS, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
     3458        AssertRCReturn(rc, rc);
     3459        rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_SS, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
    34263460                                     VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS, &pMixedCtx->ss, pMixedCtx);
    3427         rc |= hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_DS, VMX_VMCS32_GUEST_DS_LIMIT, VMX_VMCS_GUEST_DS_BASE,
     3461        AssertRCReturn(rc, rc);
     3462        rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_DS, VMX_VMCS32_GUEST_DS_LIMIT, VMX_VMCS_GUEST_DS_BASE,
    34283463                                     VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS, &pMixedCtx->ds, pMixedCtx);
    3429         rc |= hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_ES, VMX_VMCS32_GUEST_ES_LIMIT, VMX_VMCS_GUEST_ES_BASE,
     3464        AssertRCReturn(rc, rc);
     3465        rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_ES, VMX_VMCS32_GUEST_ES_LIMIT, VMX_VMCS_GUEST_ES_BASE,
    34303466                                     VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, &pMixedCtx->es, pMixedCtx);
    3431         rc |= hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_FS, VMX_VMCS32_GUEST_FS_LIMIT, VMX_VMCS_GUEST_FS_BASE,
     3467        AssertRCReturn(rc, rc);
     3468        rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_FS, VMX_VMCS32_GUEST_FS_LIMIT, VMX_VMCS_GUEST_FS_BASE,
    34323469                                     VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS, &pMixedCtx->fs, pMixedCtx);
    3433         rc |= hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_GS, VMX_VMCS32_GUEST_GS_LIMIT, VMX_VMCS_GUEST_GS_BASE,
     3470        AssertRCReturn(rc, rc);
     3471        rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_GS, VMX_VMCS32_GUEST_GS_LIMIT, VMX_VMCS_GUEST_GS_BASE,
    34343472                                     VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS, &pMixedCtx->gs, pMixedCtx);
    34353473        AssertRCReturn(rc, rc);
    … …  
    34983536               || (u32AccessRights & RT_BIT(15)));              /* Granularity MB1. */
    34993537
    3500         rc  = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_TR,         u16Sel);
    3501         rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT,         u32Limit);
    3502         rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE,          u64Base);
    3503         rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
    3504         AssertRCReturn(rc, rc);
     3538        rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_TR,         u16Sel);                AssertRCReturn(rc, rc);
     3539        rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT,         u32Limit);              AssertRCReturn(rc, rc);
     3540        rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE,          u64Base);               AssertRCReturn(rc, rc);
     3541        rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);       AssertRCReturn(rc, rc);
    35053542
    35063543        Log(("Load: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", u64Base));
    … …  
    35133550    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
    35143551    {
    3515         rc  = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);
    3516         rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE,  pMixedCtx->gdtr.pGdt);
    3517         AssertRCReturn(rc, rc);
     3552        rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);        AssertRCReturn(rc, rc);
     3553        rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE,  pMixedCtx->gdtr.pGdt);         AssertRCReturn(rc, rc);
    35183554
    35193555        Assert(!(pMixedCtx->gdtr.cbGdt & UINT64_C(0xffff0000)));       /* Bits 31:16 MBZ. */
    … …  
    35343570            u32Access = pMixedCtx->ldtr.Attr.u;
    35353571
    3536         rc  = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_LDTR,         pMixedCtx->ldtr.Sel);
    3537         rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT,         pMixedCtx->ldtr.u32Limit);
    3538         rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE,          pMixedCtx->ldtr.u64Base);
    3539         rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
    3540         AssertRCReturn(rc, rc);
     3572        rc  = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_LDTR,         pMixedCtx->ldtr.Sel);         AssertRCReturn(rc, rc);
     3573        rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT,         pMixedCtx->ldtr.u32Limit);    AssertRCReturn(rc, rc);
     3574        rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE,          pMixedCtx->ldtr.u64Base);     AssertRCReturn(rc, rc);
     3575        rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);                   AssertRCReturn(rc, rc);
    35413576
    35423577        /* Validate. */
    … …  
    35643599    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
    35653600    {
    3566         rc  = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);
    3567         rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE,  pMixedCtx->idtr.pIdt);
    3568         AssertRCReturn(rc, rc);
     3601        rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);         AssertRCReturn(rc, rc);
     3602        rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE,  pMixedCtx->idtr.pIdt);          AssertRCReturn(rc, rc);
    35693603
    35703604        Assert(!(pMixedCtx->idtr.cbIdt & UINT64_C(0xffff0000)));       /* Bits 31:16 MBZ. */
    … …  
    36663700        /* Update the VCPU's copy of the guest MSR count. */
    36673701        pVCpu->hm.s.vmx.cGuestMsrs = cGuestMsrs;
    3668         rc  = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cGuestMsrs);
    3669         rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cGuestMsrs);
    3670         AssertRCReturn(rc, rc);
     3702        rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cGuestMsrs);          AssertRCReturn(rc, rc);
     3703        rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cGuestMsrs);          AssertRCReturn(rc, rc);
    36713704#endif  /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
    36723705
    … …  
    36813714    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
    36823715    {
    3683         rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS,   pMixedCtx->SysEnter.cs);
     3716        rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS,   pMixedCtx->SysEnter.cs);    AssertRCReturn(rc, rc);
    36843717        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_CS_MSR;
    36853718    }
    36863719    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
    36873720    {
    3688         rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip);
     3721        rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip);    AssertRCReturn(rc, rc);
    36893722        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR;
    36903723    }
    36913724    if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
    36923725    {
    3693         rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp);
     3726        rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp);    AssertRCReturn(rc, rc);
    36943727        pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR;
    36953728    }
    3696     AssertRCReturn(rc, rc);
    36973729
    36983730    return rc;
    … …  
    47624794        uint32_t uVal    = 0;
    47634795        uint32_t uShadow = 0;
    4764         rc  = VMXReadVmcs32(VMX_VMCS_GUEST_CR4,            &uVal);
    4765         rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uShadow);
     4796        rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4,            &uVal);
    47664797        AssertRCReturn(rc, rc);
     4798        rc = VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uShadow);
     4799        AssertRCReturn(rc, rc);
     4800
    47674801        uVal = (uShadow & pVCpu->hm.s.vmx.cr4_mask) | (uVal & ~pVCpu->hm.s.vmx.cr4_mask);
    47684802        CPUMSetGuestCR4(pVCpu, uVal);
    … …  
    47924826        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &uVal);
    47934827        AssertRCReturn(rc, rc);
     4828
    47944829        pMixedCtx->rip = uVal;
    47954830        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RIP;
    … …  
    48184853        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &uVal);
    48194854        AssertRCReturn(rc, rc);
     4855
    48204856        pMixedCtx->rsp = uVal;
    48214857        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RSP;
    … …  
    48434879        int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &uVal);
    48444880        AssertRCReturn(rc, rc);
     4881
    48454882        pMixedCtx->eflags.u32 = uVal;
    4846 
    4847         /* Undo our real-on-v86-mode changes to eflags if necessary. */
    4848         if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
    4849         {
    4850             PVM pVM = pVCpu->CTX_SUFF(pVM);
    4851             Assert(pVM->hm.s.vmx.pRealModeTSS);
    4852             Log(("Saving real-mode RFLAGS VT-x view=%#RX64\n", pMixedCtx->rflags.u64));
     4883        if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)        /* Undo our real-on-v86-mode changes to eflags if necessary. */
     4884        {
     4885            Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
     4886            Log(("Saving real-mode EFLAGS VT-x view=%#RX32\n", pMixedCtx->eflags.u32));
     4887
    48534888            pMixedCtx->eflags.Bits.u1VM   = 0;
    48544889            pMixedCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.eflags.Bits.u2IOPL;
    … …  
    48984933               || uIntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
    48994934        rc  = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
    4900         rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);    /* for hmR0VmxGetGuestIntrState(). */
    49014935        AssertRC(rc);
     4936        rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);    /* for hmR0VmxGetGuestIntrState(). */
     4937        AssertRC(rc);
     4938
    49024939        EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
    49034940        Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
    … …  
    50775114    /* Guest CR0. Guest FPU. */
    50785115    int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
     5116    AssertRCReturn(rc, rc);
    50795117
    50805118    /* Guest CR4. */
    5081     rc |= hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
     5119    rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
    50825120    AssertRCReturn(rc, rc);
    50835121
    … …  
    50995137
    51005138            /* We require EFER to check PAE mode. */
    5101             rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
     5139            rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
     5140            AssertRCReturn(rc, rc);
    51025141
    51035142            /* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
    51045143            if (CPUMIsGuestInPAEModeEx(pMixedCtx))  /* Reads CR0, CR4 and EFER MSR. */
    51055144            {
    5106                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
    5107                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
    5108                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
    5109                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
     5145                rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);        AssertRCReturn(rc, rc);
     5146                rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);        AssertRCReturn(rc, rc);
     5147                rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);        AssertRCReturn(rc, rc);
     5148                rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);        AssertRCReturn(rc, rc);
    51105149                /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMGstUpdatePaePdpes(). */
    51115150                VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
    51125151            }
    5113             AssertRCReturn(rc, rc);
    51145152        }
    51155153
    … …  
    52625300    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GDTR))
    52635301    {
    5264         rc  = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &uGCVal);
    5265         rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);  AssertRCReturn(rc, rc);
     5302        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &uGCVal);        AssertRCReturn(rc, rc);
     5303        rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);       AssertRCReturn(rc, rc);
    52665304        pMixedCtx->gdtr.pGdt  = uGCVal;
    52675305        pMixedCtx->gdtr.cbGdt = u32Val;
    … …  
    52725310    if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_IDTR))
    52735311    {
    5274         rc  = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &uGCVal);
    5275         rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);   AssertRCReturn(rc, rc);
     5312        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &uGCVal);        AssertRCReturn(rc, rc);
     5313        rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);       AssertRCReturn(rc, rc);
    52765314        pMixedCtx->idtr.pIdt  = uGCVal;
    52775315        pMixedCtx->idtr.cbIdt = u32Val;
    … …  
    52835321    {
    52845322        rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
     5323        AssertRCReturn(rc, rc);
    52855324
    52865325        /* For real-mode emulation using virtual-8086 mode we have the fake TSS (pRealModeTSS) in TR, don't save the fake one. */
    52875326        if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
    5288             rc |= VMXLOCAL_READ_SEG(TR, tr);
    5289         AssertRCReturn(rc, rc);
     5327        {
     5328            rc = VMXLOCAL_READ_SEG(TR, tr);
     5329            AssertRCReturn(rc, rc);
     5330        }
    52905331        pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_TR;
    52915332    }
    … …  
    59375978                 */
    59385979                rc2 = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
     5980                AssertRCReturn(rc, rc);
    59395981            }
    59405982        }
    … …  
    59515993     * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
    59525994     */
    5953     rc2 |= hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
     5995    rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
    59545996    AssertRC(rc2);
    59555997
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