Changeset 45947 in vbox for trunk/include/VBox/vmm

Timestamp:

May 8, 2013 12:27:58 PM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

85594

Message:

VMM: HM cleanup for CTRL, CONTROLS in symbolic names.

Location:

trunk/include/VBox/vmm

Files:

• hm_vmx.h (modified) (4 diffs)
• hm_vmx.mac (modified) (3 diffs)

trunk/include/VBox/vmm/hm_vmx.h

@@ -872 +872 @@
 #define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH                           0x2011
 
-/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
+/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
 #define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL                       0x2012
 #define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH                       0x2013
@@ -925 +925 @@
  * @{
  */
-#define VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS                       0x4000
-#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS                      0x4002
+#define VMX_VMCS32_CTRL_PIN_EXEC                                0x4000
+#define VMX_VMCS32_CTRL_PROC_EXEC                               0x4002
 #define VMX_VMCS32_CTRL_EXCEPTION_BITMAP                        0x4004
 #define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK                    0x4006
 #define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH                   0x4008
 #define VMX_VMCS32_CTRL_CR3_TARGET_COUNT                        0x400A
-#define VMX_VMCS32_CTRL_EXIT_CONTROLS                           0x400C
+#define VMX_VMCS32_CTRL_EXIT                                    0x400C
 #define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT                    0x400E
 #define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT                     0x4010
-#define VMX_VMCS32_CTRL_ENTRY_CONTROLS                          0x4012
+#define VMX_VMCS32_CTRL_ENTRY                                   0x4012
 #define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT                    0x4014
 #define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO                 0x4016
@@ -940 +940 @@
 #define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH                      0x401A
 #define VMX_VMCS32_CTRL_TPR_THRESHOLD                           0x401C
-#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2                     0x401E
-/** @} */
-
-
-/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
+#define VMX_VMCS32_CTRL_PROC_EXEC2                              0x401E
+/** @} */
+
+
+/** @name VMX_VMCS_CTRL_PIN_EXEC
  * @{
  */
 /** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
-#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT            RT_BIT(0)
+#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT            RT_BIT(0)
 /** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
-#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT                RT_BIT(3)
+#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT                RT_BIT(3)
 /** Virtual NMIs. */
-#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI             RT_BIT(5)
+#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI             RT_BIT(5)
 /** Activate VMX preemption timer. */
-#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER           RT_BIT(6)
+#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER           RT_BIT(6)
 /* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
 /** @} */
 
-/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
+/** @name VMX_VMCS_CTRL_PROC_EXEC
  * @{
  */
 /** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT        RT_BIT(2)
+#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT        RT_BIT(2)
 /** Use timestamp counter offset. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TSC_OFFSETTING     RT_BIT(3)
+#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING     RT_BIT(3)
 /** VM Exit when executing the HLT instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT               RT_BIT(7)
+#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT               RT_BIT(7)
 /** VM Exit when executing the INVLPG instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT            RT_BIT(9)
+#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT            RT_BIT(9)
 /** VM Exit when executing the MWAIT instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT             RT_BIT(10)
+#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT             RT_BIT(10)
 /** VM Exit when executing the RDPMC instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT             RT_BIT(11)
+#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT             RT_BIT(11)
 /** VM Exit when executing the RDTSC/RDTSCP instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT             RT_BIT(12)
+#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT             RT_BIT(12)
 /** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT          RT_BIT(15)
+#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT          RT_BIT(15)
 /** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT         RT_BIT(16)
+#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT         RT_BIT(16)
 /** VM Exit on CR8 loads. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT          RT_BIT(19)
+#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT          RT_BIT(19)
 /** VM Exit on CR8 stores. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT         RT_BIT(20)
+#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT         RT_BIT(20)
 /** Use TPR shadow. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW         RT_BIT(21)
+#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW         RT_BIT(21)
 /** VM Exit when virtual nmi blocking is disabled. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT        RT_BIT(22)
+#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT        RT_BIT(22)
 /** VM Exit when executing a MOV DRx instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT            RT_BIT(23)
+#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT            RT_BIT(23)
 /** VM Exit when executing IO instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT         RT_BIT(24)
+#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT         RT_BIT(24)
 /** Use IO bitmaps. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS         RT_BIT(25)
+#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS         RT_BIT(25)
 /** Monitor trap flag. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG      RT_BIT(27)
+#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG      RT_BIT(27)
 /** Use MSR bitmaps. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS        RT_BIT(28)
+#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS        RT_BIT(28)
 /** VM Exit when executing the MONITOR instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT           RT_BIT(29)
+#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT           RT_BIT(29)
 /** VM Exit when executing the PAUSE instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT             RT_BIT(30)
+#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT             RT_BIT(30)
 /** Determines whether the secondary processor based VM-execution controls are used. */
 #define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL         RT_BIT(31)
 /** @} */
 
-/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
+/** @name VMX_VMCS_CTRL_PROC_EXEC2
  * @{
  */
@@ -1035 +1035 @@
 
 
-/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
+/** @name VMX_VMCS_CTRL_ENTRY
  * @{
  */
 /** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG                 RT_BIT(2)
+#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG                 RT_BIT(2)
 /** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST           RT_BIT(9)
+#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST           RT_BIT(9)
 /** In SMM mode after VM-entry. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM                  RT_BIT(10)
+#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM                  RT_BIT(10)
 /** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON         RT_BIT(11)
+#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON         RT_BIT(11)
 /** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR        RT_BIT(13)
+#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR        RT_BIT(13)
 /** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR         RT_BIT(14)
+#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR         RT_BIT(14)
 /** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
-#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR        RT_BIT(15)
-/** @} */
-
-
-/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
+#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR        RT_BIT(15)
+/** @} */
+
+
+/** @name VMX_VMCS_CTRL_EXIT
  * @{
  */
 /** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG                  RT_BIT(2)
+#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG                  RT_BIT(2)
 /** Return to long mode after a VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE        RT_BIT(9)
+#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE        RT_BIT(9)
 /** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR               RT_BIT(12)
+#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR               RT_BIT(12)
 /** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT                 RT_BIT(15)
+#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT                 RT_BIT(15)
 /** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR          RT_BIT(18)
+#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR          RT_BIT(18)
 /** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR           RT_BIT(19)
+#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR           RT_BIT(19)
 /** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR         RT_BIT(20)
+#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR         RT_BIT(20)
 /** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR          RT_BIT(21)
+#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR          RT_BIT(21)
 /** This control determines whether the value of the VMX preemption timer is
  *  saved on every VM exit. */
-#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER      RT_BIT(22)
+#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER      RT_BIT(22)
 /** @} */
 

trunk/include/VBox/vmm/hm_vmx.mac

@@ -61 +61 @@
 %define VMX_VMCS_GUEST_DEBUGCTL_FULL                            02802h
 %define VMX_VMCS_GUEST_DEBUGCTL_HIGH                            02803h
-%define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS                         04000h
-%define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS                        04002h
+%define VMX_VMCS_CTRL_PIN_EXEC                                  04000h
+%define VMX_VMCS_CTRL_PROC_EXEC                                 04002h
 %define VMX_VMCS_CTRL_EXCEPTION_BITMAP                          04004h
 %define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK                      04006h
 %define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH                     04008h
 %define VMX_VMCS_CTRL_CR3_TARGET_COUNT                          0400Ah
-%define VMX_VMCS_CTRL_EXIT_CONTROLS                             0400Ch
+%define VMX_VMCS_CTRL_EXIT                                      0400Ch
 %define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT                      0400Eh
 %define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT                       04010h
-%define VMX_VMCS_CTRL_ENTRY_CONTROLS                            04012h
+%define VMX_VMCS_CTRL_ENTRY                                     04012h
 %define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT                      04014h
 %define VMX_VMCS_CTRL_ENTRY_IRQ_INFO                            04016h
@@ -119 +119 @@
 %define VMX_VMCS_RO_IO_RIP                                      06408h
 %define VMX_VMCS_GUEST_LINEAR_ADDR                              0640Ah
-%define VMX_VMCS64_GUEST_CR0                                      06800h
-%define VMX_VMCS64_GUEST_CR3                                      06802h
-%define VMX_VMCS64_GUEST_CR4                                      06804h
-%define VMX_VMCS64_GUEST_ES_BASE                                  06806h
-%define VMX_VMCS64_GUEST_CS_BASE                                  06808h
-%define VMX_VMCS64_GUEST_SS_BASE                                  0680Ah
-%define VMX_VMCS64_GUEST_DS_BASE                                  0680Ch
-%define VMX_VMCS64_GUEST_FS_BASE                                  0680Eh
-%define VMX_VMCS64_GUEST_GS_BASE                                  06810h
-%define VMX_VMCS64_GUEST_LDTR_BASE                                06812h
-%define VMX_VMCS64_GUEST_TR_BASE                                  06814h
-%define VMX_VMCS64_GUEST_GDTR_BASE                                06816h
-%define VMX_VMCS64_GUEST_IDTR_BASE                                06818h
-%define VMX_VMCS64_GUEST_DR7                                      0681Ah
-%define VMX_VMCS64_GUEST_RSP                                      0681Ch
-%define VMX_VMCS64_GUEST_RIP                                      0681Eh
-%define VMX_VMCS64_GUEST_RFLAGS                                   06820h
+%define VMX_VMCS64_GUEST_CR0                                    06800h
+%define VMX_VMCS64_GUEST_CR3                                    06802h
+%define VMX_VMCS64_GUEST_CR4                                    06804h
+%define VMX_VMCS64_GUEST_ES_BASE                                06806h
+%define VMX_VMCS64_GUEST_CS_BASE                                06808h
+%define VMX_VMCS64_GUEST_SS_BASE                                0680Ah
+%define VMX_VMCS64_GUEST_DS_BASE                                0680Ch
+%define VMX_VMCS64_GUEST_FS_BASE                                0680Eh
+%define VMX_VMCS64_GUEST_GS_BASE                                06810h
+%define VMX_VMCS64_GUEST_LDTR_BASE                              06812h
+%define VMX_VMCS64_GUEST_TR_BASE                                06814h
+%define VMX_VMCS64_GUEST_GDTR_BASE                              06816h
+%define VMX_VMCS64_GUEST_IDTR_BASE                              06818h
+%define VMX_VMCS64_GUEST_DR7                                    0681Ah
+%define VMX_VMCS64_GUEST_RSP                                    0681Ch
+%define VMX_VMCS64_GUEST_RIP                                    0681Eh
+%define VMX_VMCS64_GUEST_RFLAGS                                 06820h
 %define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS                         06822h
-%define VMX_VMCS64_GUEST_SYSENTER_ESP                             06824h
-%define VMX_VMCS64_GUEST_SYSENTER_EIP                             06826h
+%define VMX_VMCS64_GUEST_SYSENTER_ESP                           06824h
+%define VMX_VMCS64_GUEST_SYSENTER_EIP                           06826h
 %define VMX_VMCS_HOST_CR0                                       06C00h
 %define VMX_VMCS_HOST_CR3                                       06C02h
@@ -152 +152 @@
 %define VMX_VMCS_HOST_RIP                                       06C16h
 
-%define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64                  RT_BIT(9)