Changeset 46004 in vbox

Timestamp:

May 13, 2013 9:20:43 AM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

85665

Message:

VMM/HMVMXR0: DR7 is 32-bit in reality, upper bits are reserved MBZ, so avoid complicated guest-natural width writes and going through the VMCS cache unnecessarily.

Location:

trunk

Files:

• include/VBox/vmm/hm_vmx.h (modified) (1 diff)
• src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (7 diffs)

trunk/include/VBox/vmm/hm_vmx.h

@@ -51 +51 @@
 # define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX                                   8
 # define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX                                   9
-# define VMX_VMCS_GUEST_DR7_CACHE_IDX                                         10
-# define VMX_VMCS_GUEST_RSP_CACHE_IDX                                         11
-# define VMX_VMCS_GUEST_RIP_CACHE_IDX                                         12
-# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX                                13
-# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX                                14
-# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX                             15
+# define VMX_VMCS_GUEST_RSP_CACHE_IDX                                         10
+# define VMX_VMCS_GUEST_RIP_CACHE_IDX                                         11
+# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX                                12
+# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX                                13
+# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX                             14
 # define VMX_VMCS_MAX_CACHE_IDX                                               (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
-# define VMX_VMCS_GUEST_CR3_CACHE_IDX                                         16
+# define VMX_VMCS_GUEST_CR3_CACHE_IDX                                         15
 # define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX                                 (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
 #else /* VBOX_WITH_OLD_VTX_CODE */

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -3164 +3164 @@
     AssertRCReturn(rc, rc);
 
-    /* The guest's view of its DR7 is unblemished. */
-    rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
+    /* The guest's view of its DR7 is unblemished. Use 32-bit write as upper 32-bits MBZ as asserted above. */
+    rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pMixedCtx->dr[7]);
     AssertRCReturn(rc, rc);
 
@@ -4036 +4036 @@
         case VMX_VMCS_GUEST_RIP:
         case VMX_VMCS_GUEST_RSP:
-        case VMX_VMCS_GUEST_DR7:
         case VMX_VMCS_GUEST_SYSENTER_EIP:
         case VMX_VMCS_GUEST_SYSENTER_ESP:
@@ -4266 +4265 @@
     VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
     VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
-    VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DR7);
     VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
     VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
@@ -4383 +4381 @@
         case VMX_VMCS_GUEST_GDTR_BASE:
         case VMX_VMCS_GUEST_IDTR_BASE:
-        case VMX_VMCS_GUEST_DR7:
         case VMX_VMCS_GUEST_RSP:
         case VMX_VMCS_GUEST_RIP:
@@ -5384 +5381 @@
     if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_DEBUG))
     {
-        RTGCUINTREG uVal;
-        rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_DR7, &uVal);          AssertRCReturn(rc, rc);
-        pMixedCtx->dr[7] = uVal;
+        /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
+        uint32_t u32Val;
+        rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val);        AssertRCReturn(rc, rc);
+        pMixedCtx->dr[7] = u32Val;
 
         pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_DEBUG;
@@ -6620 +6618 @@
      * interrupts and handle returning to ring-3 afterwards, but requires very careful state restoration.
      */
-    /** @todo Rework event evaluation and injection to be complete separate. */
+    /** @todo Rework event evaluation and injection to be completely separate. */
     if (TRPMHasTrap(pVCpu))
         hmR0VmxTRPMTrapToPendingEvent(pVCpu);
@@ -8615 +8613 @@
 
         /* Paranoia. */
-        pMixedCtx->dr[7] &= 0xffffffff;                                              /* upper 32 bits reserved */
+        pMixedCtx->dr[7] &= UINT32_C(0xffffffff);                                    /* upper 32 bits MBZ. */
         pMixedCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15));    /* must be zero */
         pMixedCtx->dr[7] |= 0x400;                                                   /* must be one */
 
-        rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
+        rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pMixedCtx->dr[7]);
         AssertRCReturn(rc,rc);